MC4HC4B -Bit Serial-Input/Parallel- Output Shift egister High Performance Silicon Gate CMOS The MC4HC4B is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The MC4HC4B is an bit, serial input to parallel output shift register. Two serial data inputs, A and A2, are provided so that one input may be used as a data enable. ata is entered on each rising edge of the clock. The active low asynchronous eset overrides the Clock and Serial ata inputs. Schmitt trigger action at the Clock input enhances the device s tolerance to slower rise and fall times and immunity to noise of the input clock signal. 4 4 SOIC 4 SUFFIX CASE 5A MAKING IAGAMS HC4BG AWLYWW Features Output rive Capability: 0 LSTTL Loads Outputs irectly Interface to CMOS, NMOS, and TTL Operating oltage ange: to Low Input Current: A High Noise Immunity Characteristic of CMOS evices In Compliance with the JEEC Standard No. A equirements Chip Complexity: 244 FETs or Equivalent Gates NL Prefix for Automotive and Other Applicatio equiring Unique Site and Control Change equirements; AEC 00 ualified and PPAP Capable These evices are Pb Free, Halogen Free/BF Free and are ohs Compliant 4 TSSOP 4 T SUFFIX CASE 4G A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or = Pb Free Package OEING INFOMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. 4 HC 4B ALYW (Note: Microdot may be in either location) Semiconductor Components Industries, LLC, March, ev. 2 Publication Order Number: MC4HC4B/
MC4HC4B PIN ASSIGNMENT LOGIC IAGAM A A2 A B C GN 2 4 5 4 2 0 CC H G F E ESET SEIAL ATA INPUTS A A2 2 ATA 4 5 0 2 A B C E F G H PAALLEL ATA OUTPUTS ESET PIN 4 = CC PIN = GN FUNCTION TABLE Inputs Outputs eset Clock A A2 A B H L X X X L L L H X X No Change H H An Gn H H An Gn = data input An Gn = data shifted from the preceding stage on a rising edge at the clock input. OEING INFOMATION evice Package Shipping MC4HC4BG MC4HC4B2G NL4HC4B2G* SOIC 4 (Pb Free) 55 Units / ail 2500 / Tape & eel 2500 / Tape & eel MC4HC4BT2G NL4HC4BT2G* TSSOP 4 (Pb Free) 2500 / Tape & eel 2500 / Tape & eel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specificatio Brochure, B0/. *NL Prefix for Automotive and Other Applicatio equiring Unique Site and Control Change equirements; AEC 00 ualified and PPAP Capable 2
MC4HC4B MAXIMUM ATINGS Symbol Parameter alue Unit CC C Supply oltage (eferenced to GN) 0.5 to +.0 in C Input oltage (eferenced to GN) 0.5 to CC + 0.5 out C Output oltage (eferenced to GN) 0.5 to CC + 0.5 I in C Input Current, per Pin ± ma I out C Output Current, per Pin ± 25 ma I CC C Supply Current, CC and GN Pi ± 50 ma P Power issipation in Still Air, SOIC Package TSSOP Package 500 450 T stg Storage Temperature 5 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds (SOIC or TSSOP Package) 20 mw C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or CC ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum atings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. erating SOIC Package: mw/ C from 5 to 25 C TSSOP Package:. mw/ C from 5 to 25 C ECOMMENE OPEATING CONITIONS Symbol Parameter Min Max Unit CC C Supply oltage (eferenced to GN) in, out C Input oltage, Output oltage (eferenced to GN) 0 CC T A Operating Temperature, All Package Types 55 + 25 C t r, t f Input ise and Fall Time CC = (Figure ) CC = CC = 0 0 0 No Limit No Limit No Limit Functional operation above the stresses listed in the ecommended Operating anges is not implied. Extended exposure to stresses beyond the ecommended Operating anges limits may affect device reliability.
MC4HC4B C ELECTICAL CHAACTEISTICS (oltages eferenced to GN) Symbol Parameter Test Conditio T+ max T+ min T max T min H max (Note ) H min (Note ) OH OL Maximum Positive Going Input Threshold oltage (Figure ) Minimum Positive Going Input Threshold oltage (Figure ) Maximum Negative Going Input Threshold oltage (Figure ) Minimum Negative Going Input Threshold oltage (Figure ) Maximum Hysteresis oltage (Figure ) Minimum Hysteresis oltage (Figure ) Minimum High Level Output oltage Maximum Low Level Output oltage out = 0. I out A out = 0. I out A out = CC 0. I out A out = CC 0. I out A out = 0. or CC 0. I out A out = 0. or CC 0. I out A in = IH or IL I out A in = IH or IL in = IH or IL I out A in = IH or IL I out 2.4 ma I out 4.0 ma I out 5.2 ma I out 2.4 ma I out 4.0 ma I out 5.2 ma CC.0.0.0.0 Guaranteed Limit 55 C to 25 C 5 C 25 C I in Maximum Input Leakage Current in = CC or GN ± 0. ±.0 ±.0 A I CC Maximum uiescent Supply Current (per Package) in = CC or GN I out = 0 A.0.0.0.0.50 2.5.5 4..0.5 2..0 0..4 2. 0. 0.5 0..2..5.00 0. 0.25 0.50. 4.4 5. 2.4. 5.4 0. 0. 0. 0.2 0.2 0.2.50 2.5.5 4. 0.5.45 2.5 0.5.45 5 2.5 0. 0.5 0..2..5.00 0. 0.25 0.50. 4.4 5. 2.4.4 5.4 0. 0. 0. 0. 0. 0..50 2.5.5 4. 0.5.45 2.5 0.5.45 5 2.5 0. 0.5 0..2..5.00 0. 0.25 0.50. 4.4 5. 2..0 5. 0. 0. 0. Unit 4 40 0 A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio.. H min > ( T+ min) ( T max); H max = ( T+ max) ( T min). 4
MC4HC4B AC ELECTICAL CHAACTEISTICS (C L = 50 pf, Input t r = t f = ) Symbol f max t PLH, t PHL t PHL t TLH, t THL Parameter Maximum Clock Frequency ( uty Cycle) (Figures and 4) Maximum Propagation elay, Clock to (Figures and 4) Maximum Propagation elay, eset to (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures and 4) CC.0 Guaranteed Limit 55 C to 25 C 5 C 25 C C in Maximum Input Capacitance 0 0 0 pf.0.0.0 0 40 50 0 00 2 2 5 00 5 0 5 2 5 0 5 45 0 50 40 4 2 50 44 5 2 0 0 40 250 0 4 42 20 0 5 45 0 22 Typical @ 25 C, CC = 5.0 Unit MHz C P Power issipation Capacitance (Per Package)* 0 pf TIMING EUIEMENTS (Input t r = t f = ) Guaranteed Limit Symbol Parameter CC 55 C to 25 C 5 C 25 C Unit t su Minimum Setup Time, A or A2 to Clock (Figure ).0 25 5 5 5 40 25 t h Minimum Hold Time, Clock to A or A2 (Figure ).0 t rec Minimum ecovery Time, eset Inactive to Clock (Figure 2).0 t w Minimum Pulse Width, Clock (Figure ).0 50 2 2 0 0 5 5 2 5 45 5 t w Minimum Pulse Width, eset (Figure 2).0 50 2 2 0 0 5 5 2 5 45 5 5
MC4HC4B PIN ESCIPTIONS INPUTS A, A2 (Pi, 2) Serial ata Inputs. ata at these inputs determine the data to be entered into the first stage of the shift register. For a high level to be entered into the shift register, both A and A2 inputs must be high, thereby allowing one input to be used as a data enable input. When only one serial input is used, the other must be connected to CC. Clock (Pin ) Shift egister Clock. A positive going traition on this pin shifts the data at each stage to the next stage. The shift register is completely static, allowing clock rates down to C in a continuous or intermittent mode. OUTPUTS A H (Pi, 4, 5,, 0,, 2, ) Parallel Shift egister Outputs. The shifted data is presented at these outputs in true, or noninverted, form. CONTOL INPUT eset (Pin ) Active Low, Asynchronous eset Input. A low voltage applied to this input resets all internal flip flops and sets Outputs A H to the low level state. SWITCHING WAEFOMS t r 0% 0% t w t f CC GN ESET t PHL t w CC GN 0% 0% t PLH t TLH /f max t PHL t THL t rec CC GN Figure. Figure 2. TEST POINT A O A2 t su ALI t h CC GN EICE UNE TEST OUTPUT C L * CC GN *Includes all probe and jig capacitance Figure. Figure 4. Test Circuit
MC4HC4B EXPANE LOGIC IAGAM A A2 2 ESET 4 5 0 2 A B C E F G H TIMING IAGAM A A2 ESET A B C E F G H
MC4HC4B PACKAGE IMENSIONS TSSOP 4 T SUFFIX CASE 4G ISSUE B 0.5 (0.00) T 0.5 (0.00) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IENT. S C 4 G 4X K EF A 0.0 (0.004) M T U S S B U H N N J J F ETAIL E ETAIL E 0.25 (0.00) K K M ÇÇÇ ÉÉÉ ÇÇÇ SECTION N N W NOTES:. IMENSIONING AN TOLEANCING PE ANSI YM, 2. 2. CONTOLLING IMENSION: MILLIMETE.. IMENSION A OES NOT INCLUE MOL FLASH, POTUSIONS O GATE BUS. MOL FLASH O GATE BUS SHALL NOT EXCEE 0.5 (0.00) PE SIE. 4. IMENSION B OES NOT INCLUE INTELEA FLASH O POTUSION. INTELEA FLASH O POTUSION SHALL NOT EXCEE 0.25 (0.00) PE SIE. 5. IMENSION K OES NOT INCLUE AMBA POTUSION. ALLOWABLE AMBA POTUSION SHALL BE 0.0 (0.00) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATEIAL CONITION.. TEMINAL NUMBES AE SHOWN FO EFEENCE ONLY.. IMENSION A AN B AE TO BE ETEMINE AT ATUM PLANE W. MILLIMETES INCHES IM MIN MAX MIN MAX A 4.0 5.0 0. 0.0 B 4.0 0 0. 0. C. 0.04 0.05 0.5 0.002 0.00 F 0.50 0.5 0.0 0.00 G 0.5 BSC 0.02 BSC H 0.50 0.0 0.0 0.024 J 0.0 0. 0.004 0.00 J 0.0 0. 0.004 0.00 K 0. 0.0 0.00 0.02 K 0. 0.25 0.00 0.00 L.40 BSC 0.252 BSC M 0 0 SOLEING FOOTPINT*.0 0.5 PITCH 4X 0. 4X.2 IMENSIONS: MILLIMETES *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLEM/.
MC4HC4B PACKAGE IMENSIONS SOIC 4 NB CASE 5A 0 ISSUE K H 4 0.25 M B M e X b A B E 0.25 M C A S B S A A C SEATING PLANE L ETAIL A h X 45 M A ETAIL A NOTES:. IMENSIONING AN TOLEANCING PE ASME YM, 4. 2. CONTOLLING IMENSION: MILLIMETES.. IMENSION b OES NOT INCLUE AMBA POTUSION. ALLOWABLE POTUSION SHALL BE 0. TOTAL IN EXCESS OF AT MAXIMUM MATEIAL CONITION. 4. IMENSIONS AN E O NOT INCLUE MOL POTUSIONS. 5. MAXIMUM MOL POTUSION 0.5 PE SIE. MILLIMETES INCHES IM MIN MAX MIN MAX A.5.5 0.054 0.0 A 0.0 0.25 0.004 0.00 A 0. 0.25 0.00 0.00 b 0.5 0.4 0.04 0.0.55.5 0. 0.44 E.0 4.00 0.50 0.5 e.2 BSC 0.050 BSC H 5.0. 0.22 0.244 h 0.25 0.50 0.00 0.0 L.25 0.0 0.04 M 0 0 SOLEING FOOTPINT*.50 4X..2 PITCH 4X 0.5 IMENSIONS: MILLIMETES *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLEM/. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION OEING INFOMATION LITEATUE FULFILLMENT: Literature istribution Center for ON Semiconductor 52 E. 2nd Pkwy, Aurora, Colorado 00 USA Phone: 0 5 25 or 00 44 0 Toll Free USA/Canada Fax: 0 5 2 or 00 44 Toll Free USA/Canada Email: orderlit@oemi.com N. American Technical Support: 00 22 55 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 0 20 Japan Customer Focus Center Phone: 5 050 ON Semiconductor Website: Order Literature: http:///orderlit For additional information, please contact your local Sales epresentative MC4HC4B/