Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors Shih-Ching Lo 1, Yiming Li 2,3, and Jyun-Hwei Tsai 1 1 National Center for High-Performance Computing, Hsinchu 3, Taiwan 2 Department of Nano Device Technology, National Nano Device Laboratories, Hsinchu 3, Taiwan 3 Microelectronics & Information Systems Research Center, National Chiao Tung Univ., Hsinchu 3, Taiwan Abstract: - High-k dielectric materials are being considered as replacement for SiO 2 as the gate dielectric while retaining the low equivalent oxide thickness (EOT) required next generation metal oxide semiconductor field effect transistors (MOSFETs). In this paper, we simulate the capacitance voltage (C-V) of n-type MOSFET devices with different high-k dielectric insulator numerically. According to the results, high-k dielectric materials maintain the capacitance and provide a robust physical thickness preventing tunneling current. mechanism must be considered in the simulation or a 9.3 % overestimation of capacitance will be observed in an extreme case. Capacitance of high-k dielectrics couldn t be estimated by capacitance of insulator with EOT directly because a 13 % difference is observed. To obtain an accurate result, a self-consistent Schrödinger Poisson equation should be solved. Key-Words: - confinement effects, Schrödinger equation, High-k dielectric, MOSFET devices, Capacitance, Equivalent oxide thickness, Ultra thin oxide. 1 Introduction Aggressive progress in metal oxide semiconductor field effect transistor (MOSFET) integrated circuit technology has allowed device performance (speed) to meet market demand. To span 7 nm technology node, the oxide thickness of gate dielectric needs to be scaled below 1.5 nm [1-3]. Large gate leakage currents and reliability problems appear even at low voltages and make the value cannot be obtained in a MOSFET structure with SiO 2 as gate oxide [4-6]. If one looks at the capacitor equation, the only factor left to adjust is the dielectric constant under the classical MOSFET structure. Therefore, research on the high-k gate dielectrics has been expanded significantly to enable the capacitor dielectric to maintain a robust thickness while still providing a continuously shrinking area and storage voltage. According to previous studies, high-k dielectric material such as SiO 2, Si 3 N 4, HfO 2, TiO 2, Ta 2 O 5, ZrO 2, La 2 O 3 and their silicates are possible candidates [7-14]. It has been shown recently that higher physical gate oxide thickness can result in degradation of the electrical performance due to increased fringing fields from gate to source/drain. On the other hand, unexpected materials are produced between dielectric/si interface while the high-k materials are deposited on silicon substrate and the actual equilvalent oxide thickness (EOT) will differ from the designed profile. Phenomena mentioned above affect the design and optimization of MOSFET structure. Therefore, gauging the impact of the gate on the device by accurate simulations of the MOSFET characteristics should be addressed for high-k dielectric application. In this study, capacitance - voltage (C-V) characteristics of MOSFET devices with SiO 2, and HfO 2 are examined quantitatively. In addition, HfO 2 /HfO ed oxide is discussed. Some important results are presented. That is, EOT not only depends on dielectric constant but also depends on other characteristics of materials, such as band gap, conduction band electrode offset and so on. Estimating EOT of high-k materials by dielectric constant directly results in incorrect C-V characteristic, electron density and potential distribution in the substrate. Thickness of byproducts between interface of dielectric and silicon should be considered while simulating or designing devices because the additional thickness lowers the designed capacitance. The remaining content of this study is organized as follows. In Sec. 2, the simulation models and the computational method are briefly described. Section 3 shows the simulation results and discussion. Finally, Sec. 4 draws the conclusions. 2 Modeling and Simulation To simulate capacitance of a MOSFET electron density and potential distribution should be calculated. In this study, classical and quantum models, which are drift-diffusion (DD) and Schrödinger Poisson DD (SP-DD) models, are compared quantatively. Three governing equations of
DD model are listed as follows. The Poisson equation is ( p n + ) ε ψ = q N D N A, (1) where ε is the electrical permittivity, q is the elementary electronic charge, n and p are the electron and hole densities, and N D and N A are the number of ionized donors and acceptors, respectively. The current densities are given by: J and (2) n = qnµ n φn J, (3) p = qpµ p φ p where J n and J p are the electron and hole current density satisfying the continous equations, µ n and µ p are the electron and hole mobility, and φ and n φ are p the electron and hole quasi-fermi potentials, respectively. The mobility model used herein is Masetti s model. In principle, Schrödinger equation is the most accurate method to solve quantum mechanism. The Schrödinger equation along the semiconductor substrate (z - direction) [13, 15] is given as 2 } E ( z) C j, v ( z) E j, v j, v ( z) + Ψ = Ψ (4) z 2mz, v ( z) z ħ is the reduced Planck constant, E C is the conduction band energy, v is the band valley, m z,v, is the effective mass for valley in quantization direction, Ψ j,v is the j-th normalized eigenfunction in valley v; and, E j,v is the j-th eigenenergy. The self-consistent computing procedure is illustrated in Fig. 1 and described as follows. Firstly, the stop criteria, mesh, output variables and simulation models are chosen. Then, Poisson equation is solved iteratively until the result converges. If quantum mechanical model is considered, the Schrödinger equation is solved until it converges. Otherwise, continuity equations are solved. Before solving continuity equations, the Schrödinger-Poisson systematic equation should be solved iteratively until the two equations converge. After all equations converge, we ll check the whole system converges or not. If the whole system converges, then stop computing. Otherwise, the outer loop should be iterated again until the whole system converges. This scheme makes sure the solution will be self-consistent. 3 Results and Discussion In the numerical studies, a NMOSFET with 9 nm gate length is simulated. The simulated dielectric materials are SiO 2, HfO 2 and HfO 2 /HfO ed oxide with EOT = 1, 2 and 3 nm. Dielectric constant of SiO 2 is 3.9 and HfO 2 is 21. Figure 2 illustrates the simulated NMOSFET. Applied gate voltage varies from 1.5 ~ 1.5 V and a 1 Hz frequency ac signal is given. Applied drain voltage should be small enough to show the capacitance of MOS structure. A.1 V drain voltage is given in this study. Numerical results of the NMOSFET are obtained by using a commercial TCAD tool, ISE-DESSIS ver. 8..3 [16]. Pre-process.mesh generation.simulation model Start Solve Poisson equation converge? converge? SP loop converge? Solve continuity equations converge? outer loop converge? Post-process.stop criteria.outputs Solve Schrodinger equation Fig. 1. The flowchart of self-consistent procedure. 4nm n + x j =11nm x j =5nm n + channel doping S/D halo oxide salicide n + Fig. 2. The simulated NMOSFET. In this study, we assume that there is no interfacial trap charge. Figures 3 ~ 5 shows simulated C-V curves of MOSFET with SiO 2, HfO 2 and HfO 2 /HfO ed oxide for EOT = 1, 2 and 3 nm, respectively. EOT is estimated by EOT = ( k SiO k x ) t 2 x (5)
where k x is the k value for the film of interest, t x is the physical thickness of the film of interest and k is the k value of silicon dioxide. However, while HfO 2 is deposited on the silicon substrate, HfO or Hf salicide may be generated and the EOT will differ from the estimation. The kind of byproduct and the thickness depend on the manufacturing process. According to previous studies, a 5nm HfO 2 film deposited on silicon substrate will generate 1nm HfO at the interface and 4 nm HfO 2 above it [14]. Thus, EOT of the ed oxide case is estimated by the ratio. EOTs simulated in this study is given as Table 1. Table 1. Equivalent oxide thickness for high-k insulators. Materials SiO 2 HfO 2 HfO HfO 2 EOT 1 (nm) 1 5.38 1.8 4.3 EOT 2 (nm) 2 1.77 2.15 8.62 EOT 3 (nm) 3 16.12 3.23 12.92 From Figs 3 ~ 5, we can observe that classical model overestimates the capacitance of a nanoscale device by comparing subfigure with. Figure 6 illustrates the comparison for capacitance of hafnium dioxide with EOT =1 and 3 nm. It is found that a thinner oxide thickness actually induces a larger capacitance than a thicker one. Since capacitance of a MOS capacitor is equal to the oxide capacitance and the silicon capacitance connected in series, total capacitance can be expressed as OX Si ( C C ) C = C C +, (6) OX Si where C OX and C Si are capacitance of gate dielectric and silicon, respectively. Once strong inversion layer forms, total capacitance is dominated by the silicon capacitance. C is approximated by C OX, which is k x /t x. Approximately, C is proportional to 1/t x. Differences between classical and quantum cases are more obvious while EOT becomes smaller. The phenomenon is caused by different electron density and potential distribution between classical and quantum models. From Fig. 7, density distribution of classical and quantum models are quite different. Comparing to potential distribution simulated by quantum model, classical model underestimates it. To get more insight into the differences of capacitance between classical and quantum cases, we consider capacitance of quantum model as the basis and compare the results. The percentage of difference is illustrated in Fig. 8. Since the difference of capacitance is getting larger as gate voltage increases. Figure 8 illustrates the results under = 1.5 V. All three dielectric materials show the same results, i.e., when EOT becomes smaller the difference of capacitance between classical and quantum cases becomes larger. In an extreme case, which is the 1 nm SiO 2 MOSFET, a 9.3 % overestimation of classical model is observed. 4.5e-1 4.e-1 3.5e-1 3.e-1 2.5e-1 1.5e-1 4.5e-1 4.e-1 3.5e-1 3.e-1 2.5e-1 1.5e-1 Fig. 3. The simulated capacitance of different gate dielectric materials with EOT = 1 nm for classical and quantum cases. 2.2e-1 1.8e-1 2.2e-1 1.8e-1 Fig. 4. The simulated capacitance of different gate dielectric materials with EOT = 2 nm for classical and quantum cases. 8.e-2 8.e-2 Fig. 5. The simulated capacitance of different gate dielectric materials with EOT = 3 nm for classical and quantum cases.
4.5e-1 4.e-1 3.5e-1 3.e-1 2.5e-1 1.5e-1 8.e-2 Fig. 6. Comparison of C-V curves between classical and quantum cases with EOT = 1 nm and EOT = 3 nm. 3.e+2 2.5e+2 2.e+2 1.5e+2 1.e+2 5.e+19. potential.9.8.7.6.5 Fig. 7. Comparison of density and potential distributions between classical and quantum cases with EOT = 1 nm. capacitance [%] 1 9 8 7 6 5 4 3 1 2 3 EOT [nm] Fig. 8. The percentage of capacitance difference between classical and quantum cases for dielectric materials with EOT = 1, 2 and 3 nm, where = 1.5V. On the other hand, devices with SiO 2, HfO 2 and HfO 2 /HfO oxide present different C-V curves by observing Figs 3 ~ 5. From the figures, differences of capacitance with different materials are shown. It is because the penetrating mechanisms of potential are diverse among three dielectric materials. The penetrating mechanism depends on the physical thickness of insulator, band gap, band structure, conduction band electrode offset and quantum mechanism. Hence, electron density and potential distributions of devices with SiO 2, HfO 2 and HfO 2 /HfO ed oxide are different and induce difference of capacitance. Therefore, we cannot estimate C by C ox and Eq. (6) directly. A Schrödinger Poisson equation should be considered as nanoscale devices are simulated. Figures 9 ~ 11 show the electron density and potential distributions for devices with three dielectric materials. In this study, we assume the ed device (HfO 2 /HfO) as the accurate profile and consider the electron density and potential distribution of it as the exact solution. The percentages of difference are illustrated in Figs 12 ~ 13. According to the figures, electron density distributions of the three dielectric are quite different and potential distribution are very close. As oxide thickness is smaller, the difference of electron density is larger. In an extreme case, the difference is up to 35 %. Among the numerical results, the largest difference of each curve occurs near the insulator/silicon interface. Difference between devices with SiO 2 and ed oxide, which is in the range of 27 ~ 35 %, is much larger than difference between devices with HfO 2 and ed oxide, which is in the range of 1 ~ 15 %. The difference is larger as EOT is smaller. In the aspect of potential, all three cases are very closed and the percentages are within 2 %. However, if we discuss the capacitance, which is a function of potential and density, significant differences are observed. Difference between devices with SiO 2 and ed oxide, which is in the range of 2 ~ 13 %, is much larger than difference between devices with HfO 2 and ed oxide, which is in the range of 2 ~ 5 %. As oxide thickness is getting thinner, the difference between SiO 2 (or HfO 2 ) and ed oxide is getting larger. The percentages of difference tend toward stable while the strong inversion layer is formed. As previous discussion, numerical results of devices with SiO 2 oxide have large difference to devices with ed oxide and the difference increases with EOT decreases. Fortunately, numerical results of devices with HfO 2 oxide are close to devices with ed oxide. Maybe results of device with HfO 2 oxide can be considered as the approximation of device with ed oxide. If
byproduct appears between oxide/substrate interface, an additional thickness of oxide is generated. Then, the designed capacitance of device will be lowered and the performance of device will not be as good as the expectation. 1e+2 8e+19 6e+19 4e+19 potential.9.85.8.75.7.65.6..2.4.6.8 1. 1.2 1.4 Fig. 9. The simulated results of different gate dielectric materials with EOT = 1 nm for density and potential distribution. 3.5e+19 3.e+19 2.5e+19 2.e+19 1.5e+19 1.e+19 5.e+18. potential.75.7.65.6.55 Fig. 1. The simulated results of different gate dielectric materials with EOT = 2 nm for density and potential distribution. 1e+19 1e+19 1e+19 8e+18 6e+18 4e+18 2e+18 potential.75.7.65.6.55.5 Fig. 11. The simulated results of different gate dielectric materials with EOT = 3 nm for density and potential distribution. electron density [%] 4 35 3 25 2 15 1 5 EOT=1nm; vs EOT=1nm; vs EOT=2nm; vs EOT=2nm; vs EOT=3nm; vs EOT=3nm; vs Fig. 12. The percentage of density difference between dielectric materials with EOT = 1, 2 and 3 nm, where = 1.5V. potential [% ] 2. 1.5 1..5. EOT=1nm; vs EOT=1nm; vs EOT=2nm; vs EOT=2nm; vs EOT=3nm; vs EOT=3nm; vs..2.4.6.8 1. 1.2 Fig. 13. The percentage of potential difference between dielectric materials with EOT = 1, 2 and 3 nm, where = 1.5V. capacitance [%] 8 4-4 -8-12 -16 1 EOT=1nm, vs. EOT=1nm, vs. EOT=2nm, vs. EOT=2nm, vs. EOT=3nm, vs. EOT=3nm, vs. Fig. 14. The percentage of capacitance difference between dielectric materials with EOT = 1, 2 and 3 nm.
According to the numerical results mentioned above, we can make summary of the results. High-k dielectrics actually provide a robust thickness without losing any capacitance. Capacitance of high-k dielectrics couldn t be estimated by capacitance of insulator with EOT directly because a 6 % difference of capacitance among materials is observed at the turn on region in the case of EOT =1 nm. At the subthreshold region, the difference will be up to 13 %. The difference is caused by the penetrating mechanism of different materials and the byproduct generated between dielectric/silicon interface. Also, while simulating capacitance of nanoscale devices, quantum mechanism should be considered. Therefore, the penetrating mechanism has to be analyzed and model carefully to obtain an accurate device capacitance. 4 Conclusions In this paper, a 9 nm NMOSFET is simulated with SiO 2, HfO 2 and ed oxide. A self-consistent Schrödinger Poisson transport model is considered to obtain the capacitance of the simulated device. The results are more accurate than estimating capacitance by oxide capacitance with EOT especially when byproduct is generated between oxide/substrate interface. According to our numerical studies, high-k dielectrics ensure a continuously shrinking of MOSFET possible without gate leakage concern by maintaining a robust thickness of oxide. Although high-k gate dielectrics seem to be an attractive solution of continuous scaling of MOSFET device, a number of difficulties are investigated, such as crystallization upon heating, fixed charge, instability in contact with poly Si, low channel mobility and uncontrolled oxide formation at the Si/high-k interface. The selection of suitable materials and their manufacturing process are left for further studies. 5 Acknowledgement The work is partially supported by the National Science Council (NSC), Taiwan, R.O.C., under Contracts NSC 92 2215 E 429-1, NSC 92 2112 M 429-1, and NSC 92 2815 C 492 1 - E. It is also partially supported by Ministry of Economic Affairs, Taiwan, R.O.C. under contract. 91 EC 17 A 7 - S1-11. References: [1] H. Iwai, Ultra Thin Gate Oxides Performance and Reliability, IEDM. Tech. Dig., p. 163, 1998. [2] H. Iwai, Downsizing of Silicon MOSFETs beyond.1 µm, Microelectron. J., Vol. 29, pp. 671-678, 1998. [3] B. Yu et al., Limits of Gate Oxide Scaling in Nano-Transistors, VLSI Tech. Dig., pp. 39-4, 2. [4] H. S. Momose, et al. 1.5 nm Direct Tunneling Gate Oxide Si MOSFET s, IEEE Trans., Elec. Dev., Vol. 43, pp. 1233, 1996. [5] S. H. Lo et al., -Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin Oxide nmosfet s, IEEE Dev. Lett., Vol. 18, pp. 29-211, 1997. [6] Y. Li et al., Modeling of Effects for Ultrathin Oxide MOS Structures with an Effective Potential, IEEE Trans. Nanotech., Vol. 1, pp. 238-242 22. [7] B. H. Lee et al., Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application, IEDM Tech. Dig., p.133, 1999. [8] B. H. Lee et al., Characteristics of TaN Gate MOSFET with Ultrathin Hafnium Oxide (8-12A), IEDM Tech. Dig., p.39, 2. [9] J. J. Lee, Theoretical and Experimental Investigation of Si Nanocrystal Memory Device with HfO 2 High-k Tunneling Dielectric, IEEE Trans. Elec. Dev., Vol. 5, pp. 1-6, 23. [1] L. Mannchanda and M. Gurvitch, Yttrium Oxide/Silicon Dioxide: A New Dielectric Structure for VLSI/ULSI Circuits, IEEE Elec. Dev. Lett., pp. 2854, 1999. [11] L. Mannchanda and W. H. Lee, Gate Quality Doped High K Films for CMOS beyond 1 nm: 3-1 nm Al 2 O 3 with low Leakage and Low Interface States, IEDM Tech. Dig., p. 65, 1998. [12] B. Cheng et al., The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-1nm MOSFET s, IEEE Trans. Elec. Dev., Vol. 46, p. 1537, 1999. [13] Y. Li et al., Numerical Simulation of Effects in High-k Gate Dielectrics MOS Structures using Mechanical Models, Computer Physics Commun., Vol. 147, pp. 214-217, 22. [14] G. Lucovsky, et al., Electronic Structure of Transition Metal High-k Dielectrics: Interfacial Band Offset Energies for Microelectronic Devices, Applied Surface Science, pp.563-569, 23. [15] Y. Li et al., A vel Parallel Approach for Effect Simulation in Semiconductor Devices, Int. J. Modelling & Simulation, Vol. 23, pp. 94-12, 23. [16] DESIS-ISE TCAD Release 8., ISE integrated Systems Engineering AG, Switzerland, 22.