Transient Charging and Relaxation in High-k Gate Dielectrics and Their Implications

Japanese Journal of Applied Physics Vol. 44, No. 4B, 25, pp. 2415 2419 #25 The Japan Society of Applied Physics Transient Charging and Relaxation in High-k Gate Dielectrics and Their Implications Byoung Hun LEE 1;2;, Chadwin YOUNG 1, Rino CHOI 1, Jang Hwan SIM 1 and Gennadi BERSUKER 1 1 International SEMATECH, 276 Montopolis Drive, Austin, Texas 78741, U.S.A. 2 IBM assignee, 276 Montopolis Drive, Austin, Texas 78741, U.S.A. (Received September 22, 24; revised November 9, 24; accepted November 11, 24; published April 21, 25) Recent results on device instability indicate that the methodologies developed for electrical characterization of metal oxide semiconductor (MOS) devices with SiO 2 gate dielectric may not be sufficiently accurate for high-k devices. While the physical origin of the instabilities in high-k devices is yet to be identified, it is found that many of the abnormal electrical characteristics of high-k devices can be explained by assuming fast and slow transient chargings in high-k dielectric. In this paper, transient charging effects in high-k gate dielectrics are reviewed and their implications on test methodologies are discussed. [DOI: 1.1143/JJAP.44.2415] KEYWORDS: transient charging effect, high-k gate dielectric, Hf-silicate, hot carrier effect, mobility, TiN electrode 1. Introduction The electrical characteristics of high-k gate dielectrics such as mobility, equivalent oxide thickness (EOT), threshold voltage, flat band voltage, transistor input and output characteristics, interface state density, time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI) and hot carrier injection (HCI) effects, have been exploited intensively in many studies. Since these electrical characterization methods have been developed for SiO 2 devices with certain assumptions to simplify the test, whether these methods are applicable to high-k devices has not been studied systematically. Studies on the charge trapping characteristics of high-k gate dielectrics showed that the instabilities in capacitance voltage (CV) and current voltage (IV) characteristics are so significant that simple device parameters such as threshold voltage and flat band voltage may not be well defined due to the dependence of the device parameters on the measurement history or their changes during the test or electrical stress. 1 5) Since inaccurate characterization methods may lead to erroneous conclusions that may hinder the optimization of high-k dielectrics, a thorough examination of the validity of test methodologies is very important. For example, if the I d V g curves and inversion CV curves are affected by the transient charging effects, which are discussed in details below, the extracted mobility value could be inaccurate 6) and the process development based on the mobility value could be guided in the wrong direction. Yet, the mobility of high-k device is frequently reported without acknowledging the contribution of charging effects. A limited number of studies discuss the validity of the standard electrical characterization methods in the case of high-k devices. Zhu et al. explored the possibility of errors in the mobility extraction methodology for high-k devices 7) and Takayanagi et al. and Lee et al. showed that the hot carrier injection test is actually dominated by cold carrier accumulation in the high-k dielectric layer rather than by hot carrier induced damage. 8,9) These examples show that the characterization and reliability test methodologies developed to characterize MOS devices with the SiO 2 gate dielectric may not be adequate for high-k devices. Transient charging has been proposed as one of the E-mail address: byoung.hun.lee@sematech.org 2415 dominant mechanisms responsible for device instability. 1,6,9,1) The physical origin of these device instabilities has not yet been fully understood, but certain progress has been made in developing the electrical characterization of high-k transistors, in particular, using ultra-short pulse I V measurement 1) or various reliability tests. 3,11) In this paper, a recent understanding of the effects of transient charging in high-k gate dielectrics will be reviewed and its implications on test methodologies and high-k development will be discussed. 2. Definition of Transient Charging In this paper, transient charging is defined as timedependent charge trapping and detrapping in high-k gate dielectrics observed during device operation or under reliability stress. Even though the physical mechanism is not yet clear, the transient charging is classified into two categories, fast transient charging and slow transient charging, depending on the characterization methods being employed. Fast transient charging can affect measurements with a characteristic time on the order of microseconds or longer such as those of single pulse I d V g with sufficiently long pulse widths or rise times, or DC I d V g and capacitance. The transient nature of this type of trapping manifests itself in its detrapping property when the bias, which maintains the given equilibrium level of charge accumulated in the high-k layer, is removed. The slow transient charging can affect many reliability measurements such as TDDB, HCI, and BTI, which are typical performed over a duration of hundreds to thousands second. These processes are also transient because most of the device degradations observed during these reliability tests are reversible. 3. Implications of Fast Transient Charging The drain current curve of a poly/hf-silicate NMOS transistor is monitored with a fast digital storage scope while a þ2 V gate pulse for 1 ms and 1 ms is applied (Fig. 1). The current traces show a rapid current decrease within the first 5 ms due to the quick charge accumulation in the high-k layer. This pulse trace is repeatable, indicating that most of the charging effect decays within 1 ms when the gate bias is turned off. Since the conventional DC techniques used to characterize MOS devices have an integration time longer than ten microsecond, the fast transient charging distorts the results of the DC measurements. To demonstrate the effect

2416 Jpn. J. Appl. Phys., Vol. 44, No. 4B (25) B. H. LEE et al. I d (µa/µm) 35 3 25 2 15 1 5 Id drop due to transient charging 1µs 1ms 1-5 1-4 1-3 1-2 Pulse duration(s) Fig. 1. Drain current measured using 1 ms and 1 ms single pulse applied to gate. Pulse bias was þ1:25 V. Drain Current (µa) 3 25 2 4.5 nm HfSi x O y nfet W/L = 1/1 µm 15 DC 1 1ms 1us 5 1us 5us..5 1. 1.5 2. 2.5 3. Gate Voltage (V) Fig. 2. I d V g curve measured with single pulse measurement. The points of the I d V g curves are drain current values measured and averaged for a pulse width in the range of 5 ms to 1 ms. of integration time, the drain current measurements taken during the pulses with various widths are averaged as shown in Fig. 2. Since the amount of accumulated charge in the high-k layer is proportional to gate bias, the DC I d V g curve is stretched as gate bias and measurement integration time increase. Both the slope of the I d V g curve and drain current in the TiN/Hf-silicate NMOS devices are improved with a shorter integration time due to reduced charging. The significant difference between the curves in Fig. 2 indicates that the models based on the data collected without considering the transient charging phenomenon may be compromised by the inadequate characterization methods. The data in Fig. 2 also indicates that conventional mobility extraction using the DC I d V g and split CV measurements underestimates the actual mobility of high-k devices. At a given gate bias, drive current increases significantly with a shorter integration time by eliminating the transient charging effects. This difference is not directly translated into mobility because the split CV curve and DC I d V g curve are stretched similarly due to the transient charging. However, this does not mean the mobility values calculated from DC I d V g and split CV curve are correct. First, the bias-dependent charge trapping skews the surface potential and the mobility vs electric field curve is stretched if the surface potential modification due to the charge trapping is not accounted. Second, the DC I d V g measurement is affected by additional carrier scattering due to the accumulated transient charging while the split CV measurement is affected by a part of fast transient charging that can follow the AC modulation frequency of capacitance measurement. Thus, the slew rates of the DC I d V g curve and the split CV curve do not match exactly and the mobility extracted from these curves is not accurate for high-k device with a large amount of charge trapping. Also, pulsed I d V g and split CV curves cannot be combined to calculate the mobility because the surface potential is not easy to match and the accuracy of the split CV curve has been negated by the charge trapping. An alternative method proposed by Zhu et al. is to fix the split CV and generate an ideal I d V g curve. 7) However, this method cannot account for the additional degradation mentioned above. Another method is to combine a pulsed I d V g curve measured with a very short pulse and an ideal CV curve modeled from the accumulation CV characteristics. More details of this method will be published elsewhere. If the mobility of the poly/hf-silicate NMOS transistors is calculated considering more than 15% current gain shown in Fig. 2, the intrinsic mobility of the high-k device used in this work is approximately 1 15% worse than in conventional SiO 2 devices. A part of the remaining difference between the high-k and SiO 2 mobility can be explained by the contribution from the interface trap density, which is about one order of magnitude higher in high-k devices and other scattering mechanisms proposed in various publications, i.e., remote charge scattering and soft optical phonon scattering. Note that the interface trap density in the high-k device can be effectively reduced by a high pressure hydrogen annealing and the mobility of high-k device can be improved by 5 15%. 12) Previous studies performed using similar methods concluded that the contribution of charge trapping is not significant. 1,13) However, the rising time of the pulse measurement used in those studies was much longer than the one employed in this study. 1,14) Long pulse rising time with respect to the time constant of fast transient charge trapping results in uncontrollable charge trapping that may have compromised the result of previous studies. While the quality of high-k dielectrics may require further improvement, it is important to assess the intrinsic characteristics of high-k films since actual circuits, which include high-k devices, can be designed to minimize the transient charging effects if the intrinsic and transient characteristics of high-k devices are well understood. Better understanding of transient charging effects provides additional insights in the optimization of a high-k gate dielectric stack. For example, it is well known that the carrier mobility in high-k gate stack devices can be recovered to the level of the conventional thermal oxide device mobility when the thickness of the interfacial layer exceeds a certain limit, typically 15 A. 15 17) This result can be understood in terms of the decrease in the transient charging due to smaller tunneling current through the interfacial layer. Therefore, the quality and thickness of the interfacial layer, which controls the tunneling current, seems to be a crucial factor in the high-k optimization. 18) On the other hand, fixed charge scattering model 17) or remote phonon scattering model 19) indicates that the thickness of interfacial oxide is the only

Jpn. J. Appl. Phys., Vol. 44, No. 4B (25) B. H. LEE et al. 2417 parameter contributing to the mobility. The relatively small mobility degradation in high-k pmos transistors compared with NMOS has long been a controversial issue. The transient charging model can explain the small mobility degradation based on the low probability of hole tunneling into the high-k film through the interfacial layer due to the high tunneling barrier and heavy effective mass of hole compared with that of electron. Another direction of mobility improvement that can be derived from the transient charging model is to reduce the electron trap density in highk dielectrics. Unfortunately, the nature of the trap sites has not yet been studied in detail. Trap sites can be related to structural defects such as oxygen vacancies and interstitial oxygen, various impurities, hafnium vacancies, hydrogen and grain boundary related defects, or they can be related to the intrinsic nature of Hf atom. 2 24) 4. Implications of Slow Transient Charging The bias-dependent device degradations of high-k devices under various types of traditional electrical stress such as time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and hot-carrier injection (HCI) can be affected by slow transient charging. Previously, the reliability characteristics of high-k films have been interpreted using the theory developed for SiO 2 films. However, most device degradations observed in high-k devices are reversible and frequency dependent. Thus, the direct application of oxide-based reliability methodology to the high-k stack may result in erroneous conclusions. The physical origins of device degradation in high-k devices may be rather different from those of the conventional oxide devices under similar stress conditions. For example, device degradations during hot-carrier stress are found to be dominated by the concurrent charging due to cold carriers. 8,9,25) The accumulated charges in the high-k film may decay once the stress bias is turned off or a parameter shift can be completely recovered by applying a proper negative bias as shown in Fig. 3. Thus, it is evident that previously reported results on the hot carrier reliability of high-k gate dielectrics have underestimated the lifetime of high-k devices. 26,27) More importantly, the hot-carrier damage mechanism inherited from the SiO 2 era should be reconsidered in the case of high-k gate dielectrics even though it may still have some relevance to the interfacial oxide layer. The TDDB measurement of high-k devices is another area that requires careful re-evaluation. Similar to the HCI stress case, slow transient charging rather than defect generation within the high-k layer is found to dominate the V th shift during TDDB stress. Figure 4 shows that the V th shift caused by a constant voltage stress can be recovered either with or without an applied bias. As indicated by the V th shift during the first few seconds of the stress, fast transient charging is responsible for a significant portion of the V th shift. Thus, the previously reported TDDB results actually present the effect of the reversible charge accumulation and its impact on electrical conduction in the high-k film rather than reflect on the physical wear-out process in the high-k gate stacks. Pulsed TDDB measurements can partly address this problem, and Kim et al. have reported on the improved TDDB lifetime of the high-k capacitors as the pulse width and duty cycle are reduced. 28) However, the extraction of the intrinsic TDDB lifetime of high-k devices may require a much shorter pulse width than the pluse width used in ref. 28 and the relaxation current during the rising and falling edges of the pulse may skew the total amount of charge injection. The NBTI phenomenon of the high-k gate dielectrics may involve a more complicated set of processes than in the SiO 2 case. Under negative bias stress, the interfacial layer of high-k gate dielectrics is preferentially degraded due to hole trapping from the interface while the transient charging is in the detrapping direction as shown in Fig. 5. Thus, the effect of hole trapping and electron detrapping are mixed under negative bias stress while electron trapping is a dominant trapping mechanism under positive bias stress. The strong polarity and temperature dependence of hole trapping and electron detrapping adds complexity to NBTI. 29,3) Thus, the NBTI mechanism widely accepted for SiO 2 devices, which explains the V th shift employing the hydrogen bond breaking process at the oxide-silicon interface, may not completely explain the NBTI stress results in high-k devices when the gate stack structure incurs significant carrier tunneling. Therefore the usefulness of the conventional constant bias stress NBTI as a measure of device reliability may be limited 3 25 3 HCI stress Relaxation 25 2 15 1 5 5 1 15 2 Stress time(s) 2 15 1 5 After Detrapping at -1V 2 4 6 8 1 Stress time(sec) Fig. 3. Hot-carrier stress-induced V th shift and its recovery during relaxation period or using negative bias detrapping.

2418 Jpn. J. Appl. Phys., Vol. 44, No. 4B (25) B. H. LEE et al. 3 25 2 15 1 5 CVS stress Relaxation 5 1 15 2 Stress time (s) 2 15 1 5 After Detrapping at -1V 2 4 6 81 Stress time (s) Fig. 4. V th shift during the constant bias stress at V g ¼þ2V and its recovery during relaxation period or using negative bias detrapping. degradation (%) -2-4 -6 Positive Bias Stress Negative Bias Stress -8. 2. 2.2 2.4 2.6 VG (V) degradation (%) -2-4 -6-8 Positive bias stress Negative bias stress -1. 2. 2.2 2.4 2.6 VG (V) Fig. 5. Polarity dependence of stress induced device degradation; gm and swing at poly/hfsio NMOS. in high-k devices. An extensive study on polarity and temperature dependence is required to understand the meaning of the NBTI test for high-k devices. The above examples of HCI, TDDB and NBTI illustrate the limits of the traditional reliability methodology such as 1) the extrapolation of the results obtained under the high field stress to the low field stress conditions and 2) the extrapolation of constant bias stress results to the dynamic stress situation. These extrapolations have not been proven as completely correct for SiO 2 devices, while in case of high-k devices the validity of the test methodology as a whole should be questioned. Although the elimination of the transient charging may be the preferred way of avoiding the complications discussed above, it may not be possible if the electron trapping is the intrinsic property of the high-k dielectrics. In that case, it is even more important to understand the reliability of high-k devices considering the effect of transient charging. 5. Conclusions Transient charging effects (TCE) are proposed to explain the various abnormal characteristics of high-k devices such as mobility degradation and reliability characteristics such as HCI, NBTI and TDDB. The transient charging mechanism, which includes both fast and slow transient charging effects, successfully explains previously reported results. The model suggests that many of the conventional electrical characterization and reliability methods developed for SiO 2 gate dielectric may need to be revised to account for the electron trapping effects in high-k gate stacks. 1) A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degrave, T. Kauerauf, G. Groeseneken, H. E. Maes and U. Schwalke: Proc. Int. Reliab. Phys. Symp., 23, p. 31. 2) S. Zafar, A. Callegari, E. Gusev and M. V. Fischetti: J. Appl. Phys. 93 (23) 9298. 3) J. H. Sim, B. H. Lee, R. Choi, K. Matthews, D. L. Kwong, P. Tsui and G. Bersuker: Proc. Device Research Conf., 24, p. 214. 4) E. Gusev and C. P. D Emic: Appl. Phys. Lett. 83 (23) 5223. 5) S. Kar: IEEE Trans. Electron Devices 5 (23) 2112. 6) G. Bersuker, P. Zeitzoff, J. Sim, B. H. Lee, R. Choi, G. Brown and C. Young: Int. Integr. Reliab. Workshop, 24, HIK5-1. 7) W. Zhu, J. P. Han and T. P. Ma: IEEE Trans. Electron Devices 51

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