Transistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. Two types: bipolar junction transistors and field effect devices. We concentrate on FETs: source drain gate The history: vacuum tubes Basic idea of three-terminal devices for current control goes back to 1906, when Lee deforest invented the vacuum triode: grid (base) cathode (emitter) heater anode (collector) Ground anode; bias cathode to large negative voltage w.r.t anode. Heater boils electrons off cathode (thermionic emission); accelerated through grid toward anode. ac voltage on grid can modulate electron current! Three-terminal device with gain: dawn of the information age. 1
The history: vacuum tubes Problems with vacuum tubes: Bulky Fragile Long warm-up times High power consumption, largely wasted High speeds difficult - require extra plates, grids to minimize capacitances (pentodes) Miniaturization very challenging. There must be a better way. acuum tubes still best for: High powers (ex.: e-gun power supplies) Radiation-hardened electronics (ex.: B-52s) The history: Lillienfeld Basic idea proposed (1930): Method and apparatus for controlling electric currents Use third electrode to modulate current between ohmic contacts on a semiconductor. Solid-state triode. from Pierret. 2
Basic field effect transistor idea Normally off: Gate acts like capacitor plate - applied voltage creates channel with free carriers, connecting source and drain. Lilienfeld Normally on: Gate acts like grid - applied voltage restricts flow of (lightly doped) carriers from source to drain. Shockley (grid-like) Why did these ideas first run into trouble? Surface states! Materials quality prevented practical FETs until 1955. Types of field effect transistors different metals JFET Junction FET MESFET MEtal Semiconductor FET Channel, source, drain all same type of doped semiconductor. Normally on - requires gate voltage to turn off S conduction; devices operate in depletion mode. Gate can be anywhere between source and drain. Current flow restricted by depletion zone (from pn junction in JFET; from Schottky barrier in MESFET). Fairly robust (no super-thin insulating layers, etc.) 3
Types of field effect transistors MOSFET or MISFET Metal Oxide or Metal Insulator Semiconductor FET channel Source, drain different doping type than bulk of semiconductor Normally OFF - gate must be biased sufficiently to invert channel region in order to see transistor action; devices operate in accumulation mode. Requires gate to extend over source and drain. Thin insulating barrier (gate oxide) necessary. Bulk may be p or n - complementary metal-oxide-semiconductor processing (CMOS). Types of field effect transistors HEMT High Electron Mobility Transistor ++++++++++++++++++++++++++++ undoped GaAs Source, drain are ohmic contacts to GaAs 2deg channel. Normally ON device (modulation doping) operates in depletion mode. ery high mobilities can lead to very high speed devices (cell phone electronics). Gate can be anywhere between source and drain. 4
Transistor operation and transconductance Basic transistor operation: I load G One obvious figure of merit for a transistor is transconductance: I gm Transistors with a higher g m are better switches than those with lower values. G The MOS system n-type p-type At left are band diagrams for metal-insulator-semiconductor stacks. These are drawn assuming flat bands; that is, negligible charge transfer at interfaces to cause band bending, + negligible surface states. For these ideal cases, with no bias on the metal, the charge density of the semiconductor = the full doped density right up to the interface. 5
Band picture + inversion Ideal system when metal is biased: Accumulation mode: gate bias bends bands to enhance free charge density in plane at insulatorsemiconductor interface. epletion mode: gate bias bends bands to reduce free charge density in plane at insulator-semiconductor interface. Inversion mode: gate bias bends bands so much that the free charge density in plane at insulatorsemiconductor interface has the opposite sign as the doping! Threshold voltage The threshold voltage T is defined as the gate voltage required to produce inversion in the channel. T depends on the band structure, the doping level of the semiconductor, and the geometry of the device (oxide thickness, oxide + SC dielectric constants, etc.). Can be calculated in certain models (will do later). Often determined empirically. For an ideal intrinsic MOS stack, threshold voltage is zero. Assumes no surface states + bands flat when G =0. In following, assume T is just a device parameter. 6
Basic transistor operation and the linear regime from Pierret Assume first that S = 0, and ( G - T ) >>. gradual channel C x = capacitance per unit area of gate oxide 2d charge density in inversion layer: en C ( ) 2d x G T Total current from this layer: W I d = W en2d µ µ Cx ( G T ) L L Basic transistor operation and the linear regime So, for small source-drain biases, W I d µ Cx ( G T ) L FET acts here like gate-controlled variable resistor: I << I ( G T W g m = µ G L Higher gate capacitance, higher transconductance! Knowing device dimensions, can measure I vs. G and calculate the mobility from this linear regime. Mobility found in FETs tends to be lower than bulk: ) C x increasing G Gate field enhances interface scattering. 7
Saturation regime - physical picture from Pierret What happens at higher sourcedrain voltages? That is, what about when > ~ ( G - T )? Physically, the thickness and charge density of the inversion layer (channel) shrinks along the length of the channel. When inversion layer just vanishes at drain, device is at pinch-off. At higher values of, for long channels I stops changing. Result is saturation regime. Saturation regime, quantitative: square law efine the channel direction as y. Local potential in channel = φ(y) Local charge density = 0 L C ( φ( y)) x G T Local current: dφ I( y) = Wµ Cx( G T φ( y)) dy I( y) dy = I L = Wµ C ( φ) dφ x 0 G T Result: I Wµ C = L x ( G ) T 2 2 0, G, sat T 8
Square law I Wµ C = L x ( G ) T 2 2 0, G, sat Since I only increases until pinch-off, can use above formula to find both pinch-off voltage and saturation current: T, sat = G T I W C = µ 2L x 2, sat ( G T ) So, assuming constant mobility and ignoring changes in depletion width down length of channel, we find that saturation current scales quadratically with ( G - T ). This provides another way of inferring mobility. (Tacit assumption: source, drain contact resistances are negligible.) What sets equilibrium depletion width? First, recall some definitions: E i = energy of the middle of the gap in the semiconductor. φ S = potential at sc-oxide interface. φ F = bulk (E - -E F )/e φ(x) = (1/e)[E i (bulk)-e i (x) n i = intrinsic carrier density = N N exp( E / 2k T ) C g B 9
What sets equilibrium depletion width? kbt ln( N A / ni ) For nondegenerate semiconductors, φ = e F kbt ln( N / ni ) e Middle of depletion: φ = φ S F Onset of inversion: φ = 2φ S F elta depletion Exact self-consistent solution shows inversion charge confined to very thin layer at interface. epletion width increases only slightly once inversion occurs. Approximation: further gating only affects inversion charge. epletion width at some surface potential: 1/ 2 2 ε sε0 d = φs en epletion width at inversion: 1/ 2ε sε 0 dt = 2φ F en A A 2 10
11 Bulk charge picture Takes into account variation in depletion width along channel. Suppose the depletion width near source and drain under no bias is d T, and under bias it depends locally on position, d(y). The induced charge density at position y is then ] ) ( [ ) ( T A T G x d y d qn C + φ inversion layer free charge additional exposed acceptors efining x T A d C d en and substituting our delta-depletion results for the ds gives + 1 2 1 F W T G x C φ φ φ Bulk charge picture With this more careful accounting, we find a more exact expression for the I - characteristics as a function of gate voltage: T G sat F F F d T G x L C W I + + =, 2 3/ 2 0, 4 3 1 2 1 3 4 2 ) ( φ φ φ µ Neither the bulk charge picture nor the square law picture predict saturation - it has to be inserted by hand into the model. Complete numerical solution of the whole system does, of course, give pretty nice results, including saturation.
What performance issues are important? Speed (10 GHz) Threshold voltage (< ~0.5 ) On-off ratio (> 10000) Off-current & sub-threshold behavior urability (mean time to failure) What limits speed? Gate capacitance Switching FET requires moving charge off and on the gate. Assuming low capacitance and high conductance leads, the maximum frequency possible is set by when the gate admittance becomes comparable to the transconductance: gm µ sat fmax = 2 2πC 2πL Time-of-flight x Clearly in some limit one is limited by the speed with which carriers can traverse the device. 12
Why are low thresholds important? In some sense, threshold voltages show how efficient your switching is - until inversion, one pays the cost of charging up the gate without getting any of the transistor benefit. Also, power dissipation varies like G2, so being able to run at lower voltages would produce a big savings in heating! Trend: c. 1980, TTL logic: G ~ 5. Now, G ~ 2.2 on CPU. On/off ratios and off-currents A transistor is only a good switch if, when it s off, it s really off. Typical on/off current ratios must be ~ 10 4, or else these subthreshold source-drain currents end up dissipating an enormous amount of power. Transistor should also switch sharply - it s subthreshold properties need to be good. 13
urability Commercially viable transistors need to last a long time! Remember, ~ 10 7 transistors per chip, each operating 10 9 times per second. Only a few failures ruin the chip. When was the last time the CPU died in any computer you own? The mean time to failure is extremely long! Most common transistor failure mode: gate oxide breakdown. Not suprising: ~ 3 across 3 nm of oxide = 10 9 /m (!). Summary Transistors are three-terminal devices, and MOSFETs are the most commonly used type in high technology. Normally off devices, with linear source-drain I curves at low source-drain bias once gate voltage exceeds threshold for inversion. I curves saturate at high bias, with saturation currents depending strongly (roughly quadratically) on gate voltage. Performance criteria clearly depend both on device geometry and on materials choices. MOSFETs are only as good as they are because of decades of exacting materials development. 14
Next time: emands of the electronics industry for high performance transistors. The semiconductor roadmap, and signs of trouble ahead. 15
emands of electronics industry Last time, we got a quick overview of the silicon MOSFET. Today, we will examine the state-of-the-art in MOSFET technology, with an eye toward what the expected requirements are for the future. Keep an eye out for nano-related issues that will crop up. Feature size [ µ m] 0.01 Ongoing trends: Moore s (1st) Law The number of components per IC doubles roughly once every 18 months. Lateral feature sizes have also decreased exponentially with time. 10 1 0.1 1980 1990 2000 2010 Year Transistors / CPU 1G 100M 10M 1M 100k 10k 1k 100 1970 1980 1990 2000 Year Breaking the 100 nm barrier in production in 2003. These trends cannot continue forever. What will replace traditional Si? Why will that replacement occur? ECONOMICS. 1
Ongoing trends: Moore s (2nd) Law 10000 1000 Cost [$M] 100 10 1 1970 1980 1990 2000 2010 Year While cost per complexity plummets exponentially (35%/yr), cost of production plant rises exponentially. By 2025, projected trend says fab plant cost ~ $1 trillion. Clearly this trend cannot continue either. International Technology Roadmap for Semiconductors These trends have been continuing by design for the last ~ 10 years. SEMATECH: international consortium of semiconductor manufacturers set goals, fund research of common interest to them all. Includes such US players as: AM, Agere Systems, Hewlett-Packard, Hynix, Infineon Technologies, IBM, Intel, Motorola, Philips, STMicroelectronics.TSMC, and Texas Instruments Identifies technology nodes and spec/cost/performance targets. These days, nodes identified by RAM pitch: 2
ITRS production cycle Technology nodes are labeled by production research demonstration must come well ahead of any node goal. Basic parts 3
Current production factoids: Typical Pentium: ~ 10 7 transistors, total chip area of 310 mm 2 Active area of transistors is ~ 28 mm 2 Cost per transistor currently between 50 and 100 microcents (!). Total number of processing steps needed for one chip: hundreds Total number of masks needed for one chip: ~ 30-40 Acceptable total yield ~ 50% (!) State-of-the-art: Si material Growth method: Czochralski A seed crystal is attached to slowly rotating rod, and is dipped into Si at just over the melting point. The rod is slowly withdrawn from the melt. Rate is increased at end to avoid impurity contamination. iameter: 300 mm Specs needed for 99% good wafers: Site flatness: < 130 nm Number of particles: < 120/wafer Surface metal contamination: < 10 10 at/cm 2 Iron concentration: < 10 10 at/cm 3 Stacking faults: < 1/cm 2 http://www.techfak.uni-kiel.de/matwis/amat/elmat_en/kap_5/illustr/i5_1_1.html 4
State-of-the-art: Lithography Light source: 248 nm Phase compensated masks + chemically amplified resists allow smallest features (e.g. FET channel length) to be ~ 90 nm. Resist pattern edge roughness: < 7 nm (3 σ) Particle contamination: < 2000/m 2 of size 200 nm or greater Number of defects in patterned film: < 0.08/cm 2 of 70 nm Overlay accuracy of mask: 45 nm State-of-the-art: MOSFET silicide spacer source n-type Poly-Si Gate oxide p-type drain n-type Intel 2Q 2003: Oxide thickness: ~ 3 nm Channel length: ~ 90 nm Gate position: ~ 6 nm (!) Characteristic time: ~ 1.6 ps Subthreshold leakage: 0.01 µa/micron Parasitic R S contribution: < 16% Energy per switching: 0.35 fj Static power dissipation: 5.6 nw 5
State-of-the-art: power Supply voltage in processor core: ~ 1.2 High performance processor power dissipation (with heatsink): 130 W Battery-powered processor power dissipation: 2.4 W Can crunch some numbers on high-performance system. Say 10 7 transistors running at 1.5 GHz gives that 130 W figure. Now consider 10 8 transistors in the same area, operating at 10 GHz, for example. Such a processor made with present-day designs and approaches would dissipate ~ 10 kw / cm 2 (!!) This is comparable to the power density radiated by a rocket engine. State-of-the-art: reliability evice early failures (in first 4000 hours): 50 ppm Long-term failures (in first 10 9 hours): 10-100 ppm Electrostatic protection survival: 10 /µm Testing is done under accelerated failure conditions typically running devices at higher-than-normal temperatures, for example. 6
Reading the roadmap White = manufacturable solutions known and being optimized. Yellow = manufacturable solutions known and demonstrated, but not yet in practice (often, too expensive / yields too low / too new to be optimized yet). Red = brick wall = no known manufacturable (!) solution to given problem / means of meeting criterion. Remember the ramp-up cycle. If there s a red item and it s less than two years away, the issue is a very serious one. Roadmap goes out ~ 10 years, but is constantly under revision. Near-term demands (2007): Si material Site flatness: < 65 nm (critical, but hard to measure) Number of particles: < 77/wafer (below measurable threshold) Surface metal contamination: < 10 10 at/cm 2 (more critical) Iron concentration: < 10 10 at/cm 3 (more critical) Stacking faults: < 0.3/cm 2 (factor of 3 over current) General trends: Even when current tolerances don t change by much, their importance increases. Running into metrology problems - don t have adequate tools to efficiently assess whether criteria are being met. 7
Near-term demands (2007): Lithography Light source: 193 nm? 157 nm? X-ray? FET channel length: 35 nm. Resist pattern edge roughness: < 3 nm (3 σ) Particle contamination: < 1500/m 2 of size 100 nm or greater Number of defects in patterned film: < 0.04/cm 2 of 40 nm Overlay accuracy of mask: 23 nm This is particularly alarming: Running into physical limitations of lithographic patterning (not just optical, but polymer resist based in general). Near-term demands (2007): MOSFET Equivalent oxide thickness: ~ 1 nm Channel length: ~ 25 nm Gate position: ~ 2 nm Characteristic time: < 0.68 ps Subthreshold leakage: 1 µa/micron Parasitic R S contribution: < 20% Energy per switching: 0.032 fj Static power dissipation: 53 nw 15nm 25 nm Biggest problems: oxide thickness, contact resistances, and leakage problems due to tunneling / thermal emission. 8
Long-term demands (2016): Si material Wafer size (!): 450 mm (How does one grow and polish these?) Site flatness: < 22 nm Number of particles: < 77/wafer (below measurable threshold) Surface metal contamination: < 10 10 at/cm 2 (more critical) Iron concentration: < 10 10 at/cm 3 (more critical) Stacking faults: < 0.1/cm 2 (another factor of 3) Most requirements continue increasing criticality. Metrology even more of a problem. Larger wafer size desired, but may not happen. Long-term demands (2016): Lithography Light source: X-ray? E-beam? FET channel length: 9 nm. Resist pattern edge roughness: < 1 nm (3 σ) Particle contamination: < 500/m 2 of size 50 nm or greater Number of defects in patterned film: < 0.01/cm 2 of 10 nm Overlay accuracy of mask: 9 nm Noone knows how to do this. Biggest problems: Single-nm alignments across ~ 2cm chip, + across 450 mm wafers. Metrology. 9
Long-term demands (2016): MOSFETs Equivalent oxide thickness: ~ 0.4 nm Channel length: ~ 9 nm Characteristic time: < 0.15 ps Subthreshold leakage: 10 µa/micron Parasitic R S contribution: < 35% Energy per switching: 0.002 fj Static power dissipation: 110 nw Intel can make THz, 10 nm channel transistors, but not in bulk. Several finite-size problems crop up (contact resistances again) Irreversibly changing 1 to 0 costs, minimally, k B T ln 2 = 0.002 fj (!) General observations We re running out of time fast for standard CMOS processing if we want to continue Moore s (1st) law. At the nm scale, lack of (fast) metrology is a real killer. Not all coming problems are simple engineering or process development issues: We have entered the era of material limited device scaling. We re approaching the era of physics-limited device scaling in certain aspects as well. 10
Is industry considering alternatives? The 2001 ITRS is the first roadmap to include a section on Emerging Research evices. Planners well aware that they need to be looking at: Nonclassical CMOS (ertical/ FIN / double-gate MOSFETS) Alternative devices (single-electron transistors) Hybrid devices (nanotube FETs) Novel architectures (defect tolerance, cellular automata) Really novel architectures (molecular computers, quantum computers) Roles for nano Pure research Fundamental physics and chemistry of these materials at nm scale. Understanding new phenomena as they arise / become relevant. Learning the science of possible new architectures. Applied research Nanomaterials including resists. Metrology: how do you measure critical properties on these length scales? 11
Summary and conclusions Moore s Laws are obeyed by design, not by accident. Electronics industry wants to continue aggressive scaling, but faces many challenges along the way. Nano can and must play a role in addressing these challenges / opportunities. Either we ll make some significant paradigmatic shift within 10-15 years, or computer hardware performance will plateau (e.g. passenger airplane speeds). One of the major limiting problems is economic. Next time: MOSFET scaling in detail: what s the physics? 12
MOSFET scaling Can we just keep miniaturizing conventional FETs? No - new physical effects kick in at small length scales. Not all these effects are bad, but certainly make design more complicated. Some can be mitigated by particular scaling schemes. What kind of variations on CMOS are proposed, and why? How far can these variations take us - when does it become essential to change to a new architecture based on new operating principles? What happens in smaller transistors? If we simply shrink all length scales, a number of physical effects can become relevant that are unimportant in larger MOSFETs: Channel shortening Punch-through Tunneling / thermionic leakage Threshold voltage variation with drain bias Finite width effects elocity saturation Field-dependent mobility Avalanche breakdown Oxide failure 1
Where is all the action? We derived transistor characteristics (e.g. square law) by looking at the charge in this box area under the gate. Gate Charge Approximation (GCA): assumes that charge distribution in that box is dominated by effects from gate field. That is, F >> for electric fields in that region. y F x Anything that affects charge distribution in or very near this box will produce changes away from our simple model predictions. Channel shortening First example happens when approaches ( G - T ). In long channel devices, we get pinchoff and saturation of I : L- L In really short devices, L can be a significant fraction of L! What happens then? L Remember, F x is large over L - that s where most of the source-drain voltage is dropped. While inversion layer is gone, drift is enhanced by high electric field there: result is a boost in I as is increased beyond dsat. 2
Channel shortening Semiempirical formula based on square law picture: I Wµ C L 2 2 x = ( G T ) 1 I Wµ C L ( ) 2 2 x G T sat 1 ( + λ ) ( + λ ) No true saturation. Can even have problems at gate voltages that shold be below threshold! Punch-through In sufficiently small devices, the depletion regions from the source and drain can actually merge. This is particularly awkward since the drain depletion region is strongly altered by. Gate only influences small volume near surface. Current can flow through depletion zone - space-charge-limited ~ 2. How to mitigate? Higher doping concentration in bulk wafer leads to shorter depletion widths, though there is an upper limit to reasonable doping. 3
Tunneling / thermionic leakage Consider an n-mosfet below threshold, but with a finite source-drain bias. Plot the energy of the conduction band as a function of position along the channel. decreasing device length, increasing bias. rain-induced Barrier Lowering (IBL). Thermionic leakage / tunneling Both processes can be relevant. Tunneling matters more for smaller devices; thermionic emission matters more for higher temperatures. Biggest problem is that these can lead to substantial off-currents and power dissipation! 4
Threshold voltage variation Consider electrostatic potential contours as devices are shortened. For fixed G, shorter channel means φ more dominated by, just from geometry. Result: Apparent T can be quite different in short devices! Trends: Shorter channel = lower threshold voltage Higher = lower threshold voltage. Thinner oxide = higher threshold voltage. Finite width effects Top view of MOSFET: source gate drain Some kind of isolation, to prevent gate from affecting more semiconductor than desired. As overall devices shrink, isolation becomes increasingly important to avoid parasitic effects. W 5
Finite width effects source gate drain Best forms of isolation: oxide oxide Field-dependent mobility We mentioned this briefly before. To keep up with source-drain field, we must scale oxide to be thinner. Thinner oxide = higher gate field. Higher gate field = enhanced surface scattering at channel-oxide interface = lower effective mobility. 3 ~ 1/ µ eff F G 6
elocity saturation Electric fields can get quite large in short channel devices. oes our simple mobility picture still work? No: if velocity of carriers becomes large enough, they can lose energy by inelastic processes (e.g. shedding optical phonons). If L is long compared to the inelastic scattering length, one sees velocity saturation: Results: I WC ( ) v sat This is a significant reduction in current. Saturation current now depends linearly on G - T rather than almost quadratically. x G T sat elocity saturation Some example numbers: Si, 300 K v sat ~ 10 7 cm/s when F y > ~ 3 x 10 4 /cm for electrons, when F y > ~ 10 5 /cm for holes. real data model with v sat model with no v sat 7
elocity overshoot What happens if channel is shorter than inelastic scattering length? elocity overshoot: can get channel velocities higher than what would be expected for simple equilibrium transport Result can be odd features in transistor characteristics: Nonmonotonic behavior of I due to overshoot. Higher fields = more inelastic scattering = shorter inelastic length. Other potential problems: Avalanche breakdown: At high enough energies (regions with big electric fields, like drain pinch-off area) carriers can collisionally produce electron-hole pairs. These pairs may not be bound, and can then also accelerate, leading to more pairs. Result is runaway I not controlled by G. Parasitic transistor action: Can get odd unintentional bipolar transistor behavior between source, drain, and bulk: 8
Oxide failure Unsurprisingly, very thin gate oxides tend to be fragile. Short-term failure: static electricity can easily cause local electric fields high enough to kill oxides. Mechanism: high energy electrons accelerated by large fields can actually break bonds - can effectively introduce enough defect states in gap to permit sufficient conduction to get runaway failure. Oxide failure Long term failure caused by accumulated damage: Certain probability per electron of damage (~ F y ). As damage accumulates, leakage currents go up, increasing damage rate. field-emission from defect sites. initial leakage (tunneling +thermionic emission) 9
Oxide failure Still not well-understood microscopically. Can see weird things - soft breakdown, healing On one hand, would think this will be less of a problem when one switches to thicker layers of alternative (high-k) dielectrics materials. However: thermal SiO 2 has among the best breakdown field properties of any oxide. Typical fields for failure are several 10 9 /m. In contrast, alumina can be as much as 5 times worse, and only has a dielectric constant of ~ 9. Also, band offset concerns: SiO 2 works well because its bands don t line up with doped Si. More exotic high-k materials (SrTiO 3 ) may not be so fortunate. Contact resistances The source and drain ohmic contacts (metal to polysilicon to highly doped wafer material) are ohmic, but have some specific contact resistivity. Current requirements: R cont < 4.7 x 10-7 Ω-cm 2. As cross-sections of contacts decrease, the actual resistance goes up like 1/contact area unless materials are modified. Remember, our FET formulae are all derived assuming negligible series resistance from sources other than the channel. 10
General scaling approaches Two major scaling approaches: Constant field scaling - reduces both sizes and voltages to maintain constant relative electric fields. Pro: avoids nasty high field issues, plus competition between gate and drain. Con: can t keep reducing voltages forever. Constant voltage scaling - keeps voltages fixed as dimensions are scaled. Pro: maintains voltages at reasonable levels. Con: run into all the high field effects described above. General scaling approaches Consider reducing all FET linear dimensions by a factor α. Here s the table of how things must scale: 11
Empirical scaling formulae Assuming effective channel length l in microns, empirical data on good transistors predicts: 0.77 t ox max(21 l,14 l 0.55 ) oxide thickness (nm) 5 l N B 0.75 4 10 l 16 1.6 supply voltage () dopant density in bulk (cm -3 ) opant density must go up to avoid punch-through. From these empirical formula, can derive other quantities: U 2 g Cx 2 = 2.2 / 10 l 4 2.75 minimal switching energy (can run into discreteness of levels.) th 0.55l 2.3 threshold decrease due to IBL. Summary: A number of device physics issues crop up if one attempts to aggressively scale standard Si MOSFETs. Typical resulting problems: gate no longer effectively controls source-drain current substantial currents even when device should be off carrier behavior differs from that in larger devices There are ways of scaling that minimize these effects, but there s no avoiding the eventual impending demise of scaling this device configuration. 12
Next time: There are a number of competing candidate CMOS solutions to try and get around both the device engineering problems discussed today, and some of the fabrication and diagnostic issues mentioned last time. Typical approaches: Change the gate geometry substantially to mitigate field problems. Change overall device shape to improve fabrication process and yield. Materials changes. 13