VLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)
SYLLABUS UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits. 2
CONTENTS: VLSI design flow MOS layers Stick Diagrams Design Rules and Layout diagrams 2µm Design Rules Layout Diagrams for Inverter, Logic gates Scaling of MOS 3
VLSI design flow 4
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MOS Layers : There are 4 layers N-diffusion P-diffusion Poly Si Metal These layers are isolated by one another by thick or thin silicon dioxide insulating layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel. 6
Metal Interconnect Layers Ox3 Via Metal2 Active contact Ox2 Metal1 Ox1 n+ n+ n+ n+ Poly Si p-substrate 7
Stick Diagrams : A stick diagram is a cartoon of a layout. Does show all components/ vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries 8
Key idea: "Stick figure cartoon" of a layout Useful for planning layout relative placement of transistors assignment of signals to layers connections between cells cell hierarchy 9
Rules for Drawing Stick Diagrams : Metal 1 Poly Si N-diffusion P-diffusion Rule 1: When two or more sticks of the same type cross or touch other that represents electrical contact. 10
Rule 2: When two or more sticks of different type cross or touch other there is no electrical contact.(if contact is needed show explicitly) 11
Rule 3: When a poly crosses diffusion it represents MOSFET. If contact is shown it is not transistor. nmosfet pmosfet nmosfet (Depletion Mode) 12
nmos Design Style: Step 1:Draw metal V DD and GND rails in parallel leaving sufficient space for circuit components between them. V DD V DD GND Step 2: Thinox (green) paths are drawn between rails for inverter & inverter logic. V in V OUT GND 13
STICK DIAGRAMS P- Diffusion n- Diffusion Poly silicon Metal 1 Contact cut PMOS Enhancement Transistor NMOS Enhancement Transistor NMOS Depletion transistor N implant NPN Bipolar Transistor Demarcation line Substrate contact 14 Buried Contact
Step 3: Connect poly over thinox wherever transistor required. 15
Step 4: Connect metal wherever is required and create contact for connection. V DD Depletion mode nmos V out V OUT V in V in GND 16
NMOS INVERTER STICK DIAGRAM D VDD S D B A GND 17
CMOS INVERTER STICK DIAGRAM VDD GND FIG 1 Supply rails 18
CMOS INVERTER STICK DIAGRAM VDD S D PMOS S D NMOS GN D Fig 2 Drawing Pmos and Nmos Transistors between Supply rails 19
CMOS INVERTER STICK DIAGRAM VDD A S D PMOS S D NMOS GND Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input With same gate poly silicon metal 20
CMOS INVERTER STICK DIAGRAM VDD A S D PMOS S D NMOS GND Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1 21
CMOS INVERTER STICK DIAGRAM VDD S D PMOS A B S D NMOS GND Fig 5 Take the output with the poly silicon metal 22
CMOS INVERTER STICK DIAGRAM VDD A S S D D PMOS B NMOS GND Fig 6 Connect the source of Pmos to VDD and Nmos to GND 23
CMOS INVERTER STICK DIAGRAM CONTACT VDD S D PMOS A B S D NMOS GND Fig 7 Connect the contact cuts where the different metals are connected 24
CMOS INVERTER STICK DIAGRAM CONTACT VDD A S S D D PMOS B NMOS Substrate contact GND Fig 8 Final CMOS Inverter 25
CMOS NAND GATE STICK DIAGRAM VDD FIG 9 Supply rails GND 26
CMOS NAND GATE STICK DIAGRAM VDD GND Fig 10 Drawing P and N Diffusion between Supply rails 27
CMOS NAND GATE STICK DIAGRAM VDD S D D S C S D S D A B GND Fig 11 Drawing the poly silicon for two different inputs and identify the source and drain 28
CMOS NAND GATE STICK DIAGRAM VDD S D D S C S D S D A B GND Fig 12 Connect the source of Pmos to VDD and Nmos to GND and subtrate contacts of both 29
CMOS NAND GATE STICK DIAGRAM VDD S D D S C S D S D A B GND Fig 13 Draw the output connections 30
CMOS NAND GATE STICK DIAGRAM VDD S D D S C S D S D A B GND Fig 14 Connect the contact cuts where the different metals are connected 31
Cmos Nor GATE Vdd contact Vdd Demarcation Line s D s D Ploy(G) Ploy(G) A B Vout(A nand B) D s Ploy(G) D s Ploy(G) Vss contact Vss 32
Cmos Nor GATE 33
Power A Out C B Ground 34
BiCmos inverter Vdd contact Vdd Demarcation Line Vout 35 Vss contact Vss
Encodings for NMOS process: 36
Encodings for CMOS process: Figure shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows when a p- transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely 37
Encoding for BJT and MOSFETs: layers in an nmos chip consists of a p-type substrate paths of n-type diffusion a thin layer of silicon dioxide paths of polycrystalline silicon a thick layer of silicon dioxide paths of metal (usually aluminium) a further thick layer of silicon dioxide 38
LAYOUT 39
There are primarily two approaches in describing the design rules 1.Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen that a design can be easily ported over a cross section of industrial process,making the layout portable.scaling can be easily done by simply changing the value. 2.Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm) and therefore can exploit the features of a given process to a maximum degree. 40
What is Via? It is used to connect higher level metals from metal1 connection The direct connections between metal, polysilicon, and diffusion use intermediate layers such as the contact-cut and the buried-contact layers. The entire chip is typically covered with a layer of protective coating called overglass 41
CMOS Process Layers Layer Color Representation Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Yellow Green Green Red Blue Magenta Black Black Black 42
2λ 2λ P diffusion P diffusion P diffusion P diffusion N diffusion N diffusion 2λ 1λ 3λ METAL 1 4λ 3λ 4λ METAL 1 43
Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select 3 3 2 Contact or Via Hole 2 2 Metal1 Metal2 3 3 4 3 44
Transistor Layout Transistor 1 3 2 5 45
Via s and Contacts 2 1 Via 1 4 5 Metal to Active Contact 1 Metal to Poly Contact 3 2 2 2 46
Select Layer 3 2 2 Select 1 3 3 2 5 Substrate Well 47
4λ 1λ 1λ 2λ 4λ 4λ 2λ 4λ 2λ 3λ 48
NMOS ENHANCEMENT PMOS ENHANCEMENT NMOS DEPLETION 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 6λ x 6λ 49
LAMBDA BSED RULES 50
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Lambda based Design Rules: Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable λ -based design rules, which are valid for a range of fabrication technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ. All width and spacing rules are specified in terms of the parameter λ. 60
Design rules for the diffusion layers and metal layers Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ. Similarly it shows for other layers. 61
Design rules for transistors and gate over hang distance 62 Figure shows the design rule for the transistor, and it also shows that the poly should extend for a minimum of 2λ beyond the diffusion boundaries.(gate over hang distance)
Via VIA is used to connect higher level metals from metal1 connection. Figure shows the design rules for contact cuts and Vias. The design rule for contact is minimum 2λx2λ and same is applicable for a Via. 63
Buried contact and Butting contact Buried contact is made down each layer to be joined Butting contact The layers are butted together in such a way the two contact cuts become contiguous 64
CMOS LAMBDA BASED DESIGN RULES: 65 Figure shows the rules to be followed in CMOS well processes to accommodate both n and p transistors
CMOS Inverter Layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p + 66
SCHEMATIC AND LAYOUT OF BASIC GATES a) CMOS INVERTER NOT GATE 67 Schematic Stick diagram Layout
The CMOS NOT Gate Vp Contact Cut Vp X n-well x x x X X x X Gnd Gnd 68
Alternate Layout of NOT Gate Vp Vp X X x x X X Gnd x Gnd x 69
b) NAND GATE Schematic Stick diagram Layout 70
NAND2 Layout Vp Vp a.b X X X Gnd a b X X a.b Gnd a b 71
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NOR2 Layout Vp Vp X X a b a b Gnd a b Gnd X X a b X 73
TRANSMISSION GATE Symbol schematic stick diagram layout 74
Example: Inverter 75
Layout using Electric Inverter, contd.. 76
Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 by 40 77
NAND3 (using Electric), contd. 78
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Scaling VLSI technology is constantly evolving towards smaller line widths Reduced feature size generally leads to better / faster performance More gate / chip More accurate description of modern technology is ULSI (ultra large scale integration 80
Scaling Factors In our discussions we will consider 2 scaling factors, α and β 1/ β is the scaling factor for VDD and oxide thickness D 1/ α is scaling factor for all other linear dimensions We will assume electric field is kept constant 81
Scaling Factors for Device Parameters Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125-129 It is important that you understand how the following parameters are effected by scaling. Gate Area Gate Capacitance per unit area Gate Capacitance Charge in Channel Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipation Per Unit Area Power - Speed Product 82
MOSFET Scaling SCALING - refers to ordered reduction in dimensions of the MOSFET and other VLSI features Reduce Size of VLSI chips. Change operational characteristics of MOSFETs and parasitic. Physical limits restrict degree of scaling that can be achieved. Constant Field Scaling Constant Voltage Scaling Lateral Scaling 83
Constant Field Scaling The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scalefactor α (such that E is unchanged): all dimensions, including those vertical to the surface (1/α) device voltages (1/α) the concentration densities (α). 84
Constant Voltage Scaling V dd is kept constant. All dimensions, including those vertical to the surface are scaled. Concentration densities are scaled. 85
Lateral Scaling Only the gate length is scaled L = 1/α (gate-shrink). Year Feature Size(μm) 1980 5.0 1983 3.5 1985 2.5 1987 1.75 1989 1.25 1991 1.0 1993 0.8 1995 0.6 86
87 PARAMETER SCALING MODEL Constant Constant Lateral Field Voltage Length (L) 1/α 1/α 1/α Width (W) 1/α 1/α 1 Supply Voltage (V) 1/α 1 1 Gate Oxide thickness (tox) 1/α 1/α 1 Junction depth (Xj) 1/α 1/α 1 Current (I) 1/α α α Power Dissipation (P) 1/α 2 α α Electric Field 1 α 1 Load Capacitance (C) 1/α 1/α 1/α Gate Delay (T) 1/α 1/α 2 1/α 2
Scaling of Interconnects Resistance of track R ~ L / wt R (scaled) ~ (L / α) / ( (w/ α )* (t /α)) R(scaled) = αr therefore resistance increases with scaling A t w L B 88
Scaling - Time Constant Time constant of track connected to gate, T = R * Cg T(scaled) = α R * (β / α 2 ) *Cg = (β / α) *R*Cg Let β = α, therefore T is unscaled! Therefore delays in tracks don t reduce with scaling Therefore as tracks get proportionately larger, effect gets worse Cross talk between connections gets worse because of reduced spacing 89
Scaling of MOS and circuit parameter 90
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