Overview of Program Objective: Competitive Low-Cost Thin-Film Varactor Technology coplanar waveguide (CPW) capacitor ground signal ground Si substrate etched troughs Focus of Our Program! Reproducibility! Inexpensive substrates! Standard growth/processing steps! Low tuning voltages! Compatible with low-cost packaging Inexpensive varactor diode replacement technology Optimal use of thin-film for circuit performance Strong potential for integration into existing IC processes Cost + Performance + Manufacture Integrated Monolithic Capacitors using Sputtered/MOCVD material on low-cost substrates Capacitance/Area [pf/um^2] 3-6 2.5-6 2-6.5-6 -6 5-7 Capacitance Density vs. Voltage -5 - -5 5 5 Voltage [V]
Nonlinear Capacitance The capacitance nonlinearity can be described empirically by CV ( ) = C + ξ ( V / V ) max 2 C zero-bias capacitance ξ "tunability" parameter V Breakdown voltage For nm film thicknesses, we typically have capacitance densities of C =5fF/um^2 max Capacitance/Area [pf/um^2] Capacitance Density vs. Voltage 3-6 2.5-6 2-6.5-6 -6 5-7 -5 - -5 5 5 Voltage [V] V max is set by the breakdown field and film thickness. For most of our films, the breakdown field is ~-2 MV/cm At V=V max the capacitance has a minimum value C min. We usually call the ratio C /C min the tunability. A 3: tunability would have C /C min =3. Other groups define tunability differently. With this definition: ξ 2 C = Cmin
Parallel-Plate Plate Capacitor: Layout Challenges Problems Phase shifters require small capacitors Small active areas required Top electrode lithography crucial Approach two capacitors in series Tight alignment tolerances 3 Required Area, µm 2 25 2 5 5 Film ε r () = 25.4 pf.3 pf 5 5 2 Film Thickness, Angstroms.2 pf. pf Ease of processing larger contact area no contact to bottom electrode Defect density higher yield graceful degradation Power handling double allowed RF voltage swing
Planar Capacitor Design C w w w Rs G l ρ Rs (3w+ 2 w/ 3) t l CV ( ) = C fringe ε rεwl 2 t + ξ ( V / V ) max 2 w 3w G = ωc tanδ C fringe ε ε w(3w t + l)
Losses in Varactors Conductor Losses Q c ωr C s 2tt = 2 ω 3ρw ε rε Effect of capacitor layout on RF losses 5 t = Å t = 75Å ε r = 25 tanδ =.6 Dielectric Losses ωc Q d = G tanδ Measured Q 4 3 2 w = 2 microns Total Q-factor for Device w = 5 microns Q tot Im( Z) Re( Z) = Q Q c + + 2 d Qc Q d 5 5 2, GHz
Projected Q Limits Conductor Losses t = 2Å t = 75Å e r = 25 Q Qser ser 8 6 4 2 w=3mm w=2mm w=mm 5 5 2, GHz Total Losses 5 4 3 w = mm tand =.2 Qtot Qser 2 5 5 2, GHz tand =.5 tand =. tand =.2
INITIAL PROCESS METHOD Starting Material (a) (d) Etch with RIE (SF6/Ar/O2), Etch using Cl2. Etch with HF. (b) (e) Deposition, Window Etch with RIE (SF6/Ar/O2) Deposit (PECVD, 25C) Top Contact Metallization (c) Possible Layer Formation Between /. (f) Window Etch Very critical step that defines capacitor areas. Very likely to damage the film. Possibility of leaving a thin layer (lowers overall capacitance & tunability) and/or thinning the film.
New Process Photographs Top View RF Device Fabrication w w w l w 3w w = lithographic design rule Oxide Window for Top metal SiO2 Window Oxide Evaporation Two Capacitors in Series Top Metal & Oxide Evaporation Ti//Au Top metal buried under SiO2 Crossover Layer Thick Metal Ti/A Ti/A u u SiO2 Ti//A Ti//Au SiO2 u base electrode Side View Window in for Thick metal Contact Etch Thick Metal Thick Metal Contact