Common Source Stage Miller Approximation ZVTC Analysis Backgate Effect Claudio Talarico Gonzaga University

Common Source Stage Miller Approximation ZVTC Analysis Backgate Effect Claudio Talarico Gonzaga University Sources: most of the figures were provided by B. Murmann

CS with Resistive Load V DD V out R D Bias Point (Q) v out i D = I D i d I d V OUT Signal v in V out = v OUT = V OUT v out V in Bias V IN - v in V IN V in v in - g m v in r o R D v out - A v = 2I D V OV R D r o 2I D V OV R D R g m often but not always!!! EE 303 Common Source Stage 2

Does r o matter? r o can be neglected in the gain calculation as long as the desired gain A v is much less than the intrinsic gain g m r o A V = g m (R D r o ) A V = g m R D g m r o g m R D = A V A V g m r o A V for A V <<g m r o v IN V in I B Vv OUT out Intrinsic Gain g m r o 2I D V OV = 2 λi D λv OV NOTE: The small signal parameters (that is g m and r o ) are determined by the DC bias point EE 303 Common Source Stage 3

Upper Bound on Gain In the basic common source stage R D performs two conflicting tasks it translates the device s drain current i d into the output voltage v out. it sets the drain bias voltage (V DS ) of the MOSFET This creates an upper bound on the achievable small signal voltage gain A V 2I D V OV R D = 2 V R D V OV V OUT A V max =2 V RDmax V OV min = 2 V DD V OV min V OV min 2 V DD V OV min V DD A B V IN V T NOTE: only a limited range of the VTC is useful for amplification V T C D For V IN large: V OUT V R DD ON (resistivedivider) R D R ON V IN V DD cutoff saturation triode EE 303 Common Source Stage 4

Voltage Gain and Drain Biasing Considerations () V IN I D V DS =V DD R D I D For a given I D if R D ( V DS ) the bias point Q moves toward triode region I D V IN5 Small R D Intercepts at V DD /R D Large R D D C Load line I D = (V DD -V OUT )/R D V IN4 V IN3 B V IN2 A V DD V IN V DS = V OUT EE 303 Common Source Stage 5

Voltage Gain and Drain Biasing Considerations (2) I d For a given I D if R D the voltage gain Intercepts at V DD /R D Small R D Q = (V DS,I D ) Large R D I D Q Q 2 I d =g m v in V out V DD v out EE 303 Common Source Stage 6

Importance of choosing the right bias point Deciding the location of the bias point Q affects: gain (the values of g m and r o depend on the DC bias) allowable signal swing at the output V out V out v out Q v out Q V in V in v in v in EE 303 Common Source Stage 7

Can we overcome the upper bound on gain? The upper bound comes from the fact that both gain and bias point depend on R D A Want large R D for large gain V max 2 V DD Want small R D to prevent device from entering triode region We can overcome the upper bound, if we can find a way to set V OUT V OV min independently of R D I d Large R D Small R D I D Q V OUT V out EE 303 Common Source Stage 8

CS stage with improved drain biasing scheme I d = I B V B V out R D at the point V out =V B we have I d =I B regardless the value of R D I B R D I d Ii d D v OUT V B V out I B Q v in V IN V B V out We wish to set I B =I D and V B =V OUT EE 303 Common Source Stage 9

Plot for I B =I D I d Large R D Small R D I D Q g m i d v out V out V OUT We can increase R D (and gain) without changing operating point EE 303 Common Source Stage 0

Infinite gain? It is tempting to think we can make R D nearly infinitely large and get close to infinite gain This is not possible in practice for two reasons Finite di d /dv ds of the transistor I B vv OUT out A V = g m r o 2I D V in v IN V OV λi D = 2 λv OV Sensitivity to mismatch between I D and I B will render the circuit impractical EE 303 Common Source Stage

Bias point shift due to mismatch in I B and I D For large values of R D, it becomes harder to absorb differences between I D and I B and still maintain an operating point that is close to the desired value I d /R D I B I D Q ΔI ΔV= ΔI R D V out V B V OUT EE 303 Common Source Stage 2

Solutions to bias point shift issue Limit R D to values such that expected mismatch in bias currents causes acceptable bias point variations Feedback Somehow sense V OUT and adjust I B (or I D ) such that the outputs sits at a proper operating point regardless of mismatch between I D and I B More later In a realistic circuit implementation, the auxiliary current source I B can be built, for example, using a pmos that operates in saturation More later (CS stage with current source load) EE 303 Common Source Stage 3

How fast can the CS stage go? There are two perspectives on how fast a circuit can go Which one of the two matters more is dependent on the application Time domain Apply a transient at the input (e.g. a voltage step), measure how fast the output settles Frequency domain Apply a sinusoid at the input, measure the gain and phase of the circuit transfer function across frequency Knowing the time domain response, we can estimate the frequency domain response, and vice versa EE 303 Common Source Stage 4

Common Source Stage revisited V B I B R R D Transducer V o v i R i V I R i models finite resistance in the driving circuit EE 303 Common Source Stage 5

Matlab Design Script % % C. Talarico % filename: csdesign.m % Design of CS amplifier using gm/id methodology % clc; clear all; close all; addpath('~/gm_id_starter_kit_204'); load 80n.mat; % specs. av0 = 0; Id = 400e-6; Ri = 0e3; RD = 2e3; Vdd =.8; VB = Vdd/2; % design choice Ln = 0.8e-6 % calculations gm = av0/rd gm_id = gm/id wt = lookup(nch, 'GM_CGG', 'GM_ID', gm_id, 'L', Ln); ft = wt/2/pi cgd_cgg = lookup(nch, 'CGD_CGG', 'GM_ID', gm_id, 'L', Ln); cdd_cgg = lookup(nch, 'CDD_CGG', 'GM_ID', gm_id, 'L', Ln); cgg = gm/wt; cgd = cgd_cgg*cgg cdd = cdd_cgg*cgg; cdb = cdd - cgd cgs = cgg - cgd gmro = lookup(nch, 'GM_GDS','GM_ID', gm_id, 'L', Ln) ro = gmro/gm % finding input bias VI = lookupvgs(nch, 'GM_ID', gm_id, 'L', Ln) % device sizing id_w = lookup(nch, 'ID_W', 'GM_ID', gm_id, 'L', Ln) W = Id/id_w % neglecting ro is not a very accurate assumption R = (/RD /ro)^- Av0 = gm*r Av0db = 20*log0(gm*R) % pole calculations (dominant pole assumption) b = Ri*(cgs cgd*(av0))r*(cdbcgd); b2 = Ri*R*(cgs*cdb cgs*cgd cdb*cgd); fp = /2/pi/b fp2 = /2/pi*b/b2 % zero calculation fz = /2/pi/cgd*gm! EE 303 Common Source Stage 6

What is the speed of the CS? V B Transducer R v i i V I I B R R D V o V DD =.8 V V B = V DD /2 = 0.9 V R i = 0KΩ R D = 2 KΩ V I = 0.627 V I B = 400 µa W/L = 2.34 µm/0.8µm C gd v i R i v gs - C gs g m v gs r o R D R C db v o - C gd 0.28 ff C gs 33.26 ff C db 5.72 ff R r o 7.63KΩ R = R D r o.58kω EE 303 Common Source Stage 7

CS Frequency Response AC Response 20 H(f) [db] 0 20 phase[h(f)] [deg] 40 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 200 50 00 50 f [Hz] 0 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 f [Hz] There seems to be two poles. Let s analyze the situation in detail. EE 303 Common Source Stage 8

Exact Analytical Analysis C gd 2 v i /R i R i v gs - C gs g m v gs r o R C db v o - Applying KCL at nodes and 2, and solving for v o /v i yields vo( s ) v ( s ) i g = 2 s db gd gs gd i m i gd m C R s g m [( C C ) R ( C C ) R g R RC ] s R R( C C C C C C ) gd i gs db gd db gs gd High entropy expression. Difficult to get any insight!!! EE 303 Common Source Stage 9

Issue We could in principle use this expression to plot the frequency response of the circuit and compute the 3-dB bandwidth The result would match the Spice simulation result exactly There are two issues with going in this direction for hand analysis The procedure is quite tedious Imagine how complex the equations would get for a multitransistor circuit The derived expression is useless for reasoning about the circuit from an intuitive design perspective By looking at this equation we cannot easily tell what exactly limits the bandwidth, or how we can improve it EE 303 Common Source Stage 20

Simulation Result Want to have a method that let s us estimate the dominant pole quickly using intuitive methods Without running into high entropy expressions that tell us things we are not interested in Non-dominant, high-frequency poles and zeros may or may not be important If they are, it may be OK to do a little more work H(f) [db] 20 0 20 40 60 Dominant pole AC Response Non-dominant pole(s) and zero(s) 80 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 2 f [Hz] EE 303 Common Source Stage 2

The Culprit The main reason for the high complexity in the derived expression is that C gd couples nodes and 2 For C gd =0, the circuit becomes 2 v i /R i R i v gs - C gs τ g m v gs R C db v o - τ 2 v o (s) v i (s) = v gs(s) v i (s) v o(s) v gs (s) = sr i C gs ( ) g m R ( src db ) = g mr ( sτ )( sτ 2 ) EE 303 Common Source Stage 22

A Promising Trick: Miller Theorem Z 2 General Linear V Network V 2 - - K V 2 V 2 V - Z K General Linear Network Z K K V 2 - EE 303 Common Source Stage 23

Finding K(s) for Our Circuit C gd 2 v gs - g m v gs R C db v o - Applying KCL at node 2, and solving for v o /v gs yields: " K(s) = v (s) s C % gd $ ' o v gs (s) = g g m mr$ ' $ sr(c gd C db )' $ ' # & EE 303 Common Source Stage 24

Circuit After Applying Miller Theorem 2 v i /R i R i v gs - C gs C gd [-K(s)] g m v gs R C db C gd [-/K(s)] v o - K( s ) = v v o gs ( s ) ( s ) = g m Cgd s gm R sr( Cgd C db ) z = g m C gd p = R(C gd C db ) Intuitively, the zero is caused because at high frequency C gd shorts the gate and drain of the device together, providing a direct path from the amplifier s input to output. Hence, as frequency increases beyond w z, the circuit appears to have one less node and one less pole (with C gd acting like a short, C gs, C db, are in parallel). Because the sign of w z is negative, the zero is in the RHP and therefore causes phase lag (just like a pole) rather than phase lead. EE 303 Common Source Stage 25

Miller Approximation As long as ω << ω z = g C m gd and ω << ω p = ( C ) R C gd db It is appropriate to approximate K( s ) = v v o gs ( s ) ( s ) = g m Cgd s gm R sr( Cgd C db ) g m R Approximating the gain term K(s) with its low-frequency value K(0) is called the Miller approximation EE 303 Common Source Stage 26

Resulting Circuit Model 2 v i /R i R i v gs - C gs g m v gs C gd [g m R] R C db C gd [/g m R] v o - This circuit model suggests that there are two poles p = p R i "# C gs C gd ( g m R) $ 2 = % R"# C db C gd ( / g m R) $ % The pole p 2 lies beyond the frequency range for which this model is valid; it must be discarded ω p2 = << ω R!" C db C gd / g m R # p = $ ( ) R(C db C gd ) EE 303 Common Source Stage 27

How about p? ω p =? << ω R i!" C gs C gd g m R # p = $ ( ) R(C db C gd ) ω p =? << ω R i!" C gs C gd g m R # z = g m = g R m $ C gd ( ) RC gd Whether or not these inequalities hold depends on the parameter values of the specific circuit in question In our example, we have R i =0kΩ > R=2kΩ, g m R 7.92, C gs > C db, C gd Conditions are met!! EE 303 Common Source Stage 28

Model for Dominant Pole Calculation 2 v i /R i R i v gs - C gs C gd [g m R] g m v gs R v o - Using calculated values from MATLAB script f 3dB = 2π R i [C gs C gd ( g m R)] = 2π 0kΩ[33.26 ff 0.28 ff( 7.92)] =27.37MHz Simulation result was 24.56 MHz; very good match!! (less than 3% discrepancy) EE 303 Common Source Stage 29

Conclusions The Miller approximation is a great tool that allows us to calculate the bandwidth of our CS circuit example on the back of an envelope An important caveat is that the Miller approximation is only useful as long as the dominant time constant is with the input network of the circuit (node ) Usually the case when R i is large, and there is no large capacitance attached to v o For calculations, you will typically start by assuming that this condition is met, and later check and make sure that the obtained dominant pole frequency lies indeed far below the pole(s) and zero(s) of K(s) With a little bit of experience you will be able to do this by inspection Very important The Miller approximation allows quick calculation of the dominant pole frequency only It is unsuitable for estimating the non-dominant pole frequency EE 303 Common Source Stage 30

Dominant Pole Approximation: ZVTC Analysis Motivation: we saw that the Miller approximation is a very useful tool that allows us to estimate the -3dB bandwidth of our CS stage quickly and intuitively Wouldn t it be nice to have a similar technique that works for a broader class of circuits? The zero-value time constant (ZVTC) method is a tool that meets this demand We will continue to use the CS amplifier to illustrate this method, along with its mathematical underpinnings EE 303 Common Source Stage 3

Analysis Revisited () C gd 2 v i /R i R i v gs - C gs g m v gs R C db v o - vo( s ) = v ( s ) s i = a v0 m 2 [( C C ) R ( C C ) R g R RC ] s R R( C C C C C C ) db s z b s b s gd 2 2 gs gd g i m C R s g m i gd gd i gs db gd db gs gd EE 303 Common Source Stage 32

Analysis Revisited (2) We know that The transfer function of our circuit has a dominant pole that sets the -3dB bandwidth The non-dominant pole and zero have little influence on the -3dB bandwidth of the circuit Can we somehow use this fact to simplify the analysis? Without circuit-specific tricks like the Miller approximation H(f) [db] 20 0 20 40 60 Dominant pole AC Response Non-dominant pole(s) and zero(s) 80 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 2 f [Hz] EE 303 Common Source Stage 33

EE 303 Common Source Stage 34 Dominant Pole Approximation () If our goal is to estimate the -3dB frequency only, we can discard the zero and write 2 2 0 2 2 0 s b b s a s b b s z s a s ) ( v s ) ( v v v i o = 2 2 0 2 2 2 0 2 0 p p s p s a p p s p s p s a p s p s a s ) ( v s ) ( v v v v i o = Next, use the fact that p 2 >> p, where p 2 is the non-dominant pole and p is the dominant pole that sets the -3dB frequency

EE 303 Common Source Stage 35 Dominant Pole Approximation (2) We can now compare to the original expression to find This means that in order to estimate the -3dB bandwidth of the circuit, all we need to know is b! 2 2 2 2 2 0 2 2 0 p p b b p b b s b b s a p p s p s a s ) ( v s ) ( v v v i o = 3 0 b p ω p s a s ) ( v s ) ( v db - v i o

b in Our Circuit vo( s ) v ( s ) i g = 2 s db gd gs gd i m i gd m C R s g m [( C C ) R ( C C ) R g R RC ] s R R( C C C C C C ) gd i gs db gd db gs gd ( Cdb Cgd ) R ( Cgs Cgd ) Ri gmri RCgd = RCdb RCgd RiC gs ( gmr) RiC gd b = Plug in numbers for our example to see if this works Looks familiar? b =.58kΩ 5.72 ff.58kω 0.28 ff 0kΩ 33.26 ff ( 7.92)0kΩ 0.28 ff = 24.84ps 6.24ps 332.60 ps 96.98ps =290.7ps f 3dB = 2π 290.66ps =23.37MHz Very good match! (Spice: 24.56 MHz, Miller: 27.37 MHz) EE 303 Common Source Stage 36

Zero-Value Time Constant Analysis A step-by-step circuit analysis method that allows us to determine b (and only b ) without solving for the complete transfer function! Here's how it works Remove all but one capacitor (C j ) Short independent voltage sources Remove independent current sources Calculate resistance seen by capacitor (R j ) and compute t j =R j C j Repeat above steps for all remaining capacitors in the circuit The sum of all t j is equal to b b = τ j ω 3dB b = τ j EE 303 Common Source Stage 37

Example () C gd v i R i v gs - C gs g m v gs R C db v o - Step : R i R =R i g m v gs R v o - τ = R i C gs EE 303 Common Source Stage 38

Example (2) Step 2: i t v t - R i v gs - g m v gs R A little more tricky, but any linear circuit method will do (e.g. apply test current (i t ), write expression for v t, find R=v t /i t R 2 = v t i t = v gs R(g m v gs i t ) i t = i t R i R(g m i t R i i t ) i t τ 2 = ( R R g i v gs = R i i t m RR i ) C gd = R i R g m RR i sum product x g m EE 303 Common Source Stage 39

Example (3) Step 3: R = R 3 τ 3 = RC db Step 4: Add up all time constants τ j = τ τ2 τ3 = i gs ( R Ri gmrri ) Cgd RCdb R C Step 5: Compute estimate of -3dB frequency ω 3dB τ j Exactly the same result we found on slide 37 EE 303 Common Source Stage 40

Important Notes on ZVTC () The key advantages of this method are It provides an excellent shortcut for finding the -3dB frequency of a circuit In addition, the method provides us with insight about the limiting time constants in our circuit! Whenever you apply the ZVTC method, it is important to remember the assumptions for which it is accurate The circuit has a dominant pole The circuit does not have any zeros in the vicinity of its -3dB frequency The time constants computed in the ZVTC method do not correspond to poles! Remember that the sum of the time constants is equal to b EE 303 Common Source Stage 4

Important Notes on ZVTC (2) When the underlying assumptions are not precisely met, it may still be OK to work with ZVTC Provided that you clearly understand what you are doing Example : AC coupling caps or bypass caps Meant to be shorts at high frequencies, and do not degrade the signal bandwidth Typically OK to discard these caps to find the upper corner frequency of the circuit Example 2: Multiple poles of similar (or same) magnitude See next page EE 303 Common Source Stage 42

Two-Pole Example () R v i v x C g m v x R C - - v o Exact calculation of -3dB frequency vo( s ) = v ( s ) i 2 = ω g m R ( src) 2 3dB R 2 2 C 2 We do not have a dominant pole!! ω 3dB 0. 64 = 2 = RC RC EE 303 Common Source Stage 43

Two-Pole Example (2) R v i v x C g m v x R C - - v o ZVTC method ω τ RC RC 3 db = = 0. 5 RC 0. 5 0. 64 Error = = 22% 0. 64 ZVTC bandwidth estimates tend to be conservative Actual bandwidth is almost always at least as high as estimate EE 303 Common Source Stage 44

Useful Expressions R gd R D R gs = R G R S g m R S R G R gs R S R ds R ds = r 0 R D R S g m R S R gd = R G R D G m R G R D g m G m = g m R S EE 303 Common Source Stage 45

Hspice Deck * Common source amplifier * filename: commonsource.sp * C. Talarico, Fall 204 *** device model.include../ece696008.mod *** useful options.option post brief nomod accurate *** netlist vdd vdd 0.8 vb vb 0 0.9 ib vdd vo 400u vi vi 0 dc 0.627 ac mn vo vg 0 0 nmos w=2.34u l=0.8u RD vb vo 2k Ri vi vg 0K *** analysis.op.ac dec 0 00 T.pz v(vo) vi *** measurements.measure AC av0 find V(vo) at K.measure AC av0db find vdb(vo) at K.measure AC f3db when Vdb(vo)='av0db - 3'.end! EE 303 Common Source Stage 46

Plotting Hspice Results in Matlab % % cs_plot.m % clear all; close all; format short eng addpath('/usr/local/matlab/personal/hspicetoolbox'); y = loadsig('./commonsource.ac0'); lssig(y) figure(); subplot(2,,); freq = evalsig(y,'hertz'); vo = evalsig(y,'v_vo'); magdb = 20*log0(abs(vo)); phase = 80*unwrap(angle(vo))/pi; semilogx(freq, magdb,'linewidth',2, 'color', 'b', 'linestyle', '-'); grid on; ylabel(' H(f) [db]', 'Fontsize', 4); xlabel(' f [Hz]', 'Fontsize', 4); title('ac Response', 'Fontsize', 6); xmin = e4; xmax = e; xlim([xmin xmax]); ymax = 25; ymin = -40; ylim([ ymin ymax]); subplot(2,,2); semilogx(freq, phase,'linewidth',2, 'color', 'b', 'linestyle', '-'); grid on; ylabel(' phase[h(f)] [deg]', 'Fontsize', 4); xlabel(' f [Hz]', 'Fontsize', 4); xmin = e4; xmax = e; xlim([xmin xmax]); ymax = 200; ymin = 0; ylim([ ymin ymax]); avo = abs(vo()) av0db = magdb() f3db = interp(magdb, freq, magdb()-3, 'spline')! EE 303 Common Source Stage 47

Simulated DC Operating Point element 0:mn model 0:nmos region Saturati id 392.556u ibs 0. ibd 0. vgs 627.0000m vds 95.6889m vbs 0. vth 486.040m vdsat 5.878m vod 40.9860m beta 42.550m gam eff 585.064m gm 4.920m gds 27.76u gmb.709m cdtot 29.5868f cgtot 43.5028f cstot 56.0268f cbtot 49.5585f cgs 30.8630f cgd 0.2858f cdtot C gd C db cgtot C gs C gd C gb cstot C gs C sb cbtot C gb C sb C db cgs C gs cgd C gd Good Agreement! Design values: g m = 5mS c dd = 26 ff c gg = 43.53 ff c gd = 0.28 ff c gs = c gg c gd = 43.53 0.28 = 33.36 ff EE 303 Common Source Stage 48

Simulated AC Response AC Response Magnitude [db] 20 0 0 0 20 30 40 50 60 70 gain = 8 db (7.8) f 3db = 24.57 MHz % pole calculations (dominant pole assumption) b = Ri*(cgs cgd*(av0))r*(cdbcgd); b2 = Ri*R*(cgs*cdb cgs*cgd cdb*cgd); fp = /2/pi/b fp2 = /2/pi*b/b2 % zero calculation fz = /2/pi/cgd*gm! The design is essentially right on target!! Typical discrepancies are no more than 0%-20% 80 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 2 Frequency [Hz] ****** pole/zero analysis input = 0:vi output = v(vo) poles (rad/sec) poles ( hertz) real imag real imag -784.66x 0. -24.883x 0. -67.7746g 0. -0.7867g 0. zeros (rad/sec) zeros ( hertz) real imag real imag 469.7g 0. 74.6622g 0.! Calculated values: A V0 7.92 (7.98 db); fp 23.30MHz; fp2 2.37GHz; fz 77.43GHz EE 303 Common Source Stage 49

Matlab Script to plot the Simulation Results % % cs_cuteplot.m % clear all; close all; format short eng addpath('/usr/local/matlab/personal/hspicetoolbox'); y = loadsig('./commonsource.ac0'); lssig(y) figure(); freq = evalsig(y,'hertz'); vo = evalsig(y,'v_vo'); magdb = 20*log0(abs(vo)); phase = 80*unwrap(angle(vo))/pi; semilogx(freq, magdb,'linewidth',2, 'color', 'b', 'linestyle', '-'); grid on; ylabel(' Magnitude [db]', 'Fontsize', 6); xlabel(' Frequency [Hz]', 'Fontsize', 6); xmin = e4; xmax = e2; xlim([xmin xmax]); av0 = abs(vo()) av0db = magdb() f3db = interp(magdb, freq, magdb()-3, 'spline') % Annotate title str = sprintf('ac Response\n'); str2 = sprintf(' gain = %0.2g db (%0.2g) - f_{3db} = %3.2f MHz', av0db, av0, f3db*e-6); str = {str, str2}; title(str, 'fontsize', 6); EE 303 Common Source Stage 50

Practical Design Considerations () If the load capacitance is modest and the source resistance is high, the Miller effect is likely to be the major limitation in the amplifier BW BW can be improved by sizing the transistor as small as possible. For a fixed current this implies that the device will exhibit a relatively large V OV. This has two drawbacks: To keep the transistor in saturation we need a higher DC voltage drop across the transistor (reduced headroom) Mobility degradation If the load capacitance is large and the source resistance is low, the output time constant will dominate and become the major limitation in the amplifier BW Large device width and small values of V OV are preferred (having the device operating near sub threshold gives the best gain-bw tradeoff) For low-gain, high frequency, it may be desirable to use resistor loads (if they do not require much silicon area) because they have less parasitic capacitances associated with them. EE 303 Common Source Stage 5

CS summary The CS stage is a decent (voltage controlled) current source ( decent trans-conductance amplifier) The CS stage can be used to realize a basic voltage amplifier, but it makes a good voltage amplifier only when terminated with a high impedance R in = (very high) R out = r o (moderately high) R in C gd 2 R out v i /R i R i v gs - C gs g m v gs r o R C db v o - D EE 303 Common Source Stage 52

More CS stage variations CS with Current-Source Load (practical implementation) CS with Diode-Connected Load ( ratiometric CS stage) CS with Degeneration EE 303 Common Source Stage 53

CS with Current-Source Load Realistic implementation of the CS basic stage with improved drain biasing scheme Use a pmos operating in saturation as load I B i D R D v OUT V B V B Source: Razavi v in V IN A V = g m (r o r o2 ) R in = R out = r o r o 2 EE 303 Common Source Stage 54

Design Considerations The upper side of the output signal swing V DD V DS2min = V DD ( V GS2 V T2 ) can be improved by increasing the width of M 2 If r o2 is not sufficiently large (for the desired gain), the length of M 2 can be increased. Increasing L 2 while keeping W 2 constant increases r o2 and hence the voltage gain, but at the cost of a higher V DS2 required to maintain M 2 in saturation. To maintain the same overdrive voltage both W and L must be increased. The penalty is the large capacitance (C gs2 C db2 ) introduced by M 2 at the output node V OV = 2 µc ox I D! L $ # & " W % The intrinsic gain of M can be increased by increasing L. Since r o is proportional to L/I D the intrinsic gain increases because λ depends more strongly on L than g m does:! W $ g m r o = 2µC ox # & " L % However, if W is not increased proportionally, the overdrive voltage V GS -V T increases, limiting the lower side (V DSmin ) of the output signal swing I D λi D NOTE: g m r o decreases as I D increases EE 303 Common Source Stage 55

Issue The output bias voltage V OUT of the circuit is not well defined. The stage is reliably biased only if a feedback loop forces V OUT to a known value. To be continued Since the current through the two MOS must stay the same, even a small error will cause a large shift of the bias voltage V OUT and push one of the transistor away from saturation 350 300 pmos pmos ( 0% bias error) nmos 250 I out [µa] 200 50 00 50 0 0 0.2 0.4 0.6 0.8.2.4.6.8 V out [V] EE 303 Common Source Stage 56

CS with current source load - Example () V DD =.8V; I D =50µA; V OUT =0.8V L = 0.8µm % % C. Talarico % filename: cscs_design.m % Design bias for CS with current source load % clc; clear all; close all; addpath('~/gm_id_starter_kit_204'); V GS = 0.68 V g m =.5 ms W = 4.94µm r o = 23.23 KΩ A V = 9.57 V GS2 = 0. 84 V g m2 = 0.76 ms W 2 = 4.94µm r o2 = 28.90 KΩ % The NMOS load 80n.mat; Ln = 0.8e-6 Vds = 0.8 Ibias = 50e-6 for Vgs=0.5:0.0:0.9 Id = lookup(nch, 'ID', 'VGS', Vgs, 'VDS', Vds, 'L', Ln); if (Id >= Ibias) Id Vgs=Vgs break end end gm = lookup(nch, 'GM', 'VGS', Vgs, 'VDS', Vds, 'L', Ln) gm_id = gm/id id_w = lookup(nch, 'ID_W', 'GM_ID', gm_id, 'L', Ln) W = Id/id_w gmro = lookup(nch, 'GM_GDS','GM_ID', gm_id, 'L', Ln) ro = gmro/gm % The PMOS load 80p.mat Ln = 0.8e-6 Vds = 0.8 Ibias = 50e-6 for Vgs=0.5:0.0:.2 Id = lookup(pch, 'ID', 'VGS', Vgs, 'VDS', Vds, 'L', Ln); if (Id >= Ibias) Id Vgs2=Vgs break end end gm2 = lookup(pch, 'GM', 'VGS', Vgs, 'VDS', Vds, 'L', Ln) gm_id = gm2/id id_w = lookup(pch, 'ID_W', 'GM_ID', gm_id, 'L', Ln) W2 = Id/id_w gmro2 = lookup(pch, 'GM_GDS','GM_ID', gm_id, 'L', Ln) ro2 = gmro2/gm2 AV = gm/(/ro/ro2) EE 303 Common Source Stage 57

CS with current source load - Example (2) * cs with current source load * filename: cscs.sp * C. Talarico, Fall 204 *** device model.include../ece696008.mod *** useful options.option post brief nomod.param supply =.8 *** circuit vdd vdd 0 'supply' vi vi 0 dc 0.68 ac vb vb 0 0.96 m vo vg 0 0 nmos w=4.94u l=0.8u m2 vo vb vdd vdd pmos w=4.94u l=0.8u Ri vi vg 0K *** analysis and measurements.op.ac dec 0 00 T.measure AC av0 find V(vo) at K.measure AC av0db find vdb(vo) at K.measure AC f3db when Vdb(vo)='av0db - 3'.alter amplifier with error * -0% error vb vb 0 '0.9*0.96'.end element 0:m 0:m2 model 0:nmos 0:pmos region Saturati Saturati id 60.5067u -60.5067u ibs 0. 0. ibd 0. 0. vgs 680.0000m -840.0000m vds 86.2602m -983.7398m vbs 0. 0. vth 485.7988m -498.706m vdsat 44.4580m -277.348m vod 94.202m -34.8294m beta 9.9652m 2.7793m gam eff 583.78m 53.420m gm.5079m 800.3570u gds 43.5979u 33.7757u gmb 355.684u 247.3357u cdtot 7.77f 7.6254f cgtot 0.9f 0.7026f cstot 3.2586f 3.4306f cbtot.9484f.4786f cgs 7.2275f 7.357f cgd 2.3756f 3.800f av0= 9.489 av0db= 25.7959 f3db= 27.4707x element 0:m 0:m2 model 0:nmos 0:pmos region Saturati Linear id 90.548u -90.548u ibs 0. 0. ibd 0. 0. vgs 680.0000m -936.0000m vds.5059-294.0804m vbs 0. 0. vth 479.7683m -507.9848m vdsat 47.790m -337.772m vod 200.237m -428.052m beta 9.9623m 2.7282m gam eff 583.78m 53.420m gm.6650m 676.2354u gds 43.9788u 236.737u gmb 388.550u 222.497u cdtot 6.77f 8.8003f cgtot 0.208f 0.7526f cstot 3.2634f 3.476f cbtot.5480f 2.3472f cgs 7.234f 7.3253f cgd 2.3750f 3.2680f av0= 5.93 av0db= 5.4628 f3db= 568.4082x -0% error on V B!! EE 303 Common Source Stage 58

CS with current source load - Signal swing 5.5 M off; M 2 triode 5 4.5 CS with current source load: DC Response um Technology M sat M 2 triode V out (max) = V B V T2 4 3.5 V out [V] 3 2.5 2 M sat M 2 sat V DD =5V V B = 3.2350V W /L = 0mm/mm W 2 /L 2 = 20mm/mm V out (min) = V in -V T.5 0.5 M triode M 2 sat 0 0 0.5.5 2 2.5 3 3.5 4 4.5 5 V in [V] EE 303 Common Source Stage 59

Bulk Terminal and Backgate Effect Bulk Connection Bulk Connection Scenarios Well Capacitance (PMOS) Backgate Effect Modified small signal model EE 303 Common Source Stage 60

Bulk Connection *Be aware: Ask the technology folks Know what it means! In our technology (N-well), only the PMOS device has an isolated bulk connection Newer technologies* (e.g. 0.3mm CMOS) also tend to have NMOS devices with isolated bulk ("tripple-well" process) EE 303 Common Source Stage 6

Aside: Modern Triple-Well Process n p p Courtesy Shoichi Masui EE 303 Common Source Stage 62

Bulk Connection Scenarios NMOS V DD PMOS Can connect bulk to source or V DD EE 303 Common Source Stage 63

Well Capacitance (PMOS) NMOS PMOS EE 303 Common Source Stage 64

Example 0.8um 0.64um 0.64um 0/0.8 0um 0.5um 0.3um * HSpice Netlist.model dwell d cj0=2e-4 is=e-5 m=0.5 Area = um x 3.4um = 37.4um 2 * d g s b mp 0 in out out pmos L=0.8um W=0um * a k area d 0 out dwell 37.4p EE 303 Common Source Stage 65

Backgate Effect () V GS - I D - V DS V SB - Depletion layer for V SB = 0 n n Depletion layer for V SB > 0 With positive V SB, depletion region around source grows Increasing amount of negative fixed charge in depletion region tends to "repel" electrons coming from source Need larger V GS to compensate for this effect (i.e. Vt increases) EE 303 Common Source Stage 66

Backgate Effect (2) This effect is usually factored in as an effective increase in V t Detailed analysis shows V t = V t 0 γ ( 2φ f V SB 2φ ) f A change in V t also means a change in drain current Define small-signal backgate transconductance g mb = I V D BS I = V D SB g g mb m V = V t SB I V D t V I GS D = V V t SB = 2 V 2φ SB γ f - EE 303 Common Source Stage 67

MOS Level Equations (Saturation) I DS = KP 2 W ( V GS V t ) 2 ( λv DS ) L eff V t = V TO γ ( 2φ f V SB 2φ ) f ' KP µc OX GAMMA γ = 2φ f = 2kT q ln N bulk n i 2ε SqN bulk ' C OX SPICE Parameter Names: VTO TOX KP LAMBDA (λ) GAMMA (ϒ) PHI (2Φ f ) ' C OX = ε OX t OX L eff = L mask 2X J lateral EE 303 Common Source Stage 68

Modified Small Signal Model C gd New term G D S B v gs - - v bs C gb C sb C gs g m v gs C db g mb v bs r o C bsub (only for PMOS in n-well) SUB EE 303 Common Source Stage 69

CS with Diode-Connected Load Source: Razavi " A V = g m $ r o # R in = R out = r o g m2 g m2b r o2 r o2 g' m2 g' m2 g m2 % ' & g m g m2 g m2b = g m g m2 with g' m2 = g m2 g m2b η η = g m2b g m2 A V g m g m2 η = $ W ' 2µC ox & ) % L ( $ W ' 2µC ox & ) % L ( 2 I D I D η = $ & % $ & % W L W L ' ) ( ' ) ( 2 η As long as M stay in saturation (M 2 is diode connected so as long as is ON, it is always in saturation) the gain is not affected by fluctuations of the bias current and bias voltages The gain is ratiometric The input-output characteristic is relatively linear EE 303 Common Source Stage 70

Design Considerations () High gain requires a strong input device (M ) and a weak load device (M 2 ) Issues: For high gain we need: very wide M (large input capacitance) or very long M 2 (large load capacitance) For high gain, the allowable voltage swing is significantly limited A V (W / L) (W / L) 2 = V GS2 V T2 V GS V T EE 303 Common Source Stage 7

Design Considerations (2) For square law devices, the output signal swing can be predicted analytically V out (max) = V DD V T 2 V out (min) = V DD V T 2 V DD V T β 2 / β NOTE: This clearly shows why for high gain (β 2 small, β large) the negative signal swing gets significantly limited Equate the equation of I D for M (edge triode region) and the equation of I D for M 2 (saturation) and solve for V out The stage is relatively linear even for large signals 2 µc OX! # " W L $ & % (V in V T ) 2 = 2 µc! W OX # " L $ & % 2 (V DD V out V T 2 ) 2! # " W L $ & % (V in V T ) =! # " W L $ & % 2 (V DD V out V T 2 ) NOTE: The eq. of V out vs. V in is a straight line EE 303 Common Source Stage 72

CS with diode connected load: I/O DC sweep () For M in cut off (V in < V T ), the output voltage settle to V out = V DD V T V out Digital folks like to say: NMOS pass a degraded VDD C P For V in > V T the device M enters saturation and V out follows an approximately straight line V out V in (W / L) (W / L) 2 As V in exceeds V out V T (beyond point A), M enters triode region, and the characteristics becomes non linear EE 303 Common Source Stage 73

CS with diode connected load: I/O DC sweep (2) CS with diode connected load: DC Response um Technology A Vmax = 3.05 5 V out (max)=v DD -V T 4.5 4 3.5 M cut-off V out [V] 3 2.5 2 M saturation V out (min)=v in -V T.5 0.5 A M triode 0 0 0.5.5 2 2.5 3 3.5 4 4.5 5 V in [V] W /L = 200µm/µm; W 2 /L 2 = 20µm/µm; A V 0 3.6 EE 303 Common Source Stage 74

Hspice Deck * CS with diode connected load * filename: csdiode.sp * C. Talarico, Fall 204 *** device model.model simple_nmos nmos kp=50u vto=0.5 lambda=0. cox=2.3e-3 capop=2 cgdo=0.5n cgso=0.5n cj=0.m cjsw=0.5n pb=0.95 mj=0.5 mjsw=0.95 acm=3 cjgate=0 hdif=.5u gamma=0.6 PHI=0.8 *** useful options.option post brief nomod accurate *** long_channel device vdd vdd 0 5 * load device mn2 vdd vdd vo 0 simple_nmos w=20u l=u * amplifing device mn vo vi 0 0 simple_nmos w=200u l=u vi vi 0 dc ac *** large signal analysis (sweep Vi).OP.dc vi 0 5 0.0.end! EE 303 Common Source Stage 75

Matlab Script % % csdiode_plot.m % clear all; close all; format short eng addpath('/usr/local/matlab/personal/hspicetoolbox'); x = loadsig('./csdiode.sw0'); lssig(x) figure(); vo = evalsig(x,'v_vo'); vi = evalsig(x,'v_vi'); vth = 0.5; plot(vi, vo,'linewidth',2, 'color', 'b', 'linestyle', '-'); grid on; ylabel(' V_{out} [V]', 'Fontsize', 6); xlabel(' V_{in} [V]', 'Fontsize', 6); xmin = 0; xmax = 5; xlim([xmin xmax]); ymax = 5; ymin = 0; ylim([ ymin ymax]); % compute when M enters triode region for i=:length(vi) if vo(i)vth-vi(i) < 0 index = i; break end end % horizontal line at Vi for which M enter triode pointa = vo(index-); % take index- for margin line([min(vi) vi(index)], [pointa pointa], 'linestyle', '--',... 'linewidth', 2, 'color', 'r'); % compute gain h = 0.0; Y = diff(vo)/h; AV = min(y) % gain is negative str = sprintf('cs with diode connected load: DC Response - um Technology'); str2 = sprintf(' A_{Vmax} = %0.2f', abs(av)); str = {str, str2}; EE 303 Common Source Stage 76

Diode connected load vs. resistive load Advantages Ratiometric Gain depends on ratio of similar parameters Effect of process and temperature variations is reduced First order cancellation of nonlinearities Disadvantage Reduced swing EE 303 Common Source Stage 77

Improving the CS with Diode-Connected Load Source: Razavi = 0.75 I Add a current source across the diode connected load Since I D2 = I /4 we have: A V g m g m2 = 4µ n (W / L) µ p (W / L) 2 = 4 V GS2 V T 2 V GS V T For a given overdrive voltage this circuit achieves a gain 4x that of the original stage. Alternatively, for a given gain, we need b /b 2 4x smaller, so this helps in terms of swing. (For a gain of 0, the overdrive of M 2 needs to be only 2.5 x that of M instead of 0 x like in the original circuit). EE 303 Common Source Stage 78

CS with Source Degeneration Examining the effect of source degeneration is important because it is widely used to increase the output resistance of MOS current sources However, source degeneration in MOS transistors amplifiers in not widely used (as emitter degeneration in bipolar transistors) The g m of MOS transistors is much lower than that of bipolar transistors, so a further reduction in the effective transconductance G m is usually not desirable Although degeneration increases the input resistance in the bipolar case, in the MOS case Ri even without degeneration This is a local series FB more later EE 303 Common Source Stage 79

Effective transconductance of CS with degeneration G m = i o v i = g m g' m R S R S r o g m g' m R S Super-MOS r o >> R s Not necessarily true!! Think of the case where R S is obtained via another transistor. EE 303 Common Source Stage 80

Output Resistance of CS with degeneration R o = v t = R S r o [ g' m R S ] r o [ g' m R S ] i t EE 303 Common Source Stage 8

Gain of CS with degeneration () A V = G m (R o R D ) G m R D g mr D g' m R S For R S >> /g m (and g m g m ) A V R D R S The degeneration soften (i.e., it linearizes) the drain current I D dependency on V in. A fraction of V in appears across R S rather than as gate-source overdrive, thus leading to a smoother variation of I D The linearization is obtained at the cost of lower gain and higher noise (more on noise later ) EE 303 Common Source Stage 82

Gain of CS with degeneration (2).8 DC Transfer Function.6.4.2 V out [V] 0.8 0.6 0.4 CS w/o degeneration CS with degeneration 0.2 0 0 0.2 0.4 0.6 0.8.2.4.6.8 V in [V] V DD =.8V; R D =2KΩ; R S =KΩ; W/L=2.34µm/0.8µm EE 303 Common Source Stage 83

BW of CS with Degeneration f 3db (CS with degeneration) f 3dB (CS w/o degeneration) ( g m R S ) Why? we need to know more about FB. To be continued EE 303 Common Source Stage 84

Summary of CS with degeneration The source degeneration introduces series negative FB Compared to the basic CS stage Gain is reduced by a factor g m R S R S controls the magnitude of the signal v gs. It ensures that v gs does not become too large and causes unacceptably high non linear distortion. Input Resistance is increased by a factor g m R S (but since R in this is not a big deal) Output Resistance is increased by a factor g m R S BW is increased by a factor g m R S EE 303 Common Source Stage 85