Methods of Analysis and Selected Topics (dc)

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Methods of Anlysis nd Selected Topics (dc) 8 Ojectives Become fmilir with the terminl chrcteristics of current source nd how to solve for the voltges nd currents of network using current sources nd/or current sources nd voltge sources. Be le to pply rnch-current nlysis nd mesh nlysis to find the currents of network with one or more independent pths. Be le to pply nodl nlysis to find ll the terminl voltges of ny series-prllel network with one or more independent sources. Become fmilir with ridge network configurtions nd how to perform Y or Y conversions. 8.1 INTRODUCTION The circuits descried in previous chpters hd only one source or two or more sources in series or prllel. The step-y-step procedures outlined in those chpters cn e pplied only if the sources re in series or prllel. There will e n interction of sources tht will not permit the reduction techniques used to find quntities such s the totl resistnce nd the source current. For such situtions, methods of nlysis hve een developed tht llow us to pproch, in systemtic mnner, networks with ny numer of sources in ny rrngement. To our enefit, the methods to e introduced cn lso e pplied to networks with only one source or to networks in which sources re in series or prllel. The methods to e introduced in this chpter include rnch-current nlysis, mesh nlysis, nd nodl nlysis. Ech cn e pplied to the sme network, lthough usully one is more pproprite thn the other. The est method cnnot e defined y strict set of rules ut cn e determined only fter developing n understnding of the reltive dvntges of ech. Before considering the first of the methods, we will exmine current sources in detil ecuse they pper throughout the nlyses to follow. The chpter concludes with n investigtion of complex network clled the ridge configurtion, followed y the use of -Y nd Y- conversions to nlyze such configurtions. 8.2 CURRENT SOURCES In previous chpters, the voltge source ws the only source ppering in the circuit nlysis. This ws primrily ecuse voltge sources such s the ttery nd supply re the most common in our dily lives nd in the lortory environment. We now turn our ttention to second type of source clled the current source which ppers throughout the nlyses in this chpter. Although current sources re ville s lortory supplies (introduced in Chpter 2), they pper extensively in the modeling of electronic devices such s the trnsistor. Their chrcteristics nd their impct on the currents nd voltges of network must therefore e clerly understood if electronic systems re to e properly investigted.

284 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) I I I V s V s () () I R = I I R V network = V s FIG. 8.1 Introducing the current source symol. The current source is often descried s the dul of the voltge source. Just s ttery provides fixed voltge to network, current source estlishes fixed current in the rnch where it is locted. Further, the current through ttery is function of the network to which it is pplied, just s the voltge cross current source is function of the connected network. The term dul is pplied to ny two elements in which the trits of one vrile cn e interchnged with the trits of nother. This is certinly true for the current nd voltge of the two types of sources. The symol for current source ppers in Fig. 8.1(). The rrow indictes the direction in which it is supplying current to the rnch where it is locted. The result is current equl to the source current through the series resistor. In Fig. 8.1(), we find tht the voltge cross current source is determined y the polrity of the voltge drop cused y the current source. For single-source networks, it lwys hs the polrity of Fig. 8.1(), ut for multisource networks it cn hve either polrity. In generl, therefore, current source determines the direction nd mgnitude of the current in the rnch where it is locted. Furthermore, the mgnitude nd the polrity of the voltge cross current source re ech function of the network to which the voltge is pplied. A few exmples will demonstrte the similrities etween solving for the source current of voltge source nd the terminl voltge of current source. All the rules nd lws developed in the previous chpter still pply, so we just hve to rememer wht we re looking for nd properly understnd the chrcteristics of ech source. The simplest possile configurtion with current source ppers in Exmple 8.1. V s I = 10 ma I V s I 1 20 k V 1 FIG. 8.2 Circuit for Exmple 8.1. 7A E I 1 I 2 2 V FIG. 8.3 Network for Exmple 8.2. EXAMPLE 8.1 Find the source voltge, the voltge V 1, nd current I 1 for the circuit in Fig. 8.2. Solution: Since the current source estlishes the current in the rnch in which it is locted, the current I 1 must equl I, nd I 1 I 10 ma The voltge cross is then determined y Ohm s lw: V 1 I 1 (10 ma)(20 ) 200 V Since resistor nd the current source re in prllel, the voltge cross ech must e the sme, nd V s V 1 200 V with the polrity shown. EXAMPLE 8.2 Find the voltge V s nd currents I 1 nd I 2 for the network in Fig. 8.3. Solution: This is n interesting prolem ecuse it hs oth current source nd voltge source. For ech source, the dependent ( function

SOURCE CONVERSIONS 285 of something else) vrile will e determined. Tht is, for the current source, V s must e determined, nd for the voltge source, I s must e determined. Since the current source nd voltge source re in prllel, V s E 12 V Further, since the voltge source nd resistor R re in prllel, V R E 12 V nd I V 2 V R 3 A The current I 1 of the voltge source cn then e determined y pplying Kirchhoff s current lw t the top of the network s follows: nd I i I o I I 1 I 2 I 1 I I 7 A 3 A 4 A EXAMPLE 8.3 Determine the current I 1 nd the voltge V s for the network in Fig. 8.4. Solution: First note tht the current in the rnch with the current source must e 6 A, no mtter wht the mgnitude of the voltge source to the right. In other words, the currents of the network re defined y I,, nd. However, the voltge cross the current source is directly ffected y the mgnitude nd polrity of the pplied source. Using the current divider rule: V s I 6A I 1 V 1 1 20 V I 1 I 11 216 A2 1 1 16 A 2 A 3 The voltge V 1 : V 1 I 1 (2 A)() 4 V Applying Kirchhoff s voltge rule to determine V s : V s V 1 20 V 0 nd V s V 1 20 V 4 V 20 V 24 V In prticulr, note the polrity of the voltge V s s determined y the network. FIG. 8.4 Exmple 8.3. 8.3 SOURCE CONVERSIONS The current source ppering is the previous section is clled n idel source due to the sence of ny internl resistnce. In relity, ll sources whether they re voltge sources or current sources hve some internl resistnce in the reltive positions shown in Fig. 8.5. For the voltge source, if R s 0, or if it is so smll compred to ny series resistors tht it cn e ignored, then we hve n idel voltge source for ll prcticl purposes. For the current source, since the resistor R P is in prllel, if R P, or if it is lrge enough compred to ny prllel resistive elements tht it cn e ignored, then we hve n idel current source. Unfortuntely, however, idel sources cnnot e converted from one type to nother. Tht is, voltge source cnnot e converted to current R I L I L I R p R L E () () FIG. 8.5 Prcticl sources: () voltge; () current.

286 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) source, nd vice vers the internl resistnce must e present. If the voltge source in Fig. 8.5() is to e equivlent to the source in Fig. 8.5(), ny lod connected to the sources such s R L should receive the sme current, voltge, nd power from ech configurtion. In other words, if the source were enclosed in continer, the lod R L would not know which source it ws connected to. This type of equivlence is estlished using the equtions ppering in Fig. 8.6. First note tht the resistnce is the sme in ech configurtion nice dvntge. For the voltge source equivlent, the voltge is determined y simple ppliction of Ohm s lw to the current source: E IR P. For the current source equivlent, the current is gin determined y pplying Ohm s lw to the voltge source: I E/R s. At first glnce, it ll seems too simple, ut Exmple 8.4 verifies the results. R s = R p I = E R s E = IR p R p = R s FIG. 8.6 Source conversion. It is importnt to relize, however, tht R s E 6 V I L FIG. 8.7 Prcticl voltge source nd lod for Exmple 8.4. 3 A I = E = 3 A R p R L R s FIG. 8.8 Equivlent current source nd lod for the voltge source in Fig. 8.7. R L I L the equivlence etween current source nd voltge source exists only t their externl terminls. The internl chrcteristics of ech re quite different. EXAMPLE 8.4 For the circuit in Fig. 8.7:. Determine the current I L.. Convert the voltge source to current source. c. Using the resulting current source of prt (), clculte the current through the lod resistor, nd compre your nswer to the result of prt (). Solutions:. Applying Ohm s lw: I L. Using Ohm s lw gin: E 6 V R s R L 6 V 1 A I E R s 6 V 3 A nd the equivlent source ppers in Fig. 8.8 with the lod repplied.

CURRENT SOURCES IN PARALLEL 287 c. Using the current divider rule: I L R pi 1213 A2 R p R L 1 13 A 1 A 3 We find tht the current I L is the sme for the voltge source s it ws for the equivlent current source the sources re therefore equivlent. As demonstrted in Fig. 8.5 nd in Exmple 8.4, note tht source nd its equivlent will estlish current in the sme direction through the pplied lod. In Exmple 8.4, note tht oth sources pressure or estlish current up through the circuit to estlish the sme direction for the lod current I L nd the sme polrity for the voltge V L. EXAMPLE 8.5 Determine current I 2 for the network in Fig. 8.9. Solution: Although it my pper tht the network cnnot e solved using methods introduced thus fr, one source conversion, s shown in Fig. 8.10, results in simple series circuit. It does not mke sense to convert the voltge source to current source ecuse you would lose the current I 2 in the redrwn network. Note the polrity for the equivlent voltge source s determined y the current source. For the source conversion: E 1 I 1 (4 A)(3 ) 12 V nd I E 1 E 2 12 V 5 V 17 V 3.4 A 3 5 8.4 CURRENT SOURCES IN PARALLEL We found tht voltge sources of different terminl voltges cnnot e plced in prllel ecuse of violtion of Kirchhoff s voltge lw. Similrly, current sources of different vlues cnnot e plced in series due to violtion of Kirchhoff s current lw. However, current sources cn e plced in prllel just s voltge sources cn e plced in series. In generl, two or more current sources in prllel cn e replced y single current source hving mgnitude determined y the difference of the sum of the currents in one direction nd the sum in the opposite direction. The new prllel internl resistnce is the totl resistnce of the resulting prllel resistive elements. Consider the following exmples. I 1 4 A 3 5 V E 2 FIG. 8.9 Two-source network for Exmple 8.5. E 1 3 12 V 5 V E 2 I 2 FIG. 8.10 Network in Fig. 8.9 following the conversion of the current source to voltge source. I 2

288 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) EXAMPLE 8.6 Reduce the prllel current sources in Fig. 8.11 to single current source. 6 A 3 10 A I s 4 A R p FIG. 8.11 Prllel current sources for Exmple 8.6. FIG. 8.12 Reduced equivlent for the configurtion of Fig. 8.11. 7 A 3 A 4 A Solution: The net source current is I 10 A 6 A 4 A with the direction of the lrger. The net internl resistnce is the prllel comintion of resistors, nd : R p 3 00 The reduced equivlent ppers in Fig. 8.12. FIG. 8.13 Prllel current sources for Exmple 8.7. I s 8 A R p FIG. 8.14 Reduced equivlent for Fig. 8.13. EXAMPLE 8.7 Reduce the prllel current sources in Fig. 8.13 to single current source. Solution: The net current is I 7 A 4 A 3 A 8 A with the direction shown in Fig. 8.14. The net internl resistnce remins the sme. EXAMPLE 8.8 Reduce the network in Fig. 8.15 to single current source, nd clculte the current through R L. Solution: In this exmple, the voltge source will first e converted to current source s shown in Fig. 8.16. Comining current sources, I s I 1 I 4 A 6 A 10 A nd R s 00 8 00 2 I L I L I 1 4 A 8 I 2 6 A 2 R L 1 E 1 8 6 A 2 1 32 V I 2 R L I 1 = E 1 32 V = = 4 A 8 FIG. 8.15 Exmple 8.8. FIG. 8.16 Network in Fig. 8.15 following the conversion of the voltge source to current source.

BRANCH-CURRENT ANALYSIS 289 Applying the current divider rule to the resulting network in Fig. 8.17, I L R pi s 12110 A2 60 A R p R L 1 20 3 A 10 A 1 I s I s R p R L I L 8.5 CURRENT SOURCES IN SERIES The current through ny rnch of network cn e only single-vlued. For the sitution indicted t point in Fig. 8.18, we find y ppliction of Kirchhoff s current lw tht the current leving tht point is greter thn tht entering n impossile sitution. Therefore, current sources of different current rtings re not connected in series, just s voltge sources of different voltge rtings re not connected in prllel. 8.6 BRANCH-CURRENT ANALYSIS Before exmining the detils of the first importnt method of nlysis, let us exmine the network in Fig. 8.19 to e sure tht you understnd the need for these specil methods. Initilly, it my pper tht we cn use the reduce nd return pproch to work our wy ck to the source E 1 nd clculte the source current I s1. Unfortuntely, however, the series elements nd E 2 cnnot e comined ecuse they re different types of elements. A further exmintion of the network revels tht there re no two like elements tht re in series or prllel. No comintion of elements cn e performed, nd it is cler tht nother pproch must e defined. The first pproch to e introduced is clled the rnch-current method ecuse we will define nd solve for the currents of ech rnch of the network. The est wy to introduce this method nd understnd its ppliction is to follow series of steps, s listed elow. Ech step is crefully defined in the exmples to follow. FIG. 8.17 Network in Fig. 8.16 reduced to its simplest form. No! 6 A 7 A FIG. 8.18 Invlid sitution. E 1 I s1 E 2 FIG. 8.19 Demonstrting the need for n pproch such s rnch-current nlysis. Brnch-Current Anlysis Procedure 1. Assign distinct current of ritrry direction to ech rnch of the network. 2. Indicte the polrities for ech resistor s determined y the ssumed current direction. 3. Apply Kirchhoff s voltge lw round ech closed, independent loop of the network. The est wy to determine how mny times Kirchhoff s voltge lw hs to e pplied is to determine the numer of windows in the network. The network in Exmple 8.9 hs definite similrity to the two-window configurtion in Fig. 8.20(). The result is need to pply Kirchhoff s voltge lw twice. For networks with three windows, s shown in Fig. 8.20(), three pplictions of Kirchhoff s voltge lw re required, nd so on. 4. Apply Kirchhoff s current lw t the minimum numer of nodes tht will include ll the rnch currents of the network.

290 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) 1 2 1 2 3 1 2 3 1 2 3 () FIG. 8.20 Determining the numer of independent closed loops. () The minimum numer is one less thn the numer of independent nodes of the network. For the purposes of this nlysis, node is junction of two or more rnches, where rnch is ny comintion of series elements. Fig. 8.21 defines the numer of pplictions of Kirchhoff s current lw for ech configurtion in Fig. 8.20. (4 nodes) (4 nodes) 3 (2 nodes) 2 (2 nodes) 2 2 3 4 2 4 1 2 1 = 1 eq. 1 2 1 = 1 eq. 1 4 1 = 3 eq. 1 4 1 = 3 eq. FIG. 8.21 Determining the numer of pplictions of Kirchhoff s current lw required. 5. Solve the resulting simultneous liner equtions for ssumed rnch currents. It is ssumed tht the use of the determinnts method to solve for the currents I 1, I 2, nd I 3 is understood nd is prt of the student s mthemticl ckground. If not, detiled explntion of the procedure is provided in Appendix D. Clcultors nd computer softwre pckges such s Mthcd cn find the solutions quickly nd ccurtely. EXAMPLE 8.9 Apply the rnch-current method to the network in Fig. 8.22. I 1 I 2 1 d E 1 2 V I 3 E 2 6 V c FIG. 8.22 Exmple 8.9.

BRANCH-CURRENT ANALYSIS 291 Solution 1: Step 1: Since there re three distinct rnches (cd, c, c), three currents of ritrry directions (I 1, I 2, I 3 ) re chosen, s indicted in Fig. 8.22. The current directions for I 1 nd I 2 were chosen to mtch the pressure pplied y sources E 1 nd E 2, respectively. Since oth I 1 nd I 2 enter node, I 3 is leving. Step 2: Polrities for ech resistor re drwn to gree with ssumed current directions, s indicted in Fig. 8.23. Defined y I 3 Defined y I 1 Fixed polrity E 1 2 V I 1 1 I 3 I 2 2 E 2 1 6 V Defined y I 2 Fixed polrity FIG. 8.23 Inserting the polrities cross the resistive elements s defined y the chosen rnch currents. Step 3: Kirchhoff s voltge lw is pplied round ech closed loop (1 nd 2) in the clockwise direction: Rise in potentil loop 1: V E V 1 R V 1 R 0 3 Drop in potentil nd Rise in potentil loop 2: V V V R3 R E 0 2 Drop in potentil loop 1: V 2 V I I 0 1 3 Bttery Voltge drop potentil cross resistor Voltge drop cross resistor loop 2: V I 1 I 3 2 6 V 0 Step 4: Applying Kirchhoff s current lw t node (in two-node network, the lw is pplied t only one node), I 1 I I 3 Step 5: There re three equtions nd three unknowns (units removed for clrity): 2I 1 4I 3 0 Rewritten: 2I 1 0 4I 3 2 4I 3 1I 0 0 I 4I 3 6 I 1 I I 3 I 1 I I 3 0

292 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) Using third-order determinnts (Appendix D), we hve I 1 D 2 0 4 6 1 4 0 1 1 2 0 4 0 1 4 1 1 1 1 A A negtive sign in front of rnch current indictes only tht the ctul current is in the direction opposite to tht ssumed. I 2 2 4 0 6 4 1 0 1 D 2 A I 3 2 0 2 0 1 6 1 1 0 D 1 A Mthcd Solution: Once you understnd the procedure for entering the prmeters, you cn use Mthcd to solve determinnts such s ppering in Solution 1 in very short time frme. The numertor is defined y n with the sequence n. Then you pply the sequence View- Toolrs-Mtrix to otin the Mtrix toolr ppering in Fig. 8.24. Selecting the top left option clled Mtrix results in the Insert Mtrix dilog ox in which 3 3 is selected. The 3 3 mtrix ppers with rcket to signl which prmeter should e entered. Enter tht prmeter, nd then left-click to select the next prmeter you wnt to enter. When you hve finished, move on to define the denomintor d in the sme mnner. Then define the current of interest, select Determinnt (1 1) from the Mtrix toolr, nd insert the numertor vrile n. Follow with division sign, nd enter the Determinnt of the denomintor s shown in Fig. 8.24. Retype I1 nd select the equl sign; the correct result of 1 will pper. ( ) 2 0 4 n := 6 1 4 d := 0 1 4 I1 := 0 1 1 ( ) 2 0 4 1 1 1 n d I1 = 1 FIG. 8.24 Using Mthcd to verify the numericl clcultions of Exmple 8.9.

BRANCH-CURRENT ANALYSIS 293 Once you hve mstered the rther simple nd direct process just descried, you will deeply pprecite eing le to use Mthcd s checking tool or solving mechnism. Solution 2: Insted of using third-order determinnts s in Solution 1, we cn reduce the three equtions to two y sustituting the third eqution in the first nd second equtions: I 3 2I 1 4 I 1 I 2 0 2I 1 4I 1 4I 2 0 I 3 4 I 1 I 2 I 2 0 4I 1 4I 2 I 2 0 or 6I 1 4I 2 4I 1 5I 6 Multiplying through y 1 in the top eqution yields 6I 1 4I 2 4I 1 5I 6 nd using determinnts, I 1 2 4 ` 6 5 ` 6 4 ` 4 5 ` 10 214 30 16 11 A TI-89 Solution: The procedure for determining the determinnt in Exmple 8.9 requires some scrolling to otin the desired mth functions, ut in time tht procedure cn e performed quite rpidly. As with ny computer or clcultor system, it is prmount tht you enter ll prmeters correctly. One error in the sequence negtes the entire process. For the T1-89, the entries re shown in Fig. 8.25. Home 2ND MATH Mtrix det 2ND [ ENTER ENTE, 4 2ND ; 6, 5 2ND ] ) 2ND MATH Mtrix ENTER det ENTEND [ 6, 4 2ND ; 4, 5 2ND ] ) ENTER FIG. 8.25 After you select the lst ENTER key, the screen shown in Fig. 8.26 ppers. 6 2 ` 4 6 ` 3 8 I 28 14 14 1 2 A I 3 I 1 I 1 1 A It is now importnt tht the impct of the results otined e understood. The currents I 1, I 2, nd I 3 re the ctul currents in the rnches in 2 4 det 6 5 = 1.00E0 6 4 det 4 5 FIG. 8.26

294 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) E 1 I 1 = 1 A 2 V I 3 = 1 A I 2 = 2 A E 2 1 6 V FIG. 8.27 Reviewing the results of the nlysis of the network in Fig. 8.22. which they were defined. A negtive sign in the solution mens tht the ctul current hs the opposite direction thn initilly defined the mgnitude is correct. Once the ctul current directions nd their mgnitudes re inserted in the originl network, the vrious voltges nd power levels cn e determined. For this exmple, the ctul current directions nd their mgnitudes hve een entered on the originl network in Fig. 8.27. Note tht the current through the series elements nd E 1 is 1 A; the current through, 1 A; nd the current through the series elements nd E 2,2A. Due to the minus sign in the solution, the direction of I 1 is opposite to tht shown in Fig. 8.22. The voltge cross ny resistor cn now e found using Ohm s lw, nd the power delivered y either source or to ny one of the three resistors cn e found using the pproprite power eqution. Applying Kirchhoff s voltge lw round the loop indicted in Fig. 8.27, A V ()I 3 (1 )I 6 V 0 or ()I 3 (1 )I 6 V nd ()(1 A) (1 )(2 A) 6 V 4 V 2 V 6 V 6 V 6 V (checks) E 1 I 1 10 I 3 15 V 1 E 3 20 V 2 FIG. 8.28 Exmple 8.10. I 2 5 E 2 40 V EXAMPLE 8.10 Apply rnch-current nlysis to the network in Fig. 8.28. Solution: Agin, the current directions were chosen to mtch the pressure of ech ttery. The polrities re then dded, nd Kirchhoff s voltge lw is pplied round ech closed loop in the clockwise direction. The result is s follows: loop 1: 15 V ()I 1 (10 )I 3 20 V 0 loop 2: 20 V (10 )I 3 (5 )I 40 V 0 Applying Kirchhoff s current lw t node, I 1 I 3 I 2 Sustituting the third eqution into the other two yields (with units removed for clrity) 15 4I 1 10I 3 20 0 Sustituting for I 2 (since it occurs only once in the two equtions) 20 10I 3 5(I 1 I 3 ) 40 0 or 4I 1 10I 3 5 5I 1 15I 3 60 Multiplying the lower eqution y 1, we hve 4I 1 10I 3 5 5I 1 15I 3 60 I 1 5 10 ` 60 15 ` 4 10 ` 5 15 ` 75 600 525 4.77 A 60 50 110 4 5 ` 5 60 ` 240 25 I 3 265 2.41 A 110 110 110 I I 1 I 3 4.77 A 2.41 A 7.18 A reveling tht the ssumed directions were the ctul directions, with I 2 equl to the sum of I 1 nd I 3.

MESH ANALYSIS (GENERAL APPROACH) 295 8.7 MESH ANALYSIS (GENERAL APPROACH) The next method to e descried mesh nlysis is ctully n extension of the rnch-current nlysis pproch just introduced. By defining unique rry of currents to the network, the informtion provided y the ppliction of Kirchhoff s current lw is lredy included when we pply Kirchhoff s voltge lw. In other words, there is no need to pply step 4 of the rnch-current method. The currents to e defined re clled mesh or loop currents. The two terms re used interchngely. In Fig. 8.29(), network with two windows hs hd two mesh currents defined. Note tht ech forms closed loop round the inside of ech window; these loops re similr to the loops defined in the wire mesh fence in Fig. 8.29() hence the use of the term mesh for the loop currents. We will find tht the numer of mesh currents required to nlyze network will equl the numer of windows of the configurtion. E 1 I 1 I 2 E 2 () () FIG. 8.29 Defining the mesh (loop) current: () two-window network: () wire mesh fence nlogy. The defined mesh currents cn initilly e little confusing ecuse it ppers tht two currents hve een defined for resistor. There is no prolem with E 1 nd, which hve only current I 1, or with E 2 nd, which hve only current I 2. However, defining the current through my seem little troulesome. Actully, it is quite strightforwrd. The current through is simply the difference etween I 1 nd I 2, with the direction of the lrger. This is demonstrted in the exmples to follow. Becuse mesh currents cn result in more thn one current through n element, rnch-current nlysis ws introduced first. Brnch-current nlysis is the strightforwrd ppliction of the sic lws of electric circuits. Mesh nlysis employs mneuver ( trick, if you prefer) tht removes the need to pply Kirchhoff s current lw. Mesh Anlysis Procedure 1. Assign distinct current in the clockwise direction to ech independent, closed loop of the network. It is not solutely necessry to choose the clockwise direction for ech loop current. In fct, ny direction cn e chosen for ech loop current with no loss in ccurcy, s long s the remining steps re followed properly. However, y choosing the clockwise direction s stndrd, we cn develop shorthnd method (Section 8.8) for writing the required equtions tht will sve time nd possily prevent some common errors.

296 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) 1 1 2 I 2 I 1 E 1 2 V 6 V E 2 I 3 FIG. 8.30 Defining the mesh currents for two-window network. This first step is ccomplished most effectively y plcing loop current within ech window of the network, s demonstrted in the previous section, to ensure tht they re ll independent. A vriety of other loop currents cn e ssigned. In ech cse, however, e sure, tht the informtion crried y ny one loop eqution is not included in comintion of the other network equtions. This is the crux of the terminology: independent. No mtter how you choose your loop currents, the numer of loop currents required is lwys equl to the numer of windows of plnr (nocrossovers) network. On occsion, network my pper to e nonplnr. However, redrwing of the network my revel tht it is, in fct, plnr. This my e true for one or two prolems t the end of the chpter. Before continuing to the next step, let us ensure tht the concept of loop current is cler. For the network in Fig. 8.30, the loop current I 1 is the rnch current of the rnch contining the resistor nd 2 V ttery. The current through the resistor is not I 1, however, since there is lso loop current I 2 through it. Since they hve opposite directions, I 4 equls the difference etween the two, I 1 I 2 or I I 1, depending on which you choose to e the defining direction. In other words, loop current is rnch current only when it is the only loop current ssigned to tht rnch. 2. Indicte the polrities within ech loop for ech resistor s determined y the ssumed direction of loop current for tht loop. Note the requirement tht the polrities e plced within ech loop. This requires, s shown in Fig. 8.30, tht the resistor hve two sets of polrities cross it. 3. Apply Kirchhoff s voltge lw round ech closed loop in the clockwise direction. Agin, the clockwise direction ws chosen to estlish uniformity nd prepre us for the method to e introduced in the next section.. If resistor hs two or more ssumed currents through it, the totl current through the resistor is the ssumed current of the loop in which Kirchhoff s voltge lw is eing pplied, plus the ssumed currents of the other loops pssing through in the sme direction, minus the ssumed currents through in the opposite direction.. The polrity of voltge source is unffected y the direction of the ssigned loop currents. 4. Solve the resulting simultneous liner equtions for the ssumed loop currents. EXAMPLE 8.11 Consider the sme sic network s in Exmple 8.9, now ppering s Fig. 8.30. Solution: Step 1: Two loop currents (I 1 nd I 2 ) re ssigned in the clockwise direction in the windows of the network. A third loop (I 3 ) could hve een included round the entire network, ut the informtion crried y this loop is lredy included in the other two. Step 2: Polrities re drwn within ech window to gree with ssumed current directions. Note tht for this cse, the polrities cross the resistor re the opposite for ech loop current. Step 3: Kirchhoff s voltge lw is pplied round ech loop in the clockwise direction. Keep in mind s this step is performed tht the lw is con-

MESH ANALYSIS (GENERAL APPROACH) 297 cerned only with the mgnitude nd polrity of the voltges round the closed loop nd not with whether voltge rise or drop is due to ttery or resistive element. The voltge cross ech resistor is determined y V IR. For resistor with more thn one current through it, the current is the loop current of the loop eing exmined plus or minus the other loop currents s determined y their directions. If clockwise pplictions of Kirchhoff s voltge lw re lwys chosen, the other loop currents re lwys sutrcted from the loop current of the loop eing nlyzed. loop 1: E 1 V 1 V 3 0 (clockwise strting t point ) Voltge drop cross resistor 2 V I 1 I 1 I 2 0 Totl current through resistor Sutrcted since I 2 is opposite in direction to I 1. loop 2: V 3 V E 0 (clockwise strting t point ) ()(I I 1 ) (1 )I 6 V 0 Step 4: The equtions re then rewritten s follows (without units for clrity): loop 1: 2I 1 4I 1 4I 0 loop 2: 4I 4I 1 1I 0 nd loop 1: 6I 1 4I 0 loop 2: 5I 4I 1 0 or loop 1: 6I 1 4I 2 loop 2: 4I 1 5I 6 Applying determinnts results in I 1 1 A nd I 2 A The minus signs indicte tht the currents hve direction opposite to tht indicted y the ssumed loop current. The ctul current through the 2 V source nd resistor is therefore 1 A in the other direction, nd the current through the 6 V source nd 1 resistor is 2 A in the opposite direction indicted on the circuit. The current through the resistor is determined y the following eqution from the originl network: loop 1: I 4 I 1 I 1 A (2 A) 1 A 2 A 1 A (in the direction of I 1 ) The outer loop (I 3 ) nd one inner loop (either I 1 or I 2 ) would lso hve produced the correct results. This pproch, however, often leds to errors since the loop equtions my e more difficult to write. The est method of picking these loop currents is the window pproch. EXAMPLE 8.12 Find the current through ech rnch of the network in Fig. 8.31. Solution: Steps 1 nd 2: These re s indicted in the circuit. Note tht the polrities of the resistor re different for ech loop current. E 1 1 5 V 1 I 1 E 2 10 V 2 I 2 FIG. 8.31 Exmple 8.12.

298 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) Step 3: Kirchhoff s voltge lw is pplied round ech closed loop in the clockwise direction: loop 1: E 1 V 1 V E 0 (clockwise strting t point ) 5 V (1 )I 1 ()(I 1 I 2 ) 10 V 0 I 2 flows through the 6 Q resistor in the direction opposite to I 1. loop 2: E V V 3 0 (clockwise strting t point ) 10 V ()(I I 1 ) ()I 0 The equtions re rewritten s Step 4: 5 I 1 6I 1 6I 10 0 10 6I 6I 1 2I 0 r 7I 1 6I 5 6I 1 8I 10 I 1 I 5 6 ` 10 8 ` 7 6 ` 8 ` 7 5 ` 10 ` 20 40 60 5 36 70 30 20 20 20 1 A 40 20 2 A Since I 1 nd I 2 re positive nd flow in opposite directions through the resistor nd 10 V source, the totl current in this rnch is equl to the difference of the two currents in the direction of the lrger: I 2 > I 1 (2 A > 1 A) Therefore, I R2 I I 1 2 A 1 A 1 A in the direction of I 2 It is sometimes imprcticl to drw ll the rnches of circuit t right ngles to one nother. The next exmple demonstrtes how portion of network my pper due to vrious constrints. The method of nlysis is no different with this chnge in configurtion. E 1 = 6 V = E 2 4 V 1 2 I 1 I 2 FIG. 8.32 Exmple 8.13. = E 3 = 3 V EXAMPLE 8.13 Find the rnch currents of the networks in Fig. 8.32. Solution: Steps 1 nd 2: These re s indicted in the circuit. Step 3: Kirchhoff s voltge lw is pplied round ech closed loop: loop 1: E 1 I 1 E V 0 (clockwise from point ) 6 V ()I 1 4 V ()(I 1 I 2 ) 0 loop 2: V E V 3 E 3 0 (clockwise from point ) ()(I I 1 ) 4 V ()(I 2 ) 3 V 0 which re rewritten s 10 4I 1 2I 1 4I 0 1 4I 1 4I 6I 0 r 6I 1 4I 10 4I 1 10I 1

MESH ANALYSIS (GENERAL APPROACH) 299 or, y multiplying the top eqution y 1, we otin 6I 1 4I 10 4I 1 10I 1 Step 4: 10 4 ` 1 10 ` 100 4 96 I 1 4 ` 10 ` 60 142.18 A I 10 ` 1 ` 44 40 44 34 40.77 A The current in the resistor nd 4 V source for loop 1 is I 1 I 2.18 A (0.77 A) 2.18 A 0.77 A 1.41 A reveling tht it is 1.41 A in direction opposite (due to the minus sign) to I 1 in loop 1. Supermesh Currents Occsionlly, you will find current sources in network without prllel resistnce. This removes the possiility of converting the source to voltge source s required y the given procedure. In such cses, you hve choice of two pproches. The simplest nd most direct pproch is to plce resistor in prllel with the current source tht hs much higher vlue thn the other resistors of the network. For instnce, if most of the resistors of the network re in the 1 to 10 rnge, choosing resistor of 100 or higher would provide one level of ccurcy for the nswer. However, choosing resistor of 1000 or higher would increse the ccurcy of the nswer. You will never get the exct nswer ecuse the network hs een modified y this introduced element. However for most pplictions, the nswer will e sufficiently ccurte. The other choice is to use the Supermesh pproch descried in the following steps. Although this pproch will provide the exct solution, it does require some prctice to ecome proficient in its use. The procedure is s follows. Strt s efore nd ssign mesh current to ech independent loop, including the current sources, s if they were resistors or voltge sources. Then mentlly (redrw the network if necessry) remove the current sources (replce with open-circuit equivlents), nd pply Kirchhoff s voltge lw to ll the remining independent pths of the network using the mesh currents just defined. Any resulting pth, including two or more mesh currents, is sid to e the pth of supermesh current. Then relte the chosen mesh currents of the network to the independent current sources of the network, nd solve for the mesh currents. The next exmple clrifies the definition of supermesh current nd the procedure. E 1 20 V I 4 A E 2 12 V EXAMPLE 8.14 Using mesh nlysis, determine the currents of the network in Fig. 8.33. FIG. 8.33 Exmple 8.14.

300 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) E 1 20 V I 1 I 4 A I 2 E 2 12 V E 1 I 1 I 2 20 V E 2 12 V Supermesh current FIG. 8.34 Defining the mesh currents for the network in Fig. 8.33. FIG. 8.35 Defining the supermesh current. Solution: First, the mesh currents for the network re defined, s shown in Fig. 8.34. Then the current source is mentlly removed, s shown in Fig. 8.35, nd Kirchhoff s voltge lw is pplied to the resulting network. The single pth now including the effects of two mesh currents is referred to s the pth of supermesh current. Applying Kirchhoff s lw: 20 V I 1 () I 1 () I 2 () 12 V 0 or 10I 1 2I 32 Node is then used to relte the mesh currents nd the current source using Kirchhoff s current lw: I 1 I I 2 The result is two equtions nd two unknowns: 10I 1 2I 32 I 1 I 4 Applying determinnts: I 1 32 2 ` 1 ` 10 2 ` 1 1 ` 132211 122142 110211 122112 40 3.33 A 12 nd I I 1 I 3.33 A 4 A 0.67 A In the ove nlysis, it my pper tht when the current source ws removed, I 1 I 2. However, the supermesh pproch requires tht we stick with the originl definition of ech mesh current nd not lter those definitions when current sources re removed. EXAMPLE 8.15 Using mesh nlysis, determine the currents for the network in Fig. 8.36. 6 A 8 8 A FIG. 8.36 Exmple 8.15.

MESH ANALYSIS (FORMAT APPROACH) 301 6 A I 1 I 2 8 I 3 8 A I 1 I 2 8 I 3 FIG. 8.37 Defining the mesh currents for the network in Fig. 8.36. Solution: The mesh currents re defined in Fig. 8.37. The current sources re removed, nd the single supermesh pth is defined in Fig. 8.38. Applying Kirchhoff s voltge lw round the supermesh pth: V 2 V 6 V 8 0 (I I 1 )I 2 () (I I 3 )8 0 2I 2I 1 6I 8I 8I 3 0 2I 1 16I 8I 3 0 Introducing the reltionship etween the mesh currents nd the current sources: I 1 6 A I 3 8 A results in the following solutions: 2I 1 16I 8I 3 0 2(6 A) 16I 8(8 A) 0 nd I 76 A 4.75 A 16 Then I 2 I 1 I 6 A 4.75 A 1.25 A nd I 8 I 3 I 8 A 4.75 A 3.25 A Agin, note tht you must stick with your originl definitions of the vrious mesh currents when pplying Kirchhoff s voltge lw round the resulting supermesh pths. Supermesh current FIG. 8.38 Defining the supermesh current for the network in Fig. 8.36. 8.8 MESH ANALYSIS (FORMAT APPROACH) Now tht the sis for the mesh-nlysis pproch hs een estlished, we now exmine technique for writing the mesh equtions more rpidly nd usully with fewer errors. As n id in introducing the procedure, the network in Exmple 8.12 (Fig. 8.31) hs een redrwn in Fig. 8.39 with the ssigned loop currents. (Note tht ech loop current hs clockwise direction.) The equtions otined re E 1 1 1 2 5 V E 2 10 V I 1 I 2 which cn lso e written s 7I 1 6I 5 6I 1 8I 10 7I 1 6I 5 8I 6I 1 10 FIG. 8.39 Network in Fig. 8.31 redrwn with ssigned loop currents.

302 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) nd expnded s Col. 1 Col. 2 Col. 3 (1 6)I 1 6I (5 10) ( 6)I 6I 1 10 Note in the ove equtions tht column 1 is composed of loop current times the sum of the resistors through which tht loop current psses. Column 2 is the product of the resistors common to nother loop current times tht other loop current. Note tht in ech eqution, this column is sutrcted from column 1. Column 3 is the lgeric sum of the voltge sources through which the loop current of interest psses. A source is ssigned positive sign if the loop current psses from the negtive to the positive terminl, nd negtive vlue is ssigned if the polrities re reversed. The comments ove re correct only for stndrd direction of loop current in ech window, the one chosen eing the clockwise direction. The ove sttements cn e extended to develop the following formt pproch to mesh nlysis. I 1 I 2 8 1 2 7 4 V 9 V FIG. 8.40 Exmple 8.16. Mesh Anlysis Procedure 1. Assign loop current to ech independent, closed loop (s in the previous section) in clockwise direction. 2. The numer of required equtions is equl to the numer of chosen independent, closed loops. Column 1 of ech eqution is formed y summing the resistnce vlues of those resistors through which the loop current of interest psses nd multiplying the result y tht loop current. 3. We must now consider the mutul terms, which, s noted in the exmples ove, re lwys sutrcted from the first column. A mutul term is simply ny resistive element hving n dditionl loop current pssing through it. It is possile to hve more thn one mutul term if the loop current of interest hs n element in common with more thn one other loop current. This will e demonstrted in n exmple to follow. Ech term is the product of the mutul resistor nd the other loop current pssing through the sme element. 4. The column to the right of the equlity sign is the lgeric sum of the voltge sources through which the loop current of interest psses. Positive signs re ssigned to those sources of voltge hving polrity such tht the loop current psses from the negtive to the positive terminl. A negtive sign is ssigned to those potentils for which the reverse is true. 5. Solve the resulting simultneous equtions for the desired loop currents. Before considering few exmples, e wre tht since the column to the right of the equls sign is the lgeric sum of the voltge sources in tht loop, the formt pproch cn e pplied only to networks in which ll current sources hve een converted to their equivlent voltge source. EXAMPLE 8.16 Write the mesh equtions for the network in Fig. 8.40, nd find the current through the 7 resistor.

MESH ANALYSIS (FORMAT APPROACH) 303 Solution: Step 1: As indicted in Fig. 8.40, ech ssigned loop current hs clockwise direction. Steps 2 to 4: I 1 : (8 )I 1 ()I 4 V I 2 : (7 )I ()I 1 9 V nd 16I 1 2I 4 9I 2I 1 9 which, for determinnts, re 16I 1 2I 4 2I 1 9I 9 nd I I 7 16 4 ` 9 ` 12 ` 2 9 ` 0.97 A 14 8 14 4 136 140 EXAMPLE 8.17 Write the mesh equtions for the network in Fig. 8.41. 1 4 V 2 V 1 2 3 3 2 V 1 I 1 I 2 I 3 FIG. 8.41 Exmple 8.17. Solution: Ech window is ssigned loop current in the clockwise direction: I 1 does not pss through n element mutul with I 3. I 1 : I 2 : I 3 : 1 1 I 1 1 I 2 0 2 V 4 V 1 3 I 2 1 I 1 3 I 3 4 V 3 I 3 3 I 2 0 2 V I 3 does not pss through n element mutul with I 1. Summing terms yields 2I 1 I 0 2 6I I 1 3I 3 4 7I 3 3I 0 2

304 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) which re rewritten for determinnts s c 2I 1 I 2 0 2 I 1 6I 2 3I 3 4 0 3I 2 7I 3 2 Note tht the coefficients of the nd digonls re equl. This symmetry out the c-xis will lwys e true for equtions written using the formt pproch. It is check on whether the equtions were otined correctly. We now consider network with only one source of voltge to point out tht mesh nlysis cn e used to dvntge in other thn multisource networks. EXAMPLE 8.18 Find the current through the 10 resistor of the network in Fig. 8.42. 10 I 10 = I 3 15 V 8 5 1 3 2 I 1 3 I 3 I 2 FIG. 8.42 Exmple 8.18. Solution: I 1 : (8 3 )I 1 (8 )I 3 (3 )I 15 V I 2 : (3 5 )I (3 )I 1 (5 )I 3 0 I 3 : (8 10 5 )I 3 (8 )I 1 (5 )I 0 or 11I 1 8I 3 3I 15 V 10I 3I 1 5I 3 0 23I 3 8I 1 5I 0 11I 1 3I 8I 3 15 V 3I 1 10I 5I 3 0 8I 1 5I 23I 3 0

MESH ANALYSIS (FORMAT APPROACH) 305 nd I 3 I 10 11 3 15 3 10 0 8 5 0 11 3 8 3 10 5 8 5 23 1.22 A Mthcd Solution: For this exmple, rther thn tke the time to develop the determinnt form for ech vrile, we pply Mthcd directly to the resulting equtions. As shown in Fig. 8.43, Guess vlue for ech vrile must first e defined. Such guessing helps the computer egin its itertion process s it serches for the solution. By providing rough estimte of 1, the computer recognizes tht the result is proly numer with mgnitude less thn 100 rther thn hve to worry out solutions tht extend into the thousnds or tens of thousnds the serch hs een nrrowed considerly. I1 := 1.A I2 := 1.A I3 := 1.A Given ( 8. 3.).I1 8..I3 3..I2 = 15.V ( 3. 5. 2.).I2 3..I1 5..I3 = 0.V ( 8. 10. 5.).I3 8..I1 5..I2 = 0.V ( ) 2.633 Find( I1, I2, I3) = 1.4 A 1.22 FIG. 8.43 Using Mthcd to verify the numericl clcultions of Exmple 8.18. Next, s shown, enter the word Given to tell the computer tht the defining equtions will follow. Finlly, crefully enter ech eqution nd set ech one equl to the constnt on the right using the Ctrl opertion. The results re then otined with the Find (I1,I2,I3) expression nd n equl sign. As shown, the results re ville with n cceptle degree of ccurcy even though entering the equtions nd performing the nlysis took only minute or two (with prctice). TI-89 Clcultor Solution: Using the TI-89 clcultor, the sequence in Fig. 8.44 results. The intermediry 2ND nd scrolling steps were not

306 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) det([11,3,15;3,10,0;8,5,0])/det([11,3,8;3,10,5;8,5,23]) ENTE.22 det det 11 3 8 11 3 8 3 10 5 3 10 5 15 0 0 8 5 23 1.22E0 FIG. 8.45 The resulting disply fter properly entering the dt for the current I 3. FIG. 8.44 Using the TI-89 clcultor to solve for the current I 3. included. This sequence certinly requires some cre in entering the dt in the required formt, ut it is still rther net, compct formt. The resulting disply in Fig. 8.45 confirms our solution. 8.9 NODAL ANALYSIS (GENERAL APPROACH) The methods introduced thus fr hve ll een to find the currents of the network. We now turn our ttention to nodl nlysis method tht provides the nodl voltges of network, tht is, the voltge from the vrious nodes (junction points) of the network to ground. The method is developed through the use of Kirchhoff s current lw in much the sme mnner s Kirchhoff s voltge lw ws used to develop the mesh nlysis pproch. Although it is not requirement, we mke it policy to mke ground our reference node nd ssign it potentil level of zero volts. All the other voltge levels re then found with respect to this reference level. For network of N nodes, y ssigning one s our reference node, we hve (N 1) nodes for which the voltge must e determined. In other words, the numer of nodes for which the voltge must e determined using nodl nlysis is 1 less thn the totl numer of nodes. The result of the ove is (N 1) nodl voltges tht need to e determined, requiring tht (N 1) independent equtions e written to find the nodl voltges. In other words, the numer of equtions required to solve for ll the nodl voltges of network is 1 less thn the totl numer of independent nodes. Since ech eqution is the result of n ppliction of Kirchhoff s current lw, Kirchhoff s current lw must e pplied (N 1) times for ech network. Nodl nlysis, like mesh nlysis, cn e pplied y series of crefully defined steps. The exmples to follow explin ech step in detil. Nodl Anlysis Procedure 1. Determine the numer of nodes within the network. 2. Pick reference node, nd lel ech remining node with suscripted vlue of voltge: V 1,V 2, nd so on. 3. Apply Kirchhoff s current lw t ech node except the reference. Assume tht ll unknown currents leve the node for ech ppliction of Kirchhoff s current lw. In other words, for ech node, don t e influenced y the direction tht n unknown current for nother node my hve hd. Ech node is to e treted s seprte entity, independent of the ppliction of Kirchhoff s current lw to the other nodes. 4. Solve the resulting equtions for the nodl voltges.

NODAL ANALYSIS (GENERAL APPROACH) 307 A few exmples clrify the procedure defined y step 3. It initilly tkes some prctice writing the equtions for Kirchhoff s current lw correctly, ut in time the dvntge of ssuming tht ll the currents leve node rther thn identifying specific direction for ech rnch ecome ovious. (The sme type of dvntge is ssocited with ssuming tht ll the mesh currents re clockwise when pplying mesh nlysis.) EXAMPLE 8.19 Apply nodl nlysis to the network in Fig. 8.46. Solution: Steps 1 nd 2: The network hs two nodes, s shown in Fig. 8.47. The lower node is defined s the reference node t ground potentil (zero volts), nd the other node s V 1, the voltge from node 1 to ground. Step 3: I 1 nd I 2 re defined s leving the node in Fig. 8.48, nd Kirchhoff s current lw is pplied s follows: I I 1 I 2 The current I 2 is relted to the nodl voltge V 1 y Ohm s lw: The current I 1 is lso determined y Ohm s lw s follows: with V R1 V 1 E Sustituting into the Kirchhoff s current lw eqution: nd rerrnging, we hve or I V 1 E V 1 V 1 1 1 E V 1 1 1 E 1 Sustituting numericl vlues, we otin V 1 1 1 24 V 1 A 4 A 1 A 1 V 1 1 5 A The currents I 1 nd I 2 cn then e determined using the preceding equtions: I 1 V 1 E 0.67 A I V V 1 I 1 V I V 1 E V 1 V 1 20 V 20 V 24 V 4 V E E 24 V 24 V 1 FIG. 8.46 Exmple 8.19. V 1 1 I I (0 V) 1 A 1 A FIG. 8.47 Network in Fig. 8.46 with ssigned nodes. I 1 E 24 V V 1 I 2 1 (0 V) I 1 A FIG. 8.48 Applying Kirchhoff s current lw to the node V 1.

308 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) E 8 64 V I 2 A 10 The minus sign indictes tht the current I 1 hs direction opposite to tht ppering in Fig. 8.48. I V 1 20 V 1.67 A 1 EXAMPLE 8.20 Apply nodl nlysis to the network in Fig. 8.49. Solution: V 1 8 E 64 V FIG. 8.49 Exmple 8.20. I 2 A V 2 10 Steps 1 nd 2: The network hs three nodes, s defined in Fig. 8.50, with the ottom node gin defined s the reference node (t ground potentil, or zero volts), nd the other nodes s V 1 nd V 2. Step 3: For node V 1, the currents re defined s shown in Fig. 8.51 nd Kirchhoff s current lw is pplied: 0 I 1 I I with nd so tht I 1 V 1 E I V V 1 V 2 V 1 E V 1 V 2 I 0 FIG. 8.50 Defining the nodes for the network in Fig. 8.49. or V 1 E V 1 V 2 I 0 V 1 I 1 8 E 64 V I 2 I 2 A V 2 10 nd Sustituting vlues: V 1 1 1 V 2 1 I E V 1 1 8 1 V 2 1 64 V 2 A 8 6 A For node V 2 the currents re defined s shown in Fig. 8.52, nd Kirchhoff s current lw is pplied: I I I 3 FIG. 8.51 Applying Kirchhoff s current lw to node V 1. with or I V V 1 V 2 I V 2 V 1 V 2 E V 1 8 64 V I 2 A 10 FIG. 8.52 Applying Kirchhoff s current lw to node V 2. I 2 V 2 I 3 nd Sustituting vlues: V 2 1 1 V 1 1 I V 2 1 1 10 V 1 1 2 A Step 4: The result is two equtions nd two unknowns: V 1 1 8 1 V 2 1 6 A V 1 1 V 2 1 1 10 2 A

NODAL ANALYSIS (GENERAL APPROACH) 309 which ecome 0.375V 1 0.25V 6 0.25V 1 0.35V 2 Using determinnts, V 1 37.82 V V 32.73 V Since E is greter thn V 1, the current I 1 flows from ground to V 1 nd is equl to I R1 E V 1 The positive vlue for V 2 results in current equl to I R3 V V 2 32.73 V 3.27 A 10 Since V 1 is greter thn V 2, the current equl to I R2 V 1 V 2 64 V 37.82 V 8 37.82 V 32.73 V from node V 2 to ground flows from V 1 to V 2 nd is 1.27 A Mthcd Solution: For this exmple, we will use Mthcd to work directly with the Kirchhoff s current lw equtions rther thn solving it mthemticlly. Simply define everything correctly, provide the Guess vlues, nd insert Given where required. The process should e quite strightforwrd. Note in Fig. 8.53 tht the first eqution comes from the fct tht I 1 I I 0 while the second eqution comes from I I 3 I. Note tht the first eqution is defined y Fig. 8.51 nd the second y Fig. 8.52 ecuse the direction of I 2 is different for ech. I R2 I R3 3.27 A I := 2. A E := 64. V R1 := 8. R2 := 4. R3 := 10. V1 := 1. V V2 := 1. V Given V1 E V1 V2 I = 0 R1 R2 V2 V1 V2 = I R2 R3 37.818 Find( V1, V2) = V ( 32.727) FIG. 8.53 Using Mthcd to verify the mthemticl clcultions of Exmple 8.20.

310 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) The results of V 1 37.82 V nd V 32.73 V confirm the theoreticl solution. EXAMPLE 8.21 Determine the nodl voltges for the network in Fig. 8.54. 1 4 A 2 A FIG. 8.54 Exmple 8.21. Solution: Steps 1 nd 2: As indicted in Fig. 8.55: I 3 V 1 V 2 = 1 4 A I 1 2 A Reference FIG. 8.55 Defining the nodes nd pplying Kirchhoff s current lw to the node V 1. Step 3: Included in Fig. 8.55 for the node V 1. Applying Kirchhoff s current lw: 4 A I 1 I 3 nd 4 A V 1 V 1 V 2 V 1 V 1 V 2 1 Expnding nd rerrnging: V 1 1 1 1 V 2 1 1 4 A For node V 2, the currents re defined s in Fig. 8.56. V 1 I 3 V 2 = 1 4 A I 2 2 A Reference FIG. 8.56 Applying Kirchhoff s current lw to the node V 2.

NODAL ANALYSIS (GENERAL APPROACH) 311 Applying Kirchhoff s current lw: 0 I 3 I 2 A V V 1 nd V 2 2 A 0 V V 1 1 V 2 2 A 0 Expnding nd rerrnging: resulting in Eq. (8.1), which consists of two equtions nd two unknowns: producing V 2 1 1 1 V 1 1 1 2 A V 1 1 1 1 V 2 1 1 4 A V 2 1 1 1 V 1 1 2 A 1 7 1 V 1 V 4 12 12 7V 1 V 48 1 3 V 1 V 2 12 12 1V 1 3V 24 (8.1) nd V 1 48 1 ` 24 3 ` 120 7 1 20 ` 1 3` 6 V V Since V 1 is greter thn V 2, the current through psses from V 1 to V 2. Its vlue is I R3 V 1 V 2 7 48 ` 1 24 ` 20 120 20 6 V 16 V2 1 The fct tht V 1 is positive results in current equl to 6 V I R1 I R1 V V 1 6 V 3 A 12 V 1 1 A from V 1 to ground Finlly, since V 2 is negtive, the current is equl to I R2 flows from ground to V 2 nd I R2 V V 2 6 V 1 A Supernode Occsionlly, you my encounter voltge sources in network tht do not hve series internl resistnce tht would permit conversion to current source. In such cses, you hve two options. The simplest nd most direct pproch is to plce resistor in series with the source of very smll vlue compred to the other resistive elements of

312 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) the network. For instnce, if most of the resistors re 10 or lrger, plcing 1 resistor in series with voltge source provides one level of ccurcy for your nswer. However, choosing resistor of 0.1 or less increses the ccurcy of your nswer.you will never get n exct nswer ecuse the network hs een modified y the introduced element. However, for most pplictions, the ccurcy will e sufficiently high. The other pproch is to use the Supernode pproch descried elow. This pproch provides n exct solution ut requires some prctice to ecome proficient. Strt s usul nd ssign nodl voltge to ech independent node of the network, including ech independent voltge source s if it were resistor or current source. Then mentlly replce the independent voltge sources with short-circuit equivlents, nd pply Kirchhoff s current lw to the defined nodes of the network. Any node including the effect of elements tied only to other nodes is referred to s supernode (since it hs n dditionl numer of terms). Finlly, relte the defined nodes to the independent voltge sources of the network, nd solve for the nodl voltges. The next exmple clrifies the definition of supernode. 10 E V 1 12 V 6 A 4 A FIG. 8.57 Exmple 8.22. V 2 EXAMPLE 8.22 Determine the nodl voltges V 1 nd V 2 in Fig. 8.57 using the concept of supernode. Solution: Replcing the independent voltge source of 12 V with short-circuit equivlent results in the network in Fig. 8.58. Even though the mentl ppliction of short-circuit equivlent is discussed ove, it would e wise in the erly stge of development to redrw the network s shown in Fig. 8.58. The result is single supernode for which Kirchhoff s current lw must e pplied. Be sure to leve the other defined nodes in plce nd use them to define the currents from tht region of the network. In prticulr, note tht the current I 3 leves the supernode t V 1 nd then enters the sme supernode t V 2. It must therefore pper twice when pplying Kirchhoff s current lw, s shown elow: I 3 10 I 3 Supernode or I i I o 6 A I 3 I 1 I 4 A I 3 I 1 I 6 A 4 A 2 A V 1 I 1 I 2 V 2 Then V 1 V 2 2 A 6 A 4 A FIG. 8.58 Defining the supernode for the network in Fig. 8.57. V 1 nd V 2 2 A Relting the defined nodl voltges to the independent voltge source, we hve V 1 V E 12 V which results in two equtions nd two unknowns: 0.25V 1 0.5V 2 V 1 1V 12 Sustituting: V 1 V 12 0.25(V 12) 0.5V 2 nd 0.75V 3 1

NODAL ANALYSIS (FORMAT APPROACH) 313 so tht V 1 1.33 V 0.75 nd V 1 V 12 V 1.33 V 12 V 10.67 V The current of the network cn then e determined s follows: I 1 T V 10.67 V S I 3 V 1 V 2 10 2.67 A I 2 c V 2 1.33 V 0.67 A 10.67 V 11.33 V2 10 A creful exmintion of the network t the eginning of the nlysis would hve reveled tht the voltge cross the resistor must e 12 V nd I 3 must e equl to 1.2 A. 1 1.2 A 10 8.10 NODAL ANALYSIS (FORMAT APPROACH) A close exmintion of Eq. (8.1) ppering in Exmple 8.21 revels tht the suscripted voltge t the node in which Kirchhoff s current lw is pplied is multiplied y the sum of the conductnces ttched to tht node. Note lso tht the other nodl voltges within the sme eqution re multiplied y the negtive of the conductnce etween the two nodes. The current sources re represented to the right of the equls sign with positive sign if they supply current to the node nd with negtive sign if they drw current from the node. These conclusions cn e expnded to include networks with ny numer of nodes. This llows us to write nodl equtions rpidly nd in form tht is convenient for the use of determinnts. A mjor requirement, however, is tht ll voltge sources must first e converted to current sources efore the procedure is pplied. Note the prllelism etween the following four steps of ppliction nd those required for mesh nlysis in Section 8.8. Nodl Anlysis Procedure 1. Choose reference node nd ssign suscripted voltge lel to the (N 1) remining nodes of the network. 2. The numer of equtions required for complete solution is equl to the numer of suscripted voltges (N 1). Column 1 of ech eqution is formed y summing the conductnces tied to the node of interest nd multiplying the result y tht suscripted nodl voltge. 3. We must now consider the mutul terms tht, s noted in the preceding exmple, re lwys sutrcted from the first column. It is possile to hve more thn one mutul term if the nodl voltge of current interest hs n element in common with more thn one other nodl voltge. This is demonstrted in n exmple to follow. Ech mutul term is the product of the mutul conductnce nd the other nodl voltge tied to tht conductnce. 4. The column to the right of the equlity sign is the lgeric sum of the current sources tied to the node of interest. A current source is

314 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) ssigned positive sign if it supplies current to node nd negtive sign if it drws current from the node. 5. Solve the resulting simultneous equtions for the desired voltges. Let us now consider few exmples. EXAMPLE 8.23 Write the nodl equtions for the network in Fig. 8.59. 3 I 1 2 A I 2 3 A FIG. 8.59 Exmple 8.23. Solution: Step 1: Redrw the figure with ssigned suscripted voltges in Fig. 8.60. V 1 V 2 3 I 1 2 A I 2 3 A Reference FIG. 8.60 Defining the nodes for the network in Fig. 8.59. Steps 2 to 4: Drwing current from node 1 1 1 1 V 1 : V 1 V 3 3 2 2 A Sum of conductnces connected to node 1 Mutul conductnce Supplying current to node 2 1 V 2 : 1 1 V 2 V 3 3 1 3 A Sum of conductnces connected to node 2 Mutul conductnce

NODAL ANALYSIS (FORMAT APPROACH) 315 nd 1 2 V 1 1 3 V 2 1 3 V 1 7 12 V 3 EXAMPLE 8.24 Find the voltge cross the 3 resistor in Fig. 8.61 y nodl nlysis. 10 8 V V 3 3 1 V FIG. 8.61 Exmple 8.24. Solution: Converting sources nd choosing nodes (Fig. 8.62), we hve V 1 V 2 4 A V 3 3 10 0.1 A Reference FIG. 8.62 Defining the nodes for the network in Fig. 8.61. 1 1 1 V 1 1 V 4 A 1 10 1 3 1 V 1 V 1 0.1 A 11 12 V 1 1 6 V 4 1 6 V 1 3 5 V 0.1 resulting in 11V 1 2V 48 5V 1 18V 3

316 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) nd V V 3 11 48 ` 5 3 ` 11 2 ` 5 18 ` 33 240 198 10 207 1.10 V 188 As demonstrted for mesh nlysis, nodl nlysis cn lso e very useful technique for solving networks with only one source. V 1 5 5 3 A FIG. 8.63 Exmple 8.25. V 4 5 5 V 2 3 A (0 V) V 3 FIG. 8.64 Defining the nodes for the network in Fig. 8.63. 10 EXAMPLE 8.25 Using nodl nlysis, determine the potentil cross the resistor in Fig. 8.63. Solution: The reference nd four suscripted voltge levels were chosen s shown in Fig. 8.64. Rememer tht for ny difference in potentil etween V 1 nd V 3, the current through nd the potentil drop cross ech 5 resistor is the sme. Therefore, V 4 is simply mid-voltge level etween V 1 nd V 3 nd is known if V 1 nd V 3 re ville. We will therefore not include it in nodl voltge nd will redrw the network s shown in Fig. 8.65. Understnd, however, tht V 4 cn e included if desired, lthough four nodl voltges will result rther thn three s in the solution of this prolem. V 1 : 1 1 1 10 V 1 1 V 1 10 V 3 0 V 2 : 1 1 V 1 V 1 1 V 3 3 A V 3 : 1 10 1 1 V 3 1 V 1 10 V 1 0 which re rewritten s For determinnts, 1.1V 1 0.5V 0.1V 3 0 V 0.5V 1 0.5V 3 3 0.85V 3 0.5V 0.1V 1 0 c 1.1V 1 0.5V 0.1V 3 0 0.5V 1 1V 2 0.5V 3 3 0.1V 1 0.5V 0.85V 3 0 V 1 V 2 V 3 3 A Before continuing, note the symmetry out the mjor digonl in the eqution ove. Recll similr result for mesh nlysis. Exmples 8.23 nd 8.24 lso exhiit this property in the resulting equtions. Keep this in mind s check on future pplictions of nodl nlysis. (0 V) FIG. 8.65 Reducing the numer of nodes for the network in Fig. 8.63 y comining the two 5 resistors. 1.1 0.5 0 0.5 1 3 0.1 0.5 0 V 3 V 4 4.65 V 1.1 0.5 0.1 0.5 1 0.5 0.1 0.5 0.85

NODAL ANALYSIS (FORMAT APPROACH) 317 V1 := 1. V V2 := 1. V V3 := 1. V Given 1 1 1 1 1 2. 2.. V1 10. 2.. V2 10.. V3 = 0. ( ) A 1 1 1 2. ( 2.. ) 2.. 1 V2 V1 2.. V3 = 3. A 1 1 1 10. ( 2.. 1 1 4. ) V3 2.. V2 10.. V1 = 0. A Find( V1, V2, V3) = ( ) 3.677 7.161 4.645 V FIG. 8.66 Using Mthcd to verify the mthemticl clcultions of Exmple 8.25. Mthcd Solution: By now, the sequence of steps necessry to solve series of equtions using Mthcd should e more fmilir nd esier to rememer. For this exmple, ll the prmeters re entered in the three simultneous equtions, voiding the need to define ech prmeter of the network. Simply provide Guess t the three nodl voltges, pply the word Given, nd enter the three equtions properly s shown in Fig. 8.66. It does tke some prctice to rememer to move the rcket to the proper loction efore mking n entry, ut you will soon understnd how the rules re needed to mintin control of the opertions to e performed. Finlly, request the desired nodl voltges using the correct formt. The numericl results pper, gin confirming our theoreticl solutions. The next exmple hs only one source pplied to ldder network. EXAMPLE 8.26 Write the nodl equtions nd find the voltge cross the resistor for the network in Fig. 8.67. 3 1 240 V 9 FIG. 8.67 Exmple 8.26.

318 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) V 1 V 2 V 3 1 20 A 1 (0 V) FIG. 8.68 Converting the voltge source to current source nd defining the nodes for the network in Fig. 8.67. Solution: The nodl voltges re chosen s shown in Fig. 8.68. nd V 1 : 1 1 1 1 V 1 1 V 0 20 A V 2 : 1 1 1 1 V 1 V 1 1 1 V 3 0 V 3 : 1 1 1 V 3 1 1 V 0 0 0.5V 1 0.25V 0 20 0.25V 1 17 12 V 1V 3 0 0 1V 1.5V 3 0 Note the symmetry present out the mjor xis. Appliction of determinnts revels tht V 3 V 2 10.67 V 8.11 BRIDGE NETWORKS This section introduces the ridge network, configurtion tht hs multitude of pplictions. In the following chpters, this type of network is used in oth dc nd c meters. Electronics courses introduce these in the discussion of rectifying circuits used in converting vrying signl to one of stedy nture (such s dc). A numer of other res of ppliction lso require some knowledge of c networks; these res re discussed lter. The ridge network my pper in one of the three forms s indicted in Fig. 8.69. The network in Fig. 8.69(c) is lso clled symmetricl lt- R 5 R 5 R 4 R 5 R 4 R 4 () () (c) FIG. 8.69 Vrious formts for ridge network.

BRIDGE NETWORKS 319 tice network if nd R 4. Fig. 8.69(c) is n excellent exmple of how plnr network cn e mde to pper nonplnr. For the purposes of investigtion, let us exmine the network in Fig. 8.70 using mesh nd nodl nlysis. Mesh nlysis (Fig 8.71) yields (3 )I 1 ()I ()I 3 20 V (5 )I ()I 1 (5 )I 3 0 (5 1 )I 3 ()I 1 (5 )I 0 nd 9I 1 4I 2I 3 20 4I 1 11I 5I 3 0 2I 1 5I 8I 3 0 with the result tht I 1 4 A I 2.67 A I 3 2.67 A The net current through the 5 resistor is I 5 I I 3 2.67 A 2.67 A 0 A Nodl nlysis (Fig. 8.72) yields nd 1 3 1 1 V 1 1 V 1 V 3 20 3 A 1 1 1 5 V 1 V 1 1 5 V 3 0 1 5 1 1 1 V 3 1 V 1 1 5 V 0 1 3 1 1 V 1 1 V 1 V 3 6.67 A 1 V 1 1 1 1 5 V 1 5 V 3 0 1 V 1 1 5 V 1 5 1 1 1 V 3 0 Note the symmetry of the solution. R s 3 R 5 E 20 V 5 R 4 FIG. 8.70 Stndrd ridge configurtion. 1 R s 3 R 1 2 R5 I2 E 20 V I 1 5 R 4 I 3 1 FIG. 8.71 Assigning the mesh currents to the network in Fig. 8.70. V 2 I R s 3 20 3 A V 1 R5 5 R 4 (0 V) 1 FIG. 8.72 Defining the nodl voltges for the network in Fig. 8.70. V 3 TI-89 Clcultor Solution With the TI-89 clcultor, the top prt of the determinnt is determined y the sequence in Fig. 8.73 (tke note of the clcultions within prentheses): det([6.67,1/4,1/2;0,(1/41/21/5),1/5;0,1/5,(1/51/21/1)]) ENTE0.51E0 FIG. 8.73 with the ottom of the determinnt determined y the sequence in Fig. 8.74. det([(1/31/41/2),1/4,1/2;1/4,(1/41/21/5),1/5;1/2,1/5,(1/51/21/1)]) ENTE.31E0 FIG. 8.74

320 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) Finlly, the simple division in Fig. 8.75 provides the desired result. nd V 1 8.02 V 10.51/1.31 ENTER 8.02 R s E 3 20 V V = 0 R 4 1 V 1 FIG. 8.76 Sustituting the short-circuit equivlent for the lnce rm of lnced ridge. R s 3 E 20 V R 4 1 V 1 FIG. 8.77 Redrwing the network in Fig. 8.76. FIG. 8.75 Similrly, V 2.67 V nd V 3 2.67 V nd the voltge cross the 5 resistor is V 5 V V 3 2.67 V 2.67 V 0 V Since V 5 0 V, we cn insert short in plce of the ridge rm without ffecting the network ehvior. (Certinly V IR I(0) 0 V.) In Fig. 8.76, short circuit hs replced the resistor R 5, nd the voltge cross R 4 is to e determined. The network is redrwn in Fig. 8.77, nd 1 7 1 220 V V 1 1voltge divider rule2 1 7 1 1 7 3 2 2 120 V2 120 V2 3 3 2 3 8 3 2 3 4 3 9 3 2120 V2 40 V 2.67 V 9 15 s otined erlier. We found through mesh nlysis tht I 5 0 A, which hs s its equivlent n open circuit s shown in Fig. 8.78(). (Certinly I V/R 0/( ) 0 A.) The voltge cross the resistor R 4 is gin determined nd compred with the result ove. R s E 3 20 V I = 0 R 4 1 V 1 R s E 3 20 V 3 () () FIG. 8.78 Sustituting the open-circuit equivlent for the lnce rm of lnced ridge. The network is redrwn fter comining series elements, s shown in Fig. 8.78(), nd 1 00 3 2120 V2 V 3 00 3 3 120 V2 3 8 V 1 18 V2 nd V 1 1 8 V 2.67 V 3 s ove. The condition V 5 0 V or I 5 0 A exists only for prticulr reltionship etween the resistors of the network. Let us now derive this re-

Y- (T-p) AND -Y (p-t) CONVERSIONS 321 ltionship using the network in Fig. 8.79, in which it is indicted tht I 0 A nd V 0 V. Note tht resistor R s of the network in Fig. 8.78 does not pper in the following nlysis. The ridge network is sid to e lnced when the condition of I 0 A or V 0 V exists. If V 0 V (short circuit etween nd ), then V 1 V 2 R s E V I 1 1 V = 0 I 3 I 2 V 2 V 3 I I = 0 4 R 4V4 nd I 1 I 2 or In ddition, when V 0 V, I 1 I 2 FIG. 8.79 Estlishing the lnce criteri for ridge network. V 3 V 4 nd I 3 I 4 R 4 If we set I 0 A, then I 3 I 1 nd I I 2, with the result tht the ove eqution ecomes I 1 I 2 R 4 Sustituting for I 1 from ove yields or, rerrnging, we hve I 2 I 2 R 4 R 4 (8.2) This conclusion sttes tht if the rtio of to is equl to tht of to R 4, the ridge is lnced, nd I 0 A or V 0 V. A method of memorizing this form is indicted in Fig. 8.80. For the exmple ove,,,, R 1, nd S R 4 1 2 The emphsis in this section hs een on the lnced sitution. Understnd tht if the rtio is not stisfied, there will e potentil drop cross the lnce rm nd current through it. The methods just descried (mesh nd nodl nlysis) will yield ny nd ll potentils or currents desired, just s they did for the lnced sitution. R 4 = R 4 FIG. 8.80 A visul pproch to rememering the lnce condition. 8.12 Y- (T-p) AND -Y (p-t) CONVERSIONS Circuit configurtions re often encountered in which the resistors do not pper to e in series or prllel. Under these conditions, it my e necessry to convert the circuit from one form to nother to solve for ny unknown quntities if mesh or nodl nlysis is not pplied. Two circuit configurtions tht often ccount for these difficulties re the wye (Y) nd delt () configurtions depicted in Fig. 8.81(). They re lso referred to s the tee (T) nd pi (p), respectively, s indicted in Fig. 8.81(). Note tht the pi is ctully n inverted delt. The purpose of this section is to develop the equtions for converting from to Y, or vice vers. This type of conversion normlly leds to

322 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) R C R B R A R B R A R C () () FIG. 8.81 The Y(T) nd (p) configurtions. R C R B c R A FIG. 8.82 Introducing the concept of -Y or Y- conversions. network tht cn e solved using techniques such s those descried in Chpter 7. In other words, in Fig. 8.82, with terminls,, nd c held fst, if the wye (Y) configurtion were desired insted of the inverted delt () configurtion, ll tht would e necessry is direct ppliction of the equtions to e derived. The phrse insted of is emphsized to ensure tht it is understood tht only one of these configurtions is to pper t one time etween the indicted terminls. It is our purpose (referring to Fig. 8.82) to find some expression for,, nd in terms of R A,R B, nd R C, nd vice vers, tht will ensure tht the resistnce etween ny two terminls of the Y configurtion will e the sme with the configurtion inserted in plce of the Y configurtion (nd vice vers). If the two circuits re to e equivlent, the totl resistnce etween ny two terminls must e the sme. Consider terminls -c in the -Y configurtions in Fig. 8.83. R C R C R -c RB R R A -c c Externl to pth of mesurement R -c R B RA c c FIG. 8.83 Finding the resistnce R -c for the Y nd configurtions. Let us first ssume tht we wnt to convert the (R A,R B,R C ) to the Y (,, ). This requires tht we hve reltionship for,, nd in terms of R A,R B, nd R C. If the resistnce is to e the sme etween terminls -c for oth the nd the Y, the following must e true: R -c (Y) R -c () so tht R -c R B 1R A R C 2 R B 1R A R C 2 (8.3)

Y- (T-p) AND -Y (p-t) CONVERSIONS 323 Using the sme pproch for - nd -c, we otin the following reltionships: R - R C 1R A R B 2 R C 1R A R B 2 (8.3) nd R -c R A1R B R C 2 R A 1R B R C 2 (8.3c) Sutrcting Eq. (8.3) from Eq. (8.3), we hve 1 1 R CR B R C R A R A R B R C R BR A R B R A R A R B R C so tht R AR C R B R A R A R B R C (8.3d) Sutrcting Eq. (8.3d) from Eq. (8.3c) yields 1 1 R AR B R A R C R A R B R C R AR C R B R A R A R B R C 2R B R A so tht R A R B R C resulting in the following expression for in terms of R A,R B, nd R C : R A R B R A R B R C (8.4) Following the sme procedure for nd, we hve R B R C R A R B R C (8.4) nd R A R C R A R B R C (8.4c) Note tht ech resistor of the Y is equl to the product of the resistors in the two closest rnches of the divided y the sum of the resistors in the. To otin the reltionships necessry to convert from Y to, first divide Eq. (8.4) y Eq. (8.4): or 1R AR B 2>1R A R B R C 2 1R B R C 2>1R A R B R C R A R C R A R C Then divide Eq. (8.4) y Eq. (8.4c) 1R AR B 2>1R A R B R C 2 1R A R C 2>1R A R B R C R B R C

324 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) or R B R C Sustituting for R A nd R B in Eq. (8.4c) yields 1R C > 2R C 1 R C > 1R C > R C 1 > 2R C 1 > 1 > 1 Plcing these over common denomintor, we otin 1 R C > 2 1 2>1 2 R C nd R C (8.5) We follow the sme procedure for R B nd R A : R A (8.5) nd R B (8.5c) Note tht the vlue of ech resistor of the is equl to the sum of the possile product comintions of the resistnces of the Y divided y the resistnce of the Y frthest from the resistor to e determined. Let us consider wht would occur if ll the vlues of or Y were the sme. If R A R B R C, Eq. (8.4) would ecome (using R A only) the following: R A R B R A R B R C nd, following the sme procedure, R A R A A R A R A R A R A 3R A 3 In generl, therefore, R A 3 R A 3 R Y R 3 (8.6) or R 3R Y (8.6) which indictes tht for Y of three equl resistors, the vlue of ech resistor of the is equl to three times the vlue of ny resistor of the Y. If only two elements of Y or re the sme, the corresponding or Y

Y- (T-p) AND -Y (p-t) CONVERSIONS 325 of ech will lso hve two equl elements. The converting of equtions is left s n exercise for you. The Y nd the often pper s shown in Fig. 8.84. They re then referred to s tee (T) nd pi (p) network, respectively. The equtions used to convert from one form to the other re exctly the sme s those developed for the Y nd trnsformtion. R B 20 R C 10 R A 30 1 3 1 3 R C c c 2 4 2 R B R A 4 FIG. 8.85 Exmple 8.27. () () FIG. 8.84 The reltionship etween the Y nd T configurtions nd the nd p configurtions. 31 /3 5 10 EXAMPLE 8.27 Convert the in Fig. 8.85 to Y. c c Solution: R B R C R A R B R C 120 2110 2 30 20 10 R A R C 130 2110 2 R A R B R C 60 R A R B 120 2130 2 R A R B R C 60 The equivlent network is shown in Fig. 8.86. 300 60 600 60 200 60 5 10 3 1 3 FIG. 8.86 The Y equivlent for the in Fig. 8.85. 60 60 60 EXAMPLE 8.28 Convert the Y in Fig. 8.87 to. c c Solution: R A 160 2160 160 2160 160 2160 2 60 3600 3600 3600 10,800 60 60 R A 180 However, the three resistors for the Y re equl, permitting the use of Eq. (8.6) nd yielding R 3R Y 3(60 ) 180 nd R B R C 180 The equivlent network is shown in Fig. 8.88. c FIG. 8.87 Exmple 8.28. R C 180 R B 180 R A c 180 FIG. 8.88 The equivlent for the Y in Fig. 8.87.

326 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) R T R T R C R B 3 R A c FIG. 8.89 Exmple 8.29. 3 1.5 1.5 0.75 FIG. 8.90 Sustituting the Y equivlent for the ottom in Fig. 8.89. c EXAMPLE 8.29 Find the totl resistnce of the network in Fig. 8.89, where R A 3, R B 3, nd R C. Solution: Two resistors of the D were equl; therefore, two resistors of the Y will e equl. R B R (3 )() 18 C 1.5 RA R B R C 3 3 12 R A R (3 )() 18 C 1.5 RA R B R C 1 12 R (3 )(3 ) 9 A R B 0.75 RA R B R C 1 12 Replcing the y the Y, s shown in Fig. 8.90, yields 11.5 211.5 2 R T 0.75 11.5 11.5 2 15.5 213.5 2 0.75 5.5 3.5 0.75 2.139 R T 2.89 EXAMPLE 8.30 Find the totl resistnce of the network in Fig. 8.91. R T 9 d 9 9 Solutions: Since ll the resistors of the or Y re the sme, Eqs. (8.6) nd (8.6) cn e used to convert either form to the other.. Converting the to Y: Note: When this is done, the resulting d of the new Y will e the sme s the point d shown in the originl figure, only ecuse oth systems re lnced. Tht is, the resistnce in ech rnch of ech system hs the sme vlue: c FIG. 8.91 Exmple 8.30. R Y R (Fig. 8.92) 3 3 The network then ppers s shown in Fig. 8.93. 1219 2 R T 2 c d 3.27 9 9 c c d FIG. 8.92 Converting the configurtion of Fig. 8.91 to Y configurtion. R T c d, d 9 9 FIG. 8.93 Sustituting the Y configurtion for the converted into the network in Fig. 8.91.

APPLICATIONS 327. Converting the Y to : R 3R Y 13219 27 12127 2 16 R T 4.91 27 33 R T R T 1R T R T 2 R T 1R T R T R T2R T 2R T 3R T 3 214.91 2 3.27 3 which checks with the previous solution. (Fig. 8.94) R T c 27 27 27 FIG. 8.94 Sustituting the converted Y configurtion into the network in Fig. 8.91. 8.13 APPLICATIONS This section discusses the constnt current chrcteristic in the design of security systems, the ridge circuit in common residentil smoke detector, nd the nodl voltges of digitl logic proe. Constnt Current Alrm Systems The sic components of n lrm system using constnt current supply re provided in Fig. 8.95. This design is improved over tht provided in Chpter 5 in the sense tht it is less sensitive to chnges in resistnce in the circuit due to heting, humidity, chnges in the length of the line to the sensors, nd so on. The 1.5 k rheostt (totl resistnce etween points nd ) is djusted to ensure current of 5 ma through the singleseries security circuit. The djustle rheostt is necessry to compenste for vritions in the totl resistnce of the circuit introduced y the resistnce of the wire, sensors, sensing rely, nd millimmeter. The millimmeter is included to set the rheostt nd ensure current of 5 ma. Sensing rely Door switch Window foil Mgnetic switch 5 ma 1 k E To ell circuit N/C N/O 5 V @ 5 ma 1 k 10 ma movement Rheostt 0 1.5 k 10 V FIG. 8.95 Constnt current lrm system. If ny of the sensors open, the current through the entire circuit drops to zero, the coil of the rely releses the plunger, nd contct is mde with the N/C position of the rely. This ction completes the circuit for the ell circuit, nd the lrm sounds. For the future, keep in mind tht

328 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) 15 V Door switch 15 V 4 ma R E Window foil Mgnetic switch 2 ma 4 ma R ref 3 15 V 14 4 2 7 Op-Amp LM2900 Constnt R current 1 source Output To lrm ell circuit On pckge to identify pin numers 3 Input 2 Input 0 V () 200 μa 7 () V high R series 7 (c) Dul-in-line pckge V INPUT 3 INPUT 4 INPUT 4 OUTPUT 4 OUTPUT 3 INPUT 3 14 13 12 11 10 9 8 4 2 1 2 3 4 5 6 7 INPUT 1 INPUT 2 INPUT 2 OUTPUT 2 OUTPUT 1 INPUT 1 GND TOP VIEW V 14 V low R low 3 1 4 Output Op-Amp FIG. 8.97 LM2900 opertionl mplifier: () dul-in-line pckge (DIP); () components; (c) impct of low-input impednce. FIG. 8.96 Constnt current lrm system with electronic components. switch positions for rely re lwys shown with no power to the network, resulting in the N/C position in Fig. 8.95. When power is pplied, the switch will hve the position indicted y the dshed line. Tht is, vrious fctors, such s chnge in resistnce of ny of the elements due to heting, humidity, nd so on, cuse the pplied voltge to redistriute itself nd crete sensitive sitution. With n djusted 5 ma, the loding cn chnge, ut the current will lwys e 5 ma nd the chnce of tripping reduced. Note tht the rely is rted s 5 V t 5 ma, indicting tht in the on stte the voltge cross the rely is 5 V nd the current through the rely is 5 ma. Its internl resistnce is therefore 5 V/5 ma 1k in this stte. A more dvnced lrm system using constnt current is illustrted in Fig. 8.96. In this cse, n electronic system using single trnsistor, ising resistors, nd dc ttery re estlishing current of 4 ma through the series sensor circuit connected to the positive side of n opertionl mplifier (op-mp). Trnsistors nd op-mp devices my e new to you (these re discussed in detil in electronics courses), ut for now you just need to know tht the trnsistor in this ppliction is eing used not s n mplifier ut s prt of design to estlish constnt current through the circuit. The op-mp is very useful component of numerous electronic systems, nd it hs importnt terminl chrcteristics estlished y vriety of components internl to its design. The LM2900 opertionl mplifier in Fig. 8.96 is one of four found in the dul-in-line integrted circuit pckge ppering in Fig. 8.97(). Pins 2, 3, 4, 7, nd 14 were used for the design in Fig. 8.96. Note in Fig. 8.97() the numer of elements required to estlish the desired terminl chrcteristics the detils of which will e investigted in your electronics courses. In Fig. 8.96, the designed 15 V dc supply, ising resistors, nd trnsistor in the upper right corner of the schemtic estlish constnt 4 ma current through the circuit. It is referred to s constnt current source ecuse the current remins firly constnt t 4 ma even though there my e moderte vritions in the totl resistnce of the series sensor circuit connected to the trnsistor. Following the 4 ma through the circuit, we find tht it enters terminl 2 (positive side of the input) of the op-mp. A second current of 2 ma, clled the reference current, is estlished y the 15 V source nd resistnce R nd enters terminl 3 (negtive side of the input) of the op-mp. The reference current of 2 ma is necessry to estlish current for the 4 ma current of the network to e compred ginst. As long s the 4 ma current exists, the opertionl

APPLICATIONS 329 mplifier provides high output voltge tht exceeds 13.5 V, with typicl level of 14.2 V (ccording to the specifiction sheet for the opmp). However, if the sensor current drops from 4 ma to level elow the reference level of 2 ma, the op-mp responds with low output voltge tht is typiclly out 0.1 V. The output of the opertionl mplifier then signls the lrm circuit out the disturnce. Note from the ove tht it is not necessry for the sensor current to drop to 0 ma to signl the lrm circuit just vrition round the reference level tht ppers unusul. One very importnt chrcteristic of this prticulr op-mp is tht the input impednce to the op-mp is reltively low. This feture is importnt ecuse you don t wnt lrm circuits recting to every voltge spike or turulence tht comes down the line ecuse of externl switching ction or outside forces such s lightning. In Fig. 8.97(c), for instnce, if high voltge should pper t the input to the series configurtion, most of the voltge will e sored y the series resistnce of the sensor circuit rther thn trveling cross the input terminls of the opertionl mplifier thus preventing flse output nd n ctivtion of the lrm. Whetstone Bridge Smoke Detector The Whetstone ridge is populr network configurtion whenever detection of smll chnges in quntity is required. In Fig. 8.98(), the dc ridge configurtion uses photoelectric device to detect the presence of smoke nd to sound the lrm. A photogrph of n ctul photoelectric smoke detector ppers in Fig. 8.98(), nd the internl construction of the unit is shown in Fig. 8.98(c). First, note tht ir vents re provided to permit the smoke to enter the chmer elow the cler plstic. The cler plstic prevents the smoke from entering the upper chmer ut permits the light from the ul in the upper chmer to ounce off the lower reflector to the semiconductor light sensor ( cdmium photocell) t the left side of the chmer. The cler plstic seprtion ensures tht the light hitting the light sensor in the upper chmer is not ffected y the entering smoke. It estlishes reference level to compre ginst the chmer with the entering smoke. If no smoke is present, the difference in response etween the sensor cells will e registered s the norml sitution. Of course, if oth cells were exctly identicl, nd if the cler plstic did not cut down on the light, oth sensors would estlish the sme reference level, nd their difference would e zero. However, this is seldom the cse, so reference difference is recognized s the sign tht smoke is not present. However, once smoke is present, there will e shrp difference in the sensor rection from the norm, nd the lrm should sound. In Fig. 8.98(), we find tht the two sensors re locted on opposite rms of the ridge. With no smoke present, the lnce-djust rheostt is used to ensure tht the voltge V etween points nd is zero volts nd the resulting current through the primry of the sensitive rely is zero mperes. Tking look t the rely, we find tht the sence of voltge from to leves the rely coil unenergized nd the switch in the N/O position (recll tht the position of rely switch is lwys drwn in the unenergized stte). An unlnced sitution results in voltge cross the coil nd ctivtion of the rely, nd the switch moves to the N/C position to complete the lrm circuit nd ctivte the lrm. Relys with two contcts nd one movle rm re clled single-poledoule-throw (SPDT) relys. The dc power is required to set up the lnced sitution, energize

330 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) Blnce djust R lnce Smoke detector Lmp DC power V lnce Test module socket LED (light-emitting diode) R Reference Sensitive rely N/C N/O To lrm circuit Screen Recessed test switch () () Ceiling Reflector Reference cell Photoconductive cells (Resistnce function of pplied light) Seled chmer Solid rrier Light source Cler plstic Smoke detector Reflector Room Vents for the pssge of ir or smoke FIG. 8.98 Whetstone ridge smoke detector: () dc ridge configurtion; () outside ppernce; (c) internl construction. (c) the prllel ul so we know tht the system is on, nd provide the voltge from to if n unlnced sitution should develop. Why do you suppose only one sensor isn t used since its resistnce would e sensitive to the presence of smoke? The nswer is tht the smoke detector my generte flse redout if the supply voltge or output light intensity of the ul should vry. Smoke detectors of the type just descried must e used in gs sttions, kitchens, dentist offices, etc., where the rnge of gs fumes present my set off n ionizing type smoke detector. Schemtic with Nodl Voltges When n investigtor is presented with system tht is down or not operting properly, one of the first options is to check the system s specified voltges on the schemtic. These specified voltge levels re ctully the

APPLICATIONS 331 5.5 V 1.8 V 1.5 V 1.2 V R 4 6.8 k 560 R 5 1 M 560 2.2 k 5.5 V U2A 3 4 LM324 1 2 11 High 5.5 V 5 4 U2B Low LM324 6 11 7 LED 1 Red R 7 1.2 k LED 2 Green 5.5 V () R 6 10 k TP LOGIC IN 5.5 V 6.8 k 1.8 V 1 560 R 5 1.5 V 1 M 560 1.2 V 1 R 4 2.2 k 1 1 1 1 5.5 V U2A 3 4 LM324 1 2 11 High 5.5 V 5 4 U2B Low LM324 6 11 7 LED 1 Red R 7 1.2 k LED 2 Green Printed circuit ord 5.5 V LEDs IC Resistors Cpcitors (c) IC () R 6 10 k TP LOGIC IN FIG. 8.99 Logic proe: () schemtic with nodl voltges; () network with glol connections; (c) photogrph of commercilly ville unit. nodl voltges determined in this chpter. Nodl voltge is simply specil term for voltge mesured from tht point to ground. The technicin ttches the negtive or lower-potentil led to the ground of the network (often the chssis) nd then plces the positive or higher-potentil led on the specified points of the network to check the nodl voltges. If they mtch, it mens tht section of the system is operting properly. If one or more fil to mtch the given vlues, the prolem re cn usully e identified. Be wre tht reding of 15.87 V is significntly different from n expected reding of 16 V if the leds hve een properly ttched. Although the ctul numers seem close, the difference is ctully more thn 30 V. You must expect some devition from the given vlue s shown, ut lwys e very sensitive to the resulting sign of the reding. The schemtic in Fig. 8.99() includes the nodl voltges for logic proe used to mesure the input nd output sttes of integrted circuit logic chips. In other words, the proe determines whether the mesured voltge is one of two sttes: high or low (often referred to s on or off or 1 or 0). If the LOGIC IN terminl of the proe is plced on chip t loction where the voltge is etween 0 nd 1.2 V, the voltge

332 METHODS OF ANALYSIS AND SELECTED TOPICS (dc) is considered to e low level, nd the green LED lights. (LEDs re lightemitting semiconductor diodes tht emit light when current is pssed through them.) If the mesured voltge is etween 1.8 V nd 5 V, the reding is considered high, nd the red LED lights. Any voltge etween 1.2 V nd 1.8 V is considered floting level nd is n indiction tht the system eing mesured is not operting correctly. Note tht the reference levels mentioned ove re estlished y the voltge divider network to the left of the schemtic. The op-mps used re of such high input impednce tht their loding on the voltge divider network cn e ignored nd the voltge divider network considered network unto itself. Even though three 5.5 V dc supply voltges re indicted on the digrm, e wre tht ll three points re connected to the sme supply. The other voltges provided (the nodl voltges) re the voltge levels tht should e present from tht point to ground if the system is working properly. The op-mps re used to sense the difference etween the reference t points 3 nd 6 nd the voltge picked up in LOGIC IN. Any difference results in n output tht lights either the green or the red LED. Be wre, ecuse of the direct connection, tht the voltge t point 3 is the sme s shown y the nodl voltge to the left, or 1.8 V. Likewise, the voltge t point 6 is 1.2 V for comprison with the voltges t points 5 nd 2, which reflect the mesured voltge. If the input voltge hppened to e 1.0 V, the difference etween the voltges t points 5 nd 6 would e 0.2 V, which idelly would pper t point 7. This low potentil t point 7 would result in current flowing from the much higher 5.5 V dc supply through the green LED, cusing it to light nd indicting low condition. By the wy, LEDs, like diodes, permit current through them only in the direction of the rrow in the symol. Also note tht the voltge t point 6 must e higher thn tht t point 5 for the output to turn on the LED. The sme is true for point 2 over point 3, which revels why the red LED does not light when the 1.0 V level is mesured. Often it is imprcticl to drw the full network s shown in Fig. 8.99() ecuse there re spce limittions or ecuse the sme voltge divider network is used to supply other prts of the system. In such cses, you should recognize tht points hving the sme shpe re connected, nd the numer in the figure revels how mny connections re mde to tht point. A photogrph of the outside nd inside of commercilly ville logic proe is shown in Fig. 8.99(c). Note the incresed complexity of system ecuse of the vriety of functions tht the proe cn perform. 8.14 COMPUTER ANALYSIS PSpice We will now nlyze the ridge network in Fig. 8.72 using PSpice to ensure tht it is in the lnced stte. The only component tht hs not een introduced in erlier chpters is the dc current source. To otin it, first select the Plce prt key nd then the SOURCE lirry. Scrolling the Prt List results in the option IDC. A left click of IDC followed y OK results in dc current source whose direction is towrd the ottom of the screen. One left click (to mke it red, or ctive) followed y right click results in listing hving Mirror Verticlly option. Selecting tht option flips the source nd gives it the direction in Fig. 8.72. The remining prts of the PSpice nlysis re pretty strightforwrd, with the results in Fig. 8.100 mtching those otined in the nlysis of Fig. 8.72. The voltge cross the current source is 8 V positive to ground, nd the voltge t either end of the ridge rm is 2.667 V. The voltge

COMPUTER ANALYSIS 333 FIG. 8.100 Applying PSpice to the ridge network in Fig. 8.72. cross R 5 is oviously 0 V for the level of ccurcy displyed, nd the current is such smll mgnitude compred to the other current levels of the network tht it cn essentilly e considered 0 A. Note lso for the lnced ridge tht the current through equls tht of, nd the current through equls tht of R 4. Multisim We will now use Multisim to verify the results in Exmple 8.18. All the elements of creting the schemtic in Fig. 8.101 hve een presented in erlier - A 1.220 3.699 V 2.800 - V FIG. 8.101 Using Multisim to verify the results in Exmple 8.18.