Task 1. Exercises: Logical Design of Digital Systems Seite: 1 Self Study (Boolean Algebra, combinational circuits) 1.1 Minimize the function f 1 a ab ab by the help of Boolean algebra and give an implementation of the minimized function Consider now the function y = abd + c acd b 1.2 Write the function y in complete disjunctive normal form by A: application of boolean algebra B: Usage of truth table 1.3 Minimize the function f 2 c bd bd ac b d cd a b ad b c ab KV-map by application of a Task 2. 2.1 Describe BCD-, Aiken-, Gray- and excess-3 code 2.2 Add the ternary numbers (B=3) N 1 = 12021,202 N 2 = 2110,2 (Binary Codes and -arithmetics) 2.3 Multiply N 1 2 = I I 0 I, 0 I N 2 2 = I I 0, I Task 3. (Flip Flops) 3.1 Determine the characteristic equation of a D-Flip Flop and a JK-Flip Flop. 3.2 How must a JK flip-flop be switched to turn it into a D flip-flop? Task 4. Given the following sequential circuit (automaton): (State machines) 4.1 what type of state machine is it? (Give reason) 4.2 determine the coded state table for this circuit. 4.3 determine the general (non-coded) state table for this circuit. 4.4 minimise the state table.
Exercises: Logical Design of Digital Systems Seite: 2 Task 5. A multiplication circuit is to be designed for processing 4-bit digits. 5.1 Multiply the two numbers 7 and 3 using the binary number system. Show your calculations and formulate ideas for a technical solution. 5.2 What happens with negative multiplicands (MD)? 5.3 Formulate an algorithm for the technical realization of the multiplication. 5.4 Discuss the steps needed to realize the processing unit. A sequential circuit to control the processing unit is now to be designed. 5.5 Give the impulse diagram of the inputs to the processing unit 5.6 Determine the state table of a state machine that generates the signals with regards to the impulse diagram. Now use D-Flip Flops for the realization of the circuit. 5.7 Determine the equations for the inputs of the D-Flip Flops as well as for the outputs of the circuit. 5.8 Show the technical realization of the circuit.
Exercises: Logical Design of Digital Systems Seite: 3 Construction sheet for task 5.3
Exercises: Logical Design of Digital Systems Seite: 4 Construction sheet for task 5.4
Exercises: Logical Design of Digital Systems Seite: 5 Construction Sheet for task 5.5 Clk
Exercises: Logical Design of Digital Systems Seite: 6 Task 6. 8-bit data words from input D[1:8] are to be stored in 8-bit registers using a bus structure. The following elements are available for building the circuit: the bus lines D1 to D8, decoder, type 74 LS 139, for controlling the clock and output control lines of the registers. edge-controlled D flip-flops in 8-bit register form (74 LS 374) with tri-state outputs Function Table Function Table 74LS139 (Decoder) 74LS374 (Register) INPUT OUTPUT OUTPUT ENABLE SELECT CONTROL CLOCK D OUTPUT G B A Y0 Y1 Y2 Y3 I X X I I I I 0 I I 0 0 0 0 I I I 0 0 0 0 0 I I 0 I I 0 0 X Q n 0 I 0 I I 0 I I X X Z 0 I I I I I 0 6.1 Discuss the 74 LS 139 function table and suggest a possible circuit solution. 6.2 Discuss the function of a tri-state output. Show the switching states of the output transistors for the various possible output levels. 6.3 Discuss the 74 LS 374 function table. The following problem is now to be solved using the given bus structure: Phase 1: Phase 2: Phase 3: Phase 4: The data word I I I I 0 0 0 0 is to be stored in IC1. The data word I 0 I 0 I 0 I 0 is to be stored in IC4. The contents of IC1 is to be transferred to IC3. The contents of IC4 is to be transferred to IC2. 6.4 Complete the circuit shown in figure 6.1 for this problem. 6.5 Explain the impulse diagram shown in figure 6.2.
Exercises: Logical Design of Digital Systems Seite: 7 74 LS 139 74 LS 374 A1 B1 C1 Y0 Y1 Y2 Y3 OC CLK OC CLK IC1 IC2 A2 B2 G2 clock Y0 Y1 Y2 Y3 OC CLK OC CLK IC3 IC4 D[1,8] Figure 6.1 Figure 6.2
Exercises: Logical Design of Digital Systems Seite: 8 Task 7. Given are the two memory structures in figure 7.1. 64 x 4 64 x 4 A 0 A 0 A 1 A 1 A 2 A 3 A 4 A 5 CS A 0 63 I/O 0 I/O 1 I/O 2 I/O 3 A 2 A 3 A 4 A 5 CS A 0 63 I/O 0 I/O 1 I/O 2 I/O 3 WE a.) b.) Figure 7.1 7.1 Identify the ROM and the RAM in figure 7.1 and characterize them. 7.2 Determine the truth table for the ROM given in figure 7.2 0 A 0 A 1 A 2 1 2 3 4 5 6 7 O1 O2 O3 O4 7.3 Design a 1-bit full adder using a ROM. Figure 7.2
Exercises: Logical Design of Digital Systems Seite: 9 Task 8. A micro-programmed state machine shall be realized using a ROM. When triggered by a binary control signal X the state machine shall realise an Aiken-code ring counter (X=0) or a BCD-code ring counter (X=1). In both cases, the states are to be addressed in Aiken code. 8.1 What is the minimum size of the ROM (memory cells, word length)? 8.2 Show the respective state machine circuit a.) for a state machine of Mealy type b.) for a state machine of Moore type. 8.3 How must the ROM be programmed? (Explain the program given below.) 8.4 Determine the coded state transition table for a Mealy type. 8.5 Give the state transition diagram for a Mealy type. 8.6 Can the ROM size be minimised any further? 0 0 0 0 0 0 0 0 I 0 0 0 0 0 0 0 0 I 0 0 I 0 0 0 0 I 0 0 0 I 0 0 0 I I 0 0 I 0 0 0 0 I I 0 I 0 0 0 0 I I 0 0 I 0 0 I 0 I I 0 I 0 0 0 0 I 0 I - - - - - - - - 0 0 I I 0 - - - - - - - - 0 0 I I I - - - - - - - - 0 I 0 0 0 - - - - - - - - 0 I 0 0 I - - - - - - - - 0 I 0 I 0 - - - - - - - - 0 I 0 I I I I 0 0 I 0 I I 0 I I 0 0 I I 0 I I I 0 0 0 I I 0 I I I I 0 I I 0 I 0 I I I 0 I I I I I I I 0 0 I I I I 0 0 0 0 I I I I I 0 0 0 0 0 0 0 I 0 0 0 0 I 0 0 0 I 0 0 I 0 0 0 0 I I 0 0 I 0 0 0 I I 0 0 I 0 I 0 0 I I 0 I 0 0 0 0 I I I 0 I 0 0 I 0 I I 0 I 0 0 I 0 I 0 I - - - - - - - - I 0 I I 0 - - - - - - - - I 0 I I I - - - - - - - - I I 0 0 0 - - - - - - - - I I 0 0 I - - - - - - - - I I 0 I 0 - - - - - - - - I I 0 I I I I 0 0 0 I 0 I I I I 0 0 I I 0 I 0 I I 0 I I I 0 I I I I 0 0 I I I I I I I 0 I I I I I 0 0 0 I I I I I 0 0 0 0 I 0 0 I Construction Sheet Task 8
Task 9. Exercises: Logical Design of Digital Systems Seite: 10 Given is the following PLA with two D Flip Flops in its feedback line (figure 9.1a) and the corresponding program scheme (figure 9.1b). a.) PLA Figure 9.1 b.) Program Scheme 9.1 Determine the logical expressions for the outputs and the state variables 9.2 Determine the state transition table 9.3 Of what type of state machine is the given circuit? 9.4 Give the state transition diagram
Exercises: Logical Design of Digital Systems Seite: 11 Task 10. Design a circuit that converts a 4-bit binary number to a hexadecimal digit and outputs the 7- bit ASCII code for the hexadecimal digit with a PAL 12H6. 10.1 Characterize the PAL 12H6 figure 10: PAL 12H6 10.2 Give the truth table for the described problem and read the output functions from the truth table. 10.3 Minimize the output functions with a KV-Map 10.4 Generate the output functions with the PAL12H6.
Exercises: Logical Design of Digital Systems Seite: 12 Construction sheets Task 10 ASCII Code Table W X II00 C III0 E II0I D IIII F 0I0I 5 0III 7 0I00 4 0II0 6 I0I0 A I0II B 00II 3 00I0 2 Y I000 8 I00I 9 000I 1 0000 0 Z Input Hex ASCII Code for Hex Digit W X Y Z Digit A 6 A 5 A 4 A 3 A 2 A 1 A 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 0 2 0 1 1 0 0 1 0 0 0 1 1 3 0 1 1 0 0 1 1 0 1 0 0 4 0 1 1 0 1 0 0 0 1 0 1 5 0 1 1 0 1 0 1 0 1 1 0 6 0 1 1 0 1 1 0 0 1 1 1 7 0 1 1 0 1 1 1 1 0 0 0 8 0 1 1 1 0 0 0 1 0 0 1 9 0 1 1 1 0 0 1 1 0 1 0 A 1 0 0 0 0 0 1 1 0 1 1 B 1 0 0 0 0 1 0 1 1 0 0 C 1 0 0 0 0 1 1 1 1 0 1 D 1 0 0 0 1 0 0 1 1 1 0 E 1 0 0 0 1 0 1 1 1 1 1 F 1 0 0 0 1 1 0
Exercises: Logical Design of Digital Systems Seite: 13 Task 11. The state machine in figure 11 consists of four different states, where state Z1 is the starting state. The state transitions according to the assigned input values can be read from figure 11. The resulting output combinations are given in table 11. Zustand Z1 Z2 Z3 Z4 Ausgang Ai={Yo,Y1,Y2} A1={010} A2={100} A3={110} A4={011} X1 X0 1 0 1 1 00 Z1/A1 01 10 11 Z2/A2 00 11 10 Z4/A4 Z3/A3 10 00 01 Table 11 Figure 11 State transition graph 11.1 Which type of state machine is given by the state machine in figure 11/table 11? Now a third input variable x2 shall control a fifth state Z5. If x2=0, the state machine transits to state Z5 and remains in Z5 as long as x2=0. As long as the state machine is in Z5, all output variables are to be set to 0. The state machine remains in Z5 independent from the values of x0 and x1 till x2=i. In this case the state machine returns to the starting state. 11.2 Complete figure 11 and table 11 for the above described requirements. 11.3 How many flip flops are needed to realize the state machine described in 11.2? 11.4 Give the uncoded state transition table. 11.5 Code the state transition table and derive the flip flop equations for a realization with D-Flip- Flops.
Exercises: Logical Design of Digital Systems Seite: 14 Now the state machine shall be realized by the usage of a PAL 16R4 device. 11.6 What are the differences between PALs und FPLAs? 11.7 Give the specification of a PAL 16R4 circuit? 11.8 Derive the equations for the outputs Y0, Y1, und Y2 here. 11.9 Realize the state machine with a PAL 16R4.
Exercises: Logical Design of Digital Systems Seite: 15 Construction sheet Aufgabe 11 Table 1 Input {x 2, x 1, x 0 } States 000 001 010 011 100 101 110 111 Output Z 1 A1 Z 2 A2 Z 3 A3 Z 4 A4 A5 Z 5 Table 2 States Input {x 2, x 1, x 0 } Output Q 2 Q 1 Q 0 000 001 010 011 100 101 110 111 {y 2,y 1,y 0 } 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1
Exercises: Logical Design of Digital Systems Seite: 16 Construction sheet Tabelle 1 Eingänge {x 2, x 1, x 0 } Zustände 000 001 010 011 100 101 110 111 Ausgabe Z 1 Z 5 Z 5 Z 5 Z 5 Z 1 Z 4 Z 4 --- A1 Z 2 Z 5 Z 5 Z 5 Z 5 --- --- Z 2 Z 1 A2 Z 3 Z 5 Z 5 Z 5 Z 5 Z 2 --- Z 3 Z 2 A3 Z 4 Z 5 Z 5 Z 5 Z 5 Z 3 Z 3 Z 1 Z 1 A4 Z 5 Z 5 Z 5 Z 5 Z 5 Z 1 Z 1 Z 1 Z 1 A5 Tabelle 2 Zustände Eingänge {x 2, x 1, x 0 } Ausgabe Q 2 Q 1 Q 0 000 001 010 011 100 101 110 111 {y 2,y 1,y 0 } 0 0 0 101 101 101 101 000 100 100 --- 010 0 0 1 101 101 101 101 --- --- 001 000 001 0 1 0 101 101 101 101 001 --- 010 001 011 1 0 0 101 101 101 101 010 010 000 000 110 1 0 1 101 101 101 101 000 000 000 000 000 Tabelle 3 Q x x x x Q Q Q x x x Q Q Q x x x Q Q Q 0 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 Q x x x Q Q Q x x x Q Q Q x x x Q Q Q 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 x x x Q Q Q x x Q Q Q 0 1 2 0 1 2 1 2 0 1 2 Q x x x x Q Q Q x x x Q Q Q 2 2 0 1 2 0 1 2 0 1 2 0 1 2 y0 Q0Q 1Q2 Q0Q 1Q2 y1 Q0Q 2 Q0Q 1 y2 Q0Q 1Q2
Exercises: Logical Design of Digital Systems Seite: 17 Task 12. Minimize the function f(a,b,c,d)= m(2,3,7,9,11,13) + d(1,10,15) with the Quine-McCluskey Approach Task 13. Given is the following prime implicant chart m0 m2 m3 m5 m7 m9 m11 m13 m14 m16 m18 m24 m26 m28 m30 p1 X X X X p2 X X X X p3 X X X X p4 X X p5 X X p6 X X p7 X X p8 X X p9 X X p10 X X p11 X X Find a solution for the given problem Construction table Task 14. Given is the function f1(a,b,c,d): f1 (A, B, C,D) ABCD ABCD ABCD ABCD ABCD ABCD ABCD 14.1 Minimize f1(a,b,c,d) with the Quine-McCluskey approach. 14.2 Determine Petricks expression and discuss the resulting solutions.
Exercises: Logical Design of Digital Systems Seite: 18 Task 15. Given is the following state machine table in out Z a b c Y 1 2 2 5 1 2 1 4 4 0 3 2 2 5 1 4 3 2 2 0 5 6 4 3 3 6 8 9 6 0 7 9 7 2 3 8 4 4 7 1 9 7 9 4 3 10 7 2 8 2 Table 15.1 15.1 What type of state machine is described by table 15.1 15.2 Give the state transition diagram 15.3 Minimize the state machine given by table 15.1. 15.4 Describe the minimized state machine as a Mealy-Machine 15.5 Derive all necessary equations to implement the Mealy-Machine
Exercises: Logical Design of Digital Systems Seite: 19 Task 16. Given is the following sequential circuit. Figure 16 16.1 Analyze the sequential circuit in Figure 16 by determining the state transition table 16.2 Enhance the circuit by adding a reset line, so that the states of all flip-flops can be reset to 0
Exercises: Logical Design of Digital Systems Seite: 20 Task 17. Given is the logical circuit shown in figure 17. Figure 17 17.1 Derive the logical function of the circuit 17.2 Derive the minimum test pattern set to identify all possible stuck-at faults of the circuit Construction sheet task 17 c b a f0 f1 f2 f3 f4 f5 f6 f8 f9 f11 f16 t0 0 0 0 I 0 I 0 I I I I I I 0 t1 0 0 I 0 0 I 0 0 0 0 0 I 0 t2 0 I 0 0 0 0 0 I I 0 I 0 I 0 t3 0 I I 0 0 0 0 0 I 0 0 0 I 0 t4 I 0 0 I 0 I I I I I I I I 0 t5 I 0 I 0 0 I I 0 0 I I 0 t6 I I 0 I I I I I I 0 I I I 0 t7 I I I I I I I 0 I 0 I I I 0
Exercises: Logical Design of Digital Systems Seite: 21 Task 18. Given is the combinatorial circuit in figure 18. Figure 18 18.1 Derive the minimum test pattern set for all possible stuck-at faults at the primary inputs by applying the Boolean difference. 18.2 For which stuck at faults inside the circuit are these test pattern applicable? 18.3 Expand the minimum test pattern set so that stuck at faults at nodes e, f and y can be recognized Task 19. Given is the combinatorial circuit in figure 19. Figure 19 19.1 Derive test pattern for the stuck at faults at node h with the Boolean difference.
Exercises: Logical Design of Digital Systems Seite: 22 Task 20. For the circuit shown in figure 20 a test for the stuck-at-1 fault at node a shall be constructed. 20.1 Derive a suitable test pattern, which creates a sensitized path from node a to node y 20.2 Which other faults can be recognized with this test pattern? Figure 20 Task 21. Given is the circuit shown in figure 21 a b G1 & h G3 G5 = 1 c d e f g G2 > 1 i & G4 & j k G6 & m G7 > 1 n G8 & y Figure 21 21.1 Derive a test pattern for stuck-at-1 faults at node i by applying the D-Algorithm 21.2 In which logical state is output node y in the a.) fault free case b.) fault case
Task 22. Exercises: Logical Design of Digital Systems Seite: 23 Bild 17 22.1 Derive the combinatorial controllability of all nodes by applying the SCOAP-Algorithm 22.2 Derive the combinatorial observability of all nodes by applying the SCOAP-Algorithm