Low Power Quint Exclusive OR/NOR Gate

Similar documents
DM7417 Hex Buffers with High Voltage Open-Collector Outputs

DM7404 Hex Inverting Gates

CD4028BC BCD-to-Decimal Decoder

DM Quad 2-Input NAND Buffers with Open-Collector Outputs

CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

DM74LS02 Quad 2-Input NOR Gate

DM74LS08 Quad 2-Input AND Gates

MM74HC32 Quad 2-Input OR Gate

MM74HC00 Quad 2-Input NAND Gate

MM74HC08 Quad 2-Input AND Gate

DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs

CD40106BC Hex Schmitt Trigger

DM74LS05 Hex Inverters with Open-Collector Outputs

MM74HC154 4-to-16 Line Decoder

DM74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Connection Diagram. Logic Diagram. Function Table (Each Latch)

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

MM74HC244 Octal 3-STATE Buffer

CD4028BC BCD-to-Decimal Decoder

MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter

MM74HC251 8-Channel 3-STATE Multiplexer

MM74C906 Hex Open Drain N-Channel Buffers

MM74C14 Hex Schmitt Trigger

MM74HC175 Quad D-Type Flip-Flop With Clear

CD4024BC 7-Stage Ripple Carry Binary Counter

MM74HCT08 Quad 2-Input AND Gate

CD4013BC Dual D-Type Flip-Flop

MM74HC139 Dual 2-To-4 Line Decoder

MM74HC373 3-STATE Octal D-Type Latch

MM74HC138 3-to-8 Line Decoder

MM74C14 Hex Schmitt Trigger

MM74HC373 3-STATE Octal D-Type Latch

MM74HCT138 3-to-8 Line Decoder

CD4093BC Quad 2-Input NAND Schmitt Trigger

MM74HC74A Dual D-Type Flip-Flop with Preset and Clear

CD4049UBC CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer

MM74HC573 3-STATE Octal D-Type Latch

MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

CD4021BC 8-Stage Static Shift Register

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register

MM74HC374 3-STATE Octal D-Type Flip-Flop

74F30 8-Input NAND Gate

74F139 Dual 1-of-4 Decoder/Demultiplexer

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop


74AC08 74ACT08 Quad 2-Input AND Gate


DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver

CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders

CD4528BC Dual Monostable Multivibrator

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

74VHC00 Quad 2-Input NAND Gate

74VHC00 Quad 2-Input NAND Gate

74F153 Dual 4-Input Multiplexer

DM Bit Addressable Latch

MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder

DM74LS670 3-STATE 4-by-4 Register File

DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

MM74HCT540 MM74HCT541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer

74F537 1-of-10 Decoder with 3-STATE Outputs

74F109 Dual JK Positive Edge-Triggered Flip-Flop

MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

MM74C908 Dual CMOS 30-Volt Relay Driver

74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear

MM74C85 4-Bit Magnitude Comparator

74F174 Hex D-Type Flip-Flop with Master Reset

74F194 4-Bit Bidirectional Universal Shift Register

74F175 Quad D-Type Flip-Flop

74AC153 74ACT153 Dual 4-Input Multiplexer

DM7490A Decade and Binary Counter

74F240 74F241 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs

MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

74F379 Quad Parallel Register with Enable

74AC138 74ACT138 1-of-8 Decoder/Demultiplexer

74ACT825 8-Bit D-Type Flip-Flop

DM74LS240 DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver

74F283 4-Bit Binary Full Adder with Fast Carry

74VHC244 Octal Buffer/Line Driver with 3-STATE Outputs

Excellent Integrated System Limited

MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop

CD4511BC BCD-to-7 Segment Latch/Decoder/Driver

74F539 Dual 1-of-4 Decoder with 3-STATE Outputs

Excellent Integrated System Limited

MM82C19 16-Line to 1-Line Multiplexer

NC7SVU04 TinyLogic ULP-A Unbuffered Inverter

74FR74 74FR1074 Dual D-Type Flip-Flop

74VHC138 3-to-8 Decoder/Demultiplexer


74VHC139 Dual 2-to-4 Decoder/Demultiplexer

FIN1531 5V LVDS 4-Bit High Speed Differential Driver

NC7SV11 TinyLogic ULP-A 3-Input AND Gate

DM7446A, DM7447A BCD to 7-Segment Decoders/Drivers

Transcription:

100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-or/nor gate. The Function output is the wire-or of all five exclusive-or outputs. All inputs have 50 kω pull-down resistors. Ordering Code: Features August 1989 Revised August 2000 Low Power Operation 2000V ESD protection Pin/function compatible with 100107 Voltage compensated operating range = 4.2V to 5.7V Available to industrial grade temperature range (PLCC package only) Order Number Package Number Package Description 1000307PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 1000307QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 1000307QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range ( 40 C to +85 C) Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Connection Diagrams 100307 Low Power Quint Exclusive OR/NOR Gate 24-Pin DIP Pin Descriptions Pin Names D na D ne F O a O e O a O e Logic Equation Description Data Inputs Function Output Data Outputs Complementary Data Outputs 28-Pin PLCC F = (D 1a D 2a ) + (D 1b D 2b ) + (D 1c D 2c ) + (D 1d D 2d ) + (D 1e D 2e ). 2000 Fairchild Semiconductor Corporation DS010582 www.fairchildsemi.com

100307 Absolute Maximum Ratings(Note 1) Storage Temperature (T STG ) 65 C to +150 C Maximum Junction Temperature (T J ) +150 C V EE Pin Potential to Ground Pin 7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) 50 ma ESD (Note 2) 2000V Commercial Version Recommended Operating Case Temperature (T C ) Commercial 0 C to +85 C Industrial 40 C to +85 C Supply Voltage (V EE ) 5.7V to 4.2V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. the parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The Recommended Operating table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. DC Electrical Characteristics (Note 3) V EE = 4.2V to 5.7V, V CC = V CCA = GND, T C = 0 C to +85 C Min Typ Max V OH Output HIGH Voltage 1025 955 870 mv V IN =V IH (Max) Loading with V OL Output LOW Voltage 1830 1705 1620 mv or V IL (Min) 50Ω to 2.0V V OHC Output HIGH Voltage 1035 mv V IN = V IH (Min) Loading with V OLC Output LOW Voltage 1610 mv or V IL (Max) 50Ω to 2.0V V IH Input HIGH Voltage 1165 870 mv Guaranteed HIGH Signal for All Inputs V IL Input LOW Voltage 1830 1475 mv Guaranteed LOW Signal for All Inputs I IL Input LOW Current 0.50 µa V IN = V IL (Min) I IH Input HIGH Current D 2a D 2e 250 µa V IN = V IH (Max) D 1a D 1e 350 I EE Power Supply Current 69 43 30 ma Inputs Open Note 3: The specified limits represent the worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. for testing shown in the tables are chosen to guarantee operation under worst case conditions. DIP AC Electrical Characteristics V EE = 4.2V to 5.7V, V CC = V CCA = GND T C = 0 C T C = +25 C T C = +85 C Min Max Min Max Min Max t PHL D 2a D 2e to O, O 0.55 1.90 0.55 1.80 0.55 1.90 ns 0.55 1.70 0.55 1.60 0.55 1.70 ns t PHL D 1a D 1e to O, O Figures 1, 2 t PHL Data to F 1.15 2.75 1.15 2.75 1.15 3.00 ns t TLH Transition Time t THL 20% to 80%, 80% to 20% 0.35 1.20 0.35 1.20 0.35 1.20 ns www.fairchildsemi.com 2

Commercial Version (Continued) PLCC AC Electrical Characteristics V EE = 4.2V to 5.7V, V CC = V CCA = GND t PHL D 2a D 2e to O, O t PHL D 1a D 1e to O, O t PHL Data to F t TLH Transition Time t THL 20% to 80%, 80% to 20% T C = 0 C T C = +25 C T C = +85 C Min Max Min Max Min Max 0.55 1.70 0.55 1.60 0.55 1.70 ns 0.55 1.50 0.55 1.40 0.55 1.50 ns 1.15 2.55 1.15 2.55 1.15 2.80 ns 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2 100307 Industrial Version PLCC DC Electrical Characteristics (Note 4) V EE = 4.2V to 5.7V, V CC = V CCA = GND, T C = 40 C to +85 C T C = 40 C T C = 0 C to +85 C Min Max Min Max V OH Output HIGH Voltage 1085 870 1025 870 mv V IN = V IH(Max) Loading with V OL Output LOW Voltage 1830 1575 1830 1620 mv or V IL(Min) 50Ω to 2.0V V OHC Output HIGH Voltage 1095 1035 mv V IN = V IH(Min) Loading with V OLC Output LOW Voltage 1565 1610 mv or V IL(Max) 50Ω to 2.0V V IH Input HIGH Voltage 1170 870 1165 870 mv Guaranteed HIGH Signal for All Inputs V IL Input LOW Voltage 1830 1480 1830 1475 mv Guaranteed LOW Signal for All Inputs I IL Input LOW Current 0.50 0.50 µa V IN = V IL(Min) I IH Input HIGH Current D 2a D 2e 250 250 µa V IN = V IH (Max) D 1a D 1e 350 350 I EE Power Supply Current 69 30 69 30 ma Inputs Open Note 4: The specified limits represent the worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. for testing shown in the tables are chosen to guarantee operation under worst case conditions. PLCC AC Electrical Characteristics V EE = 4.2V to 5.7V, V CC = V CCA = GND t PHL D 2a D 2e to O, O t PHL D 1a D 1e to O, O t PHL Data to F t TLH Transition Time t THL 20% to 80%, 80% to 20% T C = 40 C T C = +25 C T C = +85 C Min Max Min Max Min Max 0.45 1.70 0.55 1.60 0.55 1.70 ns 0.45 1.50 0.55 1.40 0.55 1.50 ns 1.05 2.55 1.15 2.55 1.15 2.80 ns 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1, 2 3 www.fairchildsemi.com

100307 Test Circuitry Notes: V CC, V CCA = +2V, V EE = 2.5V L1 and L2 = equal length 50Ω impedance lines R T = 50Ω terminator internal to scope Decoupling 0.1 µf from GND to V CC and V EE All unused outputs are loaded with 50Ω to GND C L = Fixture and stray capacitance 3 pf FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com 4

Physical Dimensions inches (millimeters) unless otherwise noted 100307 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 5 www.fairchildsemi.com

100307 Low Power Quint Exclusive OR/NOR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com