Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Department of Electrical, Electronic and Computer Engineering Wintereksamen Kopiereg voorbehou Analoogelektronika ENE310 18 Junie 2004 Winter Examination Copyright reserved Analogue Electronics ENE310 18 June 2004 Toetsinligting: Test information: Maksimum punte: Maximum marks: 100 Duur van vraestel: Duration of paper: 180 minute 180 minutes Volpunte: Full marks: 100 Oopboek / toeboek: Oop (Enige materiaal) Open / closed book: Open (Any material) Eksamen beplanning: n Addisionele 10 minute sal aan die begin van die eksamen beskikbaar gestel word. Gedurende hierdie tydperk mag Kandidate nie op die antwoordstelle skryf nie. Exam planning: An additional 10 minutes will be availed at the start of the exam. During this period, candidates may not make any markings on the answer scripts. Enige toestel met n kommunikasiepoort (van enige aard) word nie toegelaat nie. Any device with a communication port (of whatsoever kind) may not be used. Totale aantal bladsye (hierdie blad ingesluit): Total number of pages (including this page): 15 BELANGRIK- IMPORTANT 1. Die eksamenregulasies van die Universiteit van Pretoria geld. The examination regulations of the University of Pretoria apply. 2. Vrae moet in onuitwisbare ink beantwoord word. Geen antwoorde wat in potlood geskryf is sal gemerk word nie. Questions must be answered in indelible ink. Answers in pencil will not be marked. 3. Daar is twee stelle antwoordboeke beskikbaar vir hierdie eksamen: die standard 8 bladsy antwoordboek & n addisionele spesiale ontwerp & numeriese analiese opsommingsblad/boek. Dit moet vir die beantwoording van hierdie eksamen gebruik word. There are two sets of answer booklets available for this examination: the standard 8 page answer booklet & an additional special design & numeric analysis summary sheet/booklet. These must be used for answering this examination. 4. Toon alle berekeninge waar/indien van toepassing. Geen punte sal toegeken word vir korrekte antwoorde sonder berekenings/redenasies om dit te staaf nie. Show all calculations where/as applicable. No marks will be given for correct answers without calculations/reasoning to support them. 5. Gebruik duidelik geregverdigde & kundige Ingenieursbenaderings (en/of aannames) waar/indien van toepassing. Use clearly justified & educated engineering approximations (and/or stated assumptions) where/as appropriate. 6. Verskeie datavelle word voorsien as deel van die aanhangsels van hierdie eksamen. Daar word voorgestel dat studente duidelik (geregverdig) die gebruikte parameters en waardes, wat vanaf die datavel gebruik word, noem. Various datasheets are provided as part of the appendices to this examination. Students are advised to very clearly (with justification) remark the parameters & values used from the datasheet. Dosent: Lecturer: Mr Saurabh Sinha Eksterne Eksaminator: External examiner: Prof. M. du Plessis & Mr Johan Schoeman Vertaler (Engels Afrikaans) Translator (English Afrikaans): Mr Werner Düvel
EXAMINATION PREFIX The following figure shows the general structure of a series-shunt feedback amplifier. v s Σ \\ A-network v o v fb \\ β-network The examination is aimed as a procedural process to design the first preliminary circuit of the above structure: Question 1: Design of a difference amplifier [6] Study Unit: 8 (Study Theme 4) Question 2: Partial design of the A network consisting of a CS & CC amplifier (Including biasing & design for a particular frequency response) [16] Study Units: 3, 4 & 5 (Study Theme 2) [13] Study Units: 6 & 7 (Study Theme 3) [21] Study Units: 9, 10, 11, 12 & 13 (Study Theme 5) Question 3: Design of a class AB power stage with short circuit protection [10] Study Unit: 17 (Study Theme 7) Question 4: Analysis of a typical β-network & feedback analysis [19] Study Units: 14, 15 & 16 (Study Theme 6) [7] Study Unit: 2 (Study Theme 1) Question 5: Designing with heat-sinks [4] Study Unit: 18 (Study Theme 7) Question 6: Basic ADC application (unrelated to the feedback structure) [4] Study Unit: 1 (Study Theme 1) IImppoorrt taannt t nnoot tee In answering every question, clearly state: all parameters of relevance (such as device parameters from datasheets), all design assumptions, all design component values (including all components of a biasing network), and justification of any educated engineering approximations made. Datasheets required refer to: Appendix A: Q2N2222 datasheet Appendix B: Q2N7000 datasheet Appendix C: Standard resistor sheet Appendix D: Standard capacitor sheet 2
Question 1 [6]: Design of a differential amplifier (DA) The comparator of the feedback structure can be simply implemented by a DA. This is shown below. Differential-to-singleended converter VCC_BAR V v s Σ v o1 v o2 v o-se VCC_CIRCLE v s R C VCC_CIRCLE v o1 v o2 VCC_CIRCLE Q 1 Q 2 R C vvcc_circle fb DA v fb I O VCC_BAR V EE Component specifications ( Datasheets required) 5 % standard resistors BJT: Q2N2222 Assume an ideal current source, I O is available. Design the DA that meets the following specifications: a differential-mode single-ended gain, A dm-se 100, a common mode rejection ratio, CMRR > 60 db, a differential swing range at output terminals of at least ± 3 V, an input resistance, r in-dm > 1 k, an output resistance, r out-se < 1 k, and power supplies fixed: V CC/EE = ± 10 V. 3
Question 2 [50]: Design of a CS & CC amplifier The configuration represents part of the feed-forward, A network. v o-se CS CC v o-ab The CS & CC amplifier needs to be designed as part of this problem. Assume that the amplifiers are coupled by the dc blocking capacitor, C C. VCC_BAR V DD R 1 R D R 3 R C C M C C VCC_CIRCLE v o-se C IN M 1 Q 3 Q 4 C O vvcc_circle o-ab R 2 R S C S R 4 R E CS CC Component specifications ( Datasheets required) 5 % standard resistors Standard capacitors BJT: 2 x Q2N2222 MOSFET: Q2N7000 Power supply, V DD = 10 V Inter(pre/post)-stage: The source resistance, R S prior to the CS stage can be assumed as 1 k. The input resistance of the class AB stage following the CC stage can be assumed as 1 k. Design [35] the cascade stage to achieve: Mid-band gain, A v = v o-se /v o-ab = 20 db (Completely specify each biasing network to set the required gain as/where applicable) Mid-band region, 100 Hz to at least 1 MHz (Use the method of time-constants and/or Miller s theorem as/where applicable) Analyse the network: [3] sketch the bode magnitude & phase plots of each stage, [3] sketch the bode magnitude & phase plots of the cascade, [4] specify the two port-model of each of the amplifiers, viz. CS & CC, [3] completely specify the two-port network model of the network, and [2] determine the dc power dissipation of the entire network. 4
Question 3 [10]: Design of a class AB amplifier A class AB amplifier follows the cascade network of Question 2. This is shown below. VCC_BAR V R B1 Q 5 VCC_CIRCLE v o-ab D 1 C C Q 6 R E1 C L R L vvcc_circle o D 2 R E2 R B2 Q 7 Component specifications: 5 % standard resistors ( Datasheet required) BJT: complementary pair (Q 5 & Q 7 ) Capacitors, C Power supply, V CC = 10 V Assume the current gain, β of all transistors as approximately 50. Design [5] the class AB amplifier to meet the following specifications: deliver 1 W to a load, R L = 4, and achieve maximum power transfer to the load. Analyse the designed amplifier to approximate: [1] the input resistance, [1] the output resistance, [1] the efficiency, and [1] the power dissipated by transistor, Q 5. [1] Sketch the transfer curve of the class AB amplifier as shown above. 5
Question 4 [26]: Analysis of a typical β-network & feedback analysis Assume that the feedback structure can be approximately represented as below. VCC_CIRCLE v s 3 2 + - A-network OUT 6 vvcc_circle o v fb Rβ2 R β1 β-network Assume that the A-network can be represented by: Ao A( jω) =, jω jω jω 1 + 1 + 1 + ω1 ω2 ω3 where ω 1 = 10 rad/s, ω 2 = ω 3 = 10 6 rad/s, and A o = 120 db. Design [2] the feedback network (select resistor component values) to achieve a feedback gain, A fb = 100. Analyse (taking the loading of β-network into account) the shunt-series feedback structure to determine/sketch: [3] the input resistance of the entire feedback network, R if, [3] the output resistance of the entire feedback network, R of. [7] the two port network, and [3] the closed-loop amplifier bandwidth. Stability analysis: [3] Sketch the bode magnitude and phase plot of the open-loop, A network. [3] Approximate the gain margin, GM (in db) & phase margin, PM (in º) for the design. [2] Assuming that A o varies by ± 10 db. For this variation, comment on the stability of the above network. 6
Question 5 [4]: Designing with a heat sink Assume that the power transistors used in Question 3, has a rated power of 15 W and a maximum junction temperature, T j-max = 200 ºC. The device is to operate in air at an ambient temperature of 25 ºC. The transistor is mounted on a heat sink with Θ sink-air = 4 ºC/W and Θ case-sink = 1 ºC/W. [4] Determine the actual power that can be safely dissipated in the transistor. Question 6 [4]: Basic ADC application The following problem is unrelated to the feedback structure shown in the examination prefix. VCC_CIRCLE v X ADC VCC_CIRCLE VCC_CIRCLE 14-bit binary output data (b 1, b 2,, b 14 ) VCC_CIRCLE [4] The AD9240 is a 14 bit ADC with V REF set to 10 V. If the input is v X = 1.4321 V, determine the binary output of the converter. 7
APPENDIX A 8
9
10
11
12
APPENDIX B 13
APPENDIX C Standard component scaling factors Standard base resistor values are given in the following tables for the most commonly used tolerances (1%, 5%, 10%), along with typically available resistance ranges. To determine values other than the base, multiply the base value by 10, 100, 1 000 or 10 000. Example: Calculations indicate the need for a 355 k resistor and a tolerance of 1%. Look in the 1% table and select the 35.7 value (the nearest available standard value). Multiply by 10 000 to convert to 357 k. 1% Standard Values Decade multiples are available from 10.0 through 1.00 M (also 1.10 M, 1.20 M, 1.30 M, 1.50 M, 1.60 M, 1.80 M, 2.00 M and 2.20 M) 10.0 10.2 10.5 10.7 11.0 11.3 11.5 11.8 12.1 12.4 12.7 13.0 13.3 13.7 14.0 14.3 14.7 15.0 15.4 15.8 16.2 16.5 16.9 17.4 17.8 18.2 18.7 19.1 19.6 20.0 20.5 21.0 21.5 22.1 22.6 23.2 23.7 24.3 24.9 25.5 26.1 26.7 27.4 28.0 28.7 29.4 30.1 30.9 31.6 32.4 33.2 34.0 34.8 35.7 36.5 37.4 38.3 39.2 40.2 41.2 42.2 43.2 44.2 45.3 46.4 47.5 48.7 49.9 51.1 52.3 53.6 54.9 56.2 57.6 59.0 60.4 61.9 63.4 64.9 66.5 68.1 69.8 71.5 73.2 75.0 76.8 78.7 80.6 82.5 84.5 86.6 88.7 90.9 93.1 95.3 97.6 5% Standard Values Decade multiples are available from 10 through 22 M 10 11 12 13 15 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91 10% Standard Values Decade multiples are available from 10 through 1 M 10 12 15 18 22 27 33 39 47 56 68 82 14
APPENDIX D Standard Capacitor Values These capacitor values are the most commonly found pf pf pf pf µf µf µf µf µf µf µf 1.0 10 100 1000 0.01 0.1 1.0 10 100 1000 10,000 1.1 11 110 1100 1.2 12 120 1200 1.3 13 130 1300 1.5 15 150 1500 0.015 0.15 1.5 15 150 1500 1.6 16 160 1600 1.8 18 180 1800 2.0 20 200 2000 2.2 22 220 2200 0.022 0.22 2.2 22 220 2200 2.4 24 240 2400 2.7 27 270 2700 3.0 30 300 3000 3.3 33 330 3300 0.033 0.33 3.3 33 330 3300 3.6 36 360 3600 3.9 39 390 3900 4.3 43 430 4300 4.7 47 470 4700 0.047 0.47 4.7 47 470 4700 5.1 51 510 5100 5.6 56 560 5600 6.2 62 620 6200 6.8 68 680 6800 0.068 0.68 6.8 68 680 6800 7.5 75 750 7500 8.2 82 820 8200 9.1 91 910 9100 15
Student Number Signature Full Name Special Answer Sheet: Design & Numeric Analysis Summary This sheet does not include the summary of answers requiring sketches (such as Bode plots, two-port models, etc.) These sketches must be part of the answer booklet. QUESTION 1 VCC_BAR V V CC = V EE = 10 V R C R C R C = VCC_CIRCLE v s VCC_CIRCLE v o1 v o2 VCC_CIRCLE Q 1 Q 2 vvcc_circle fb I O = A I O VCC_BAR V EE QUESTION 2 R 1 R D V DD VCC_BAR R 1 = R 2 = R 3 R C R D = R S = C M C C C IN VCC_CIRCLE v o-se Q 3 C O M 1 Q 4 R 2 R R 4 R E S C S CS CC V DD = 10 V R 3 = R 4 = R C = R E = vvcc_circle o-ab C C = C M = C S = C IN = C O = dc power dissipation of the entire network: W F F F F F University of Pretoria http://eerc.up.ac.za/~subjects [ENE310] [Analogue Electronics] Winter Examination: Design & numeric analysis summary sheet 1
QUESTION 3 VCC_CIRCLE v o-ab QUESTION 4 R B1 D 1 Q 6 C C D 2 R B2 VCC_CIRCLE v s 3 2 + - v fb Rβ2 VCC_BAR V Q 5 R E1 C L R E2 Q 7 A-network OUT R L 6 vvcc_circle o vvcc_circle o R B1 = R B2 = R E1 = R E2 = R L = 4 C V CC = 10 V R IN = R OUT = η = % P Q5 = W R β1 = R β2 = R if = R of = BW = Hz R β1 β-network GM = db PM = º Stable: / YES / NO QUESTION 5 Power = W QUESTION 6 b 1 MSB b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 LSB University of Pretoria http://eerc.up.ac.za/~subjects [ENE310] [Analogue Electronics] Winter Examination: Design & numeric analysis summary sheet 2