Digital Integrated Circuits Lecture 4: CAMs, ROMs, and PLAs Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec4 cwliu@twins.ee.nctu.edu.tw
Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 2
CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key adr data/key read write CAM match DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 3
T CAM Cell Add four match transistors to 6T SRAM 56 x 43 λ unit cell word bit bit_b match cell cell_b DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 4
CAM Cell Operation Read and write like ordinary SRAM CAM cell For matching: Leave wordline low Precharge matchlines address row decoder clk weak miss match match match2 Place key on bitlines Matchlines evaluate read/write column circuitry data match3 Miss line Pseudo-nMOS NOR of match lines Goes high if no words match DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 5
Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines or DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 6
ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate s in ROM Word : Word : Word 2: A A weak pseudo-nmos pullups Word 3: 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y Y Looks like 6 4-input pseudo-nmos NORs DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 7
ROM Array Layout Unit cell is 2 x 8 λ (about / size of SRAM) Unit Cell DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 8
Row Decoders ROM row decoders must pitch-match with ROM Only a single track per word! DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 9
Complete ROM Layout DIC-Lec4 cwliu@twins.ee.nctu.edu.tw
PROMs and EPROMs Programmable ROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable ROMs Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO 2) n+ n+ p bulk Si DIC-Lec4 cwliu@twins.ee.nctu.edu.tw
Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires words x bits Changing function is easy reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with bit ROM and bit reg inputs n DEC 2 n wordlines ROM Array inputs n ROM k s state outputs k s k outputs DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 2
Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires 2 n words x k bits Changing function is easy reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with 2 n+s x (k+s) bit ROM and (k+s) bit reg inputs n DEC 2 n wordlines ROM Array inputs n ROM k s state outputs k s k outputs DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 3
Example: RoboAnt Let s build an Ant Sensors: Antennae (L,R) when in contact Actuators: Legs Forward step F Ten degree turns TL, TR L R Goal: make our ant smart enough to get out of a maze Strategy: keep right antenna on wall (RoboAnt adapted from MIT 6.4 22 OpenCourseWare by Ward and Terman) DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 4
Lost in space Action: go forward until we hit something Initial state DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 5
Bonk!!! Action: turn left (rotate counterclockwise) Until we don t touch anymore DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 6
A little to the right Action: step forward and turn right a little Looking for wall DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 7
Then a little to the left Action: step and turn left a little, until not touching DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 8
Whoops a corner! Action: step and turn right until hitting next wall DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 9
Simplification Merge equivalent states where possible DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 2
DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 2 State Transition Table X X X X X F TL TR S : R L S : Lost RCCW Wall Wall2
ROM Implementation 6-word x 5 bit ROM S S L R L, R ROM TL, TR, F 4:6 DEC S' : S : S ' S 'TR'TL'F' DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 22
ROM Implementation 6-word x 5 bit ROM S S L R L, R ROM TL, TR, F 4:6 DEC S' : S : S ' S 'TR'TL'F' DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 23
PLAs A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms Example: Full Adder s = + + + c = ab+ bc+ ac out AND Plane OR Plane a b c s cout Inputs Outputs bc ac ab Minterms DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 24
NOR-NOR PLAs ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient Use DeMorgan s Law to convert to all NORs AND Plane OR Plane AND Plane OR Plane bc bc ac ac ab ab a b c s c out a b c s c out DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 25
PLA Schematic & Layout AND Plane OR Plane bc ac ab a b c s c out DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 26
PLAs vs. ROMs The OR plane of the PLA is like the ROM array The AND plane of the PLA is like the ROM decoder PLAs are more flexible than ROMs No need to have 2 n rows for n inputs Only generate the minterms that are needed Take advantage of logic simplification DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 27
Example: RoboAnt PLA Convert state transition table to logic equations S : L R S : TR TL F X X X X X TR = S S TL = S F = S + S DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 28
RoboAnt Dot Diagram AND Plane OR Plane S' = S S + LS + LRS S' = R+ LS + LS TR = S S TL = S F = S + S S S S LS LS R LRS LS SS S S L R S ' S ' TR TL F DIC-Lec4 cwliu@twins.ee.nctu.edu.tw 29