LOSS COPARSON OF TWO AND THREE-LEVEL NVERTER TOPOLOGES G.. Orfnoudis*, S.. Shrh*,. A. Yurtih nd. A. Ausr* * University of Southmpton, UK, TSL Tehnology, UK G..Orfnoudis@soton..u Keywords: nverter, DC-lin pitors, losses. Astrt This pper investigtes semiondutor nd DC-lin pitor losses in two two-level nd two three-level voltge soure inverters. The omponents of the four inverters re seleted to hve pproprite voltge nd urrent rtings. Anlytil epressions for semiondutor losses re reviewed nd epressions for DC lin pitor losses re derived for ll topologies. Three-level inverters re found to hve lower semiondutor losses, ut higher DC-lin pitor losses. Overll, the three-level Neutrl-Point-Clmped inverter proved to e the most effiient topology.. 1 ntrodution The proess of seleting the topology, omponents nd operting prmeters (voltge, urrent nd swithing frequeny) of n inverter is highly ffeted y the ntiipted inverter losses. An urte estimte of the losses ourring in eh prt of n inverter n signifintly ontriute to hieving n enhned inverter design. This pper emines the semiondutor nd DC-lin pitor losses of four voltge soure inverter topologies: the onventionl two-level inverter, the two-level two-hnnel interleved inverter, the three-level Neutrl-Point-Clmped (NPC) inverter nd the three-level Csded H-Brge inverter, shown in Figure 1. Losses in two-level inverters hve een reported etensively in the literture. Reserhers hve lso investigted semiondutor losses in three-level inverters. Estimtes of swithing losses hve een otined using pproimtions of GBT nd diode -V swithing hrteristis [1 17, 18]. However, more onvenient pproh sed on lulting swithing loss using the swithing energy-urrent (E sw -) hrteristis, revels tht the swithing losses of n GBTdiode pir re pproimtely proportionl to the swithing voltge nd urrent [1]. This oservtion n e verified sed on GBT-Diode module dt sheets [8]. Anlytil epressions for swithing losses in two-level inverter n e found in [7, 1]. For the two-level inverter, ll ontinuous PW methods hve the sme swithing losses, whih re lso independent of the lod phse ngle [9, 1]. Disontinuous strtegies, however, n result in lower swithing losses. Swithing losses in three-level NPC inverter hve een investigted in [7], using seond order pproimtion of the GBT nd diode E sw - hrteristis... d. Figure 1: Ciruit digrms (one leg) of (.) Two-level inverter, (.) Two-hnnel two-level interleved inverter, (.) Three-level NPC inverter nd (d.) Three-level Csded H- Brge inverter.
Epressions for the two-level inverter ondution losses n e found in [, 1, 1]. The lultion of ondution losses is sed on the liner -V hrteristis of the GBT-diode modules. Unlie swithing losses, two-level inverter ondution losses re ffeted y the seletion of the PW strtegy nd the lod power ftor. Epressions for the NPC inverter n e found in [7] s well s in [1] for numer of modultion strtegies. DC-lin pitor loss estimtion is sed on the rms vlue of the pitor urrent. The derivtion of the urrent rms epression for the two-level inverter hs een presented in [8, 13, 19]. Cpitor loss estimtions lso pper for the twolevel two-hnnel interleved nd the three-level Csded H- Brge inverters in [] nd [], respetively. The DC-lin of the three-level NPC inverter hs only een studied in the literture with respet to its voltge nd the pitor lning prolem [5, 15, 16]. n this pper, epressions for swithing nd ondution losses in the four inverter topologies re reviewed. Anlytil epression for DC-lin pitor losses re derived for the two-level interleved nd the three-level inverters. Unlie most studies tht fous on single inverter topology or loss type, the epressions for semiondutor nd DC-lin pitor losses re used to ompre the four emined topologies. Another signifint ontriution of the pper is tht the omprison is sed on seletion of inverter omponents from ville ommeril devies with pproprite voltge/urrent rtings nd swithing frequeny. This seletion whih is different for eh topology, ffets the resulting losses. Seletion of GBT-Diode odules The four inverter topologies re ompred on the sis of ommon power output. Assuming DC-lin voltge V d of V (1V for the Csded H-Brge inverter) nd nominl lod pe urrent of 37A, the inverter power rting S o is equl to 555VA. The swithing voltge of the GBT-diode modules in threelevel inverter is hlf of tht in two-level inverter generting voltge wveform with the sme mplitude. The voltge rting of the GBT-diode modules used in three-level inverter therefore needs to e hlf tht of n equivlent twolevel inverter. This differene in voltge rting hs very signifint impt on swithing nd ondution loss prmeters of the modules. The urrent rried y eh module is the sme for ll topologies eept for the interleved inverter in whih eh module rries hlf the urrent. The effet of the module urrent rting on swithing loss prmeters is insignifint, ut ondution loss prmeters re pproimtely douled for the hlf urrent-rted modules. Approprite GBT modules re seleted for eh topology. The two-level inverter uses high-voltge high-urrent GBTdiode modules (A), the interleved inverter uses high-voltge low-urrent modules (B), while the three-level inverters uses the low-voltge high-urrent module (C). Tle 1 lists the swithing nd ondution prmeters of the seleted modules. odule A is the Eupe FZ8R33KLC_B5 3.3V 8A GBT-diode module, odule B is the FZR33KLC_B5 3.3V A GBT-diode module, while odule C is the FF8R17KE3 1.7V 8A module. Prmeter vlues hve een otined from modules dt sheets [8]. Prmeter odule odule odule Unit A B C V se 1.8 1.8.9 V V, 1.6 1.6.9 V R.5 5 1.87 mω V,d 1.7 1.7 1 V R d 1.5.5 1 mω 5.7 5.7.8 mj/a 5 5 mj d.5.5.1 mj/a d 15 15 6 mj Tle 1: GBT-Diode module prmeters Prmeters V,/d nd R /d pproimte the ondution -V hrteristis of GBTs/diodes, respetively, ording to: V V, / d + R (1) / d Prmeters V se, /d nd /d pproimte the swithing energy E sw - hrteristis ording to: Vsw E sw, / d ( / d sw + / d ) () Vse where V sw nd sw re the instntneous swithing voltge nd urrent, respetively. 3 Estimtion of nverter Semiondutor Losses For given swithing frequeny f s, the two-level inverter hs the sme swithing losses for ll ontinuous PW methods. Swithing losses re lso independent of the inverter modultion inde nd the lod power ftor PF [1] ut inrese linerly with swithing frequeny. Condution losses re not ffeted y f s ut depend on the modultion strtegy, nd PF. For ommonly used swithing frequenies, ondution losses of the two-level inverter re signifintly lower thn orresponding swithing losses. The two-level two-hnnel interleved inverter losses re emined under the ssumption tht the instntneous urrent rried y eh of the inverter hnnels is pproimtely hlf of the respetive phse urrent. Leg (hnnel) indutors nd suffiiently high swithing frequenies re used to stisfy this requirement. Eh module in this topology therefore rries hlf the urrent of two-level inverter module. On the other hnd, the numer of modules in the interleved inverter is twie tht of the onventionl two-level inverter.
Given tht the epressions for swithing nd ondution losses in the onventionl two-level inverter re (3) nd (), the epressions for the interleved inverter losses n e proved to e (5) nd (6), respetively. All equtions refer to the three-phse inverters modulted y sinusol wveforms nd their derivtion is sed on [1]. Prmeters nd represent the sums of, d nd, d, respetively, of the module seleted for eh inverter. Vd Psw L 6 + f (3), s Vse 3 Pon,L ( R + Rd ) + ( R Rd )osφ + () 3 3 ( V + Vd ) + ( V Vd )osφ Vd Psw L nt 6 + f (5), s Vse 3 Pon,L nt ( R + Rd ) + ( R Rd )osφ + 8 (6) 3 3 ( V + Vd ) + ( V Vd )osφ The indivul swithing loss epressions for the three-level NPC inverter modules given in [7], were revised ssuming liner dependene of the swithing losses on the instntneous urrent. Their summtion yields Eqution (7) for the totl three-phse NPC inverter swithing losses. The respetive eqution for ondution losses is (8). These epressions re pplile to ny doule rrier PW methods with sinusol referene wveforms, suh s threelevel PD nd APOD/POD PW, eplined in [1]. Vd Psw L 3 + f (7),3 s Vse 3 Pon,3L ( R + Rd ) + ( R Rd )osφ + (8) 6 3 ( V + Vd ) + ( V Vd )osφ Under the ssumption of n equivlent modultion strtegy s desried in [1], the three-level Csded H-Brge inverter n e shown to hve the sme semiondutor losses s the NPC inverter. Equivlent strtegies ssoite eh GBTdiode module of the NPC inverter to module of the Csded inverter. The losses on GBTs re equl for respetive modules, while losses on the NPC inverter s lmping diodes re trnsferred to free-wheeling diodes of the Csded inverter. The three-phse semiondutor losses for the Csded H-Brge topology n lso e lulted using Equtions (7) nd (8). DC-Lin Cpitor RS Current n this prgrph, the method of [6], used for the derivtion of the two-level inverter pitor urrent rms epression, is pplied to the three other inverter topologies. The method onsers eh inverter GBT-diode module s swith tht, while on, rries the urrent of the respetive phse. The sum of the urrents through the upper swithes of n inverter is i d, s shown in Figure 1 for eh of the four topologies. The DC omponent of this urrent is supplied y the inverter DC soure, while the AC omponent is filtered, nd hene rried y the DC-lin pitor. The rms vlue of the pitor urrent, C,rms, is lulted using the verge (DC) nd rms vlues of i d, d,,dc nd d,,rms, respetively: + (9) d, rms d, DC C, rms C, rms d, rms d, DC Aording to [6], the lultion of urrent i d verge nd rms vlues is sed on the nlysis of its trnsitions during single swithing period. f i d is equl to i d,int1, i d,int,... during time intervls T int1, T int,..., respetively (with T int < T s ), then its verge nd rms vlue during swithing period T s re given y Equtions (1) nd (11): 1 i d, DC ( θ ) Tint,int (1) int d,int Ts 1, rms ( θ ) Tint,int (11) int d,int Ts The intervl duty yles int nd respetive urrents i d,int re funtions of θ, the ngle of the voltge referene wveform for phse. The verge nd rms vlues of i d over fundmentl period re otined using the following epressions: 1 d DC DC ( θ ) (1),, d, rms 1, rms ( θ ) (13) The epressions for int (θ) nd i d,int (θ) my hnge during setors of the fundmentl yle. n this se, the ove epressions re written s sums of integrls for the different setors. For emple, for the derivtion of the DC-lin pitor urrent rms epression of the two-level two-hnnel interleved inverter, the fundmentl yle is dived into si setors, eh of whih overs n ngle of /3. The inverter opertion in these setors is symmetri nd hene only one setor needs to e nlyzed. Setor ( /3) is dived into two su-setors, s desried in Tle. The tle illustrtes the duty yles of the swithing intervls nd the orresponding vlues of urrent i d s int i int. Angles θ α, θ nd θ, re equl to: θ, θ nd θ 3 3
Setor 1 Setor Durtion (θ) /6 /6 /3 T / T s T / T s T / T s ntervl 1 (1- - ) -i / (1- - ) -i / ntervl ( - ) (i -i )/ ( - ) (i -i )/ ntervl 3 ( -1/) -i ( -1/) -i Tle : Swithing intervls for the two-level two-hnnel interleved inverter For two-level inverters: 1 1+ sin θ + θ ( ( )) (1) Assuming tht the inverter lod hs power ftor os(φ), the three-phse urrents re given y: i sin θ + θ φ (15) ( ) Aording to Tle, for setor 1 : i, DC, 1, L nt ( θ ) ( 1 ) i i + + 1/ i i, rms, 1, L nt ( θ ) ( 1 ) i i + + 1/ i ( ) ( ) ( ) ( ) ( ) ( ) (16) (17) Similrly, epressions n e derived for setor. The verge (DC) nd rms vlues of i d re given y: / 6 / 3 3 i 1, + i, (18) d DC L nt d DC L nt d DC L nt / 6 / 6 / 3 3 i 1, + i, (19) d rms L nt d rms L nt d rms L nt / 6 whih result in: d, DC,L nt os( φ) () 3 3 1 3 + + os ( φ) (1) d rms L nt 6 The pitor urrent rms epression for the two-level interleved inverter will therefore e given y: 3 3 1 3 + + os ( φ) 6 C, rms,l nt () os ( φ) 16 For the three-level NPC inverter, the three-phse voltge nd urrent wveforms re dived into three setors, overing n intervl of /3, eh. Setor is dived into three susetors, s desried in Tle 3. Setor 1 Setor Setor 3 Durtion (θ) /6 /3 /3 /3 /3 5/6 T / T s T / T s T / T s ntervl 1 -i i -i ntervl - i - i Tle 3: Swithing intervls for the three-level NPC inverter For three-level inverters: sin ( θ + θ ) (3) Aording to Tle 3, for setor 1 : DC NPC ( θ ) ( i ) + ( ) () 1, i θ i + (5) ( ) ( ) d, rms, 1, NPC ( ) Similr epressions re derived for setors nd 3. The DC nd rms vlues of i d for the NPC inverter re derived using equtions similr to (18) nd (19), whih result in: 3 d, DC, NPC osφ (6) 3 [ 1 os ( )] + φ (7) d rms NPC Use of Eqution (9) here gives the urrent rms epression for the upper pitor of the three-level NPC inverter. Due to symmetry, the epression for the lower pitor is entil: 3 3 9 + os ( φ) (8) C rms NPC 8 The derivtion of the DC-lin pitor urrent rms for the three-phse Csded H-Brge inverter is sed on the nlysis of single H-Brge, tht of phse. The urrent rms vlue of eh pitor in this topology is not ffeted y the swithing opertions of the other phses. The lultion of the pitor rms urrent is sed on the nlysis of one out of two symmetril setors, overing n intervl of, eh. Durtion (θ) Τ / T s ntervl 1 i Tle : Swithing intervls for phse of the three-level Csded H-Brge inverter Aording to Tle : DC Cs ( θ ) (9) i θ i (3) ( ) d, rms, Cs
The verge (DC) nd rms vlues of urrent i d for the Csded H-Brge inverter re lulted using Equtions (1) nd (13), respetively, whih result in: d, DC, Cs os( φ) (31) ( 3 + os(φ )) (3) d rms Cs 3 The pitor urrent rms epression for this topology n e lulted using (9), (31) nd (3) to e: [ 3 + ( 8 3 ) os( )] (33) C, rms, Cs φ The DC-lin pitor urrent of single-phse H-Brge hs een investigted in [], deriving n epression for the rms vlue of high frequeny pitor urrent hrmonis. This epression is equivlent to (33), whih lso inorportes the low-frequeny hrmoni of the Csded H-Brge inverter DC-lin pitor urrent. All the ove derived pitor urrent rms epressions were verified y inverter simultions in the SimPowerSystems toolo of tl-simulin. 5 Results All inverters re ssumed to supply 3Ω impedne (Z) lod with power ftor equl to.9. Due to the inresed swithing losses of high-voltge GBTs, however, two-level inverters re ssumed to e swithed t lower frequenies. The swithing frequeny f s is set to 1Hz for two-level nd.5hz for three-level inverters, respetively. Figure plots the semiondutor losses ginst the inverter odultion nde, ording to Equtions (3)-(8) nd the vlues of Tle 1. An inspetion of the plot indites tht the swithing losses of the two-level inverters re signifintly higher thn tht of the three-level inverters. Even though the swithing frequenies of the two-level inverters re lower, three-level inverters ehiit mjor dvntge over swithing losses, s result of their deresed swithing prmeter vlues ( /d nd /d ). The deresed numer of output voltge levels nd the lower swithing frequenies lso hve negtive impt on the output hrmoni performne of the two-level inverters, ut this onsertion is eyond the sope of this pper. Losses (W) 6 5 3 1 L Swithing 3L Swithing L Condution 3L Condution nterleved Conventionl...6.8 1 Figure : Semiondutor losses vs The ondution losses of the two two-level inverters re equl due to the vlues of ondution prmeters R /d, whih re hlf for the interleved inverter modules (see Equtions () nd (6)). Condution losses for three-level topologies re slightly higher. The DC-lin pitors power losses re given y the following epression: PC N RC (3) C,rms where N is the numer of pitors used in eh topology nd R represents the Equivlent Series Resistne (ESR) of eh pitor. As shown in Figure 1, N is equl to for the two two-level nd the three-level NPC inverters, nd 3 for the Csded H-Brge inverter. Eh pitor (or pitor n) is ssumed to hve nominl voltge of 1V nd n ESR of 15mΩ. Losses (W) 1 8 6 L nd 3L NPC L nterleved 3L Csded...6.8 1 Figure 3: DC-lin pitor losses vs Figure 3 illustrtes the vrition of totl DC-lin pitor losses with modultion inde for the emined topologies. As shown in the figure, the two-level interleved inverter hs the lowest mount of DC-lin pitors losses. The pitor losses in the onventionl two-level inverter re higher nd equl to the three-level NPC inverter losses. n ft, the epressions for the pitor urrent rms vlues of these two topologies re entil. However, ording to inverter simultions, their instntneous pitor urrents nd urrent spetr differ signifintly. n ontrst to the two-level inverter, the pitor urrent of the three-level NPC inverter ontins low-frequeny hrmonis. Low-frequeny hrmonis lso pper in the pitor urrent of the three-level Csded H-Brge inverter. This topology hs the highest mount of pitor losses, prtilly due to the ft tht it uses three insted of two DC-lin pitors. A fied vlue of ESR ws ssumed for ll DC-lin pitors. n relity, the ESR of eletrolyti pitors tht re ommonly used for inverter DC-lins, vries with the frequeny of pitor urrent hrmonis. ts vlue for low frequenies, in the rnge of hundreds of Hz, is two to three times higher thn it is for frequenies in the rnge of Hz.
Losses for the three-level inverters, whose pitors rry low-frequeny pitor urrents, will therefore e higher thn predited y (3). DC-lin pitor sizing for these topologies must onser this epeted inrement. A finl remr refers to the losses in two-level interleved inverters. Results were presented ssuming tht ll topologies supply the sme urrent (with mgnitude nd phse φ) to the lod, for the given DC-lin voltges. However, the leg indutors of the interleved inverter inrese the pprent lod indutne (y L f /), hene deresing the lod urrent nd inresing the power ngle φ. The indutne of the leg indutors ws here ssumed to e smll ompred to the lod indutne. n prtie, the DC-lin voltge is inresed to ompenste for the indutor voltge drop. 6 Conlusion The pper emined nd ompred the semiondutor nd DC-lin pitor losses of four inverter topologies. The semiondutor losses of the onventionl nd interleved two-level inverters proved to e signifintly higher thn the respetive losses of the NPC nd Csded H-Brge threelevel inverters. Swithing losses tht dominte in the twolevel inverters re inresed even for low swithing frequenies, due to the high-voltge GBT-diode modules tht these topologies use. The interleved inverter hs higher swithing losses thn the onventionl two-level inverter. Semiondutor losses for the three-level topologies re lower nd equl for the NPC nd Csded H-Brge inverters, ssuming n equivlene of their modultion strtegies. n terms of DC-lin pitor losses, the interleved inverter n hieve etter results thn the onventionl two-level inverter. Cpitor losses in the onventionl two-level nd three-level NPC inverters proved to e equl. The Csded H-Brge inverter, on the ontrry, hs signifintly more pitor losses thn these two topologies. Lower DC-lin pitor losses of the two-level inverters nnot ompenste for their inresed semiondutor losses. Given the equlity of three-level inverter semiondutor losses, the NPC inverter proved to e the most effiient etween the four topologies. Referenes [1] O. Al-Nseem, R. W. Erison nd P. Crlin. Predition of swithing loss vritions y verged swith modelling, EEE Applied Power Eletronis Conferene (APEC), Vol. 1, pp. 8, () [] L. Asiminoei et l. Shunt Ative-Power-Filter Topology Bsed on Prllel nterleved nverters, EEE Trnstions on ndustril Eletronis, Vol. 55, No. 3, (8) [3]. H. Bierhoff nd F. W. Fuhs. DC-Lin Hrmonis of Three-Phse Voltge-Soure Converters nfluened y the Pulsewth-odultion Strtegy - An Anlysis, EEE Trnstions on ndustril Eletronis, Vol. 55, No. 5, (8) [] F. Csnells. Losses in PW inverters using GBTs, EE Proeedings in Eletril Power Applitions, Vol. 11, No. 5, pp. 35 39, (199) [5] N. Celnovi nd D. Boroyevih. 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