EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption
Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2
Power and Energy Challenges 1 billion computers in the world 0.4 PW (PetaWatt = 10 15 W) of power dissipation Equivalent to 65 nuclear plants! Data centers represent the absolute challenge 1 single server rack is between 5 and 20 kw 100 s of those racks in a single room! Power and energy management and minimization have emerged as some of the most dominant roadblocks. The best opportunity lies in a very aggressive scaling and adaptation of supply and threshold values in concert with a careful orchestration of the system activity. EE115C Winter 2017 3
The Power Challenge: A Modern Data Center IBM RoadRunner [2008] 2.35 MW Technical specs 12,240 Cell chips 6,562 AMD Opteron chips 98 TB of memory 278 racks (5,200 square feet) 55 miles of fiber optic cable 500,000 lbs 2.35 MW 437 M calculations / W Top supercomputer (PFlop) 122400 cores PowerXCell 8i 3.2 GHz Opteron DC 1.9 GHz 1,375,776 GFlops (peak) $100M Future data centers 1000 PFlops (~2015) Climate modeling Human genome science Limited (today) to ~20 MW due to power distribution issues EE115C Winter 2017 4
Portability: Battery Storage is the Limiting Factor Little change in basic technology store energy using a chemical reaction Battery capacity doubles every 10 years 4x in the last 10 years Energy density, size, and safe handling are limiting factors Energy density KWH/kg of material Gasoline 14 Lead-Acid 0.04 Li polymer 0.15 EE115C Winter 2017 5
Power versus Energy Watts Power is the height of the waveform Lower power design could simply be slower Approach 1 Approach 2 time Watts Energy is the area under the waveform Two approaches require the same energy Approach 1 Approach 2 time EE115C Winter 2017 6
Where Does Power Go in CMOS? #1: Dynamic Power Consumption Charging and discharging capacitors #2: Short Circuit Currents Short-circuit path between supply rails during switching #3: Leakage Currents Leaking diodes and transistors EE115C Winter 2017 7
CMOS Energy & Power Equations Dynamic Short-circuit Leakage Energy C L V DD 2 t sc V DD I peak V DD I leakage / f clock Power C L V DD2 f 0 1 t sc V DD I peak f 0 1 V DD I leakage Switching frequency / activity f 0 1 = a 0 1 f clock EE115C Winter 2017 8
#1: Dynamic Power Dissipation Vdd V in V out C L Energy/transition = C L V dd 2 Power = Energy/transition f = f C L V dd 2 Dynamic power: observations Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power EE115C Winter 2017 9
Example Parameters Switched capacitance: 2fF / gate Fanout 4 gates Clock frequency: 2.5 GHz Power per gate Now, with many gates Activity: 0.1 10 M gates EE115C Winter 2017 10
Modification for Circuits With Reduced Swing V dd V dd V dd V t C L Can exploit reduced swing for lower power (e.g., reduced bit-line swing in memory) EE115C Winter 2017 11
General Formulas Basic formula Energy(V DD ) = Energy(heat) + Energy(C L ) Components: EE115C Winter 2017 12
Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E N : the energy consumed for N clock cycles n(n): the number of 0 1 transitions in N clock cycles EE115C Winter 2017 13
Lowering Dynamic Power Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations P dyn = C L V DD2 a 0 1 f clock Activity factor: How often, on average, do wires switch? Clock frequency: Increasing EE115C Winter 2017 14
Dynamic Power as a Function of V DD Decreasing V DD decreases dynamic energy consumption (quadratically) But, increases gate delay (decreases performance) Energy (norm) 1.2 1 0.8 0.6 0.4 0.2 1.2 1.0 0.9 0.7 0.55 0.45 V DD (V) 0.35 0.25 0.15 Scaling into the subthreshold regime results in very large delays (100-1000x) 0 1 10 100 1000 10000 100000 Delay (norm) EE115C Winter 2017 15
#2: Short-Circuit Power Consumption Vin I sc Vout C L Short-circuit current Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting Both LH and HL transitions have short-circuit current EE115C Winter 2017 16
I VDD (ma) Calculating Short-Circuit Power Vdd V in V out C L Triangular approximation 0.15 I peak Per switching period 0.10 0.05 V T V DD V T Esc = tsc VDD Ipeak P sc = t sc V DD I peak f 0 1 0.0 1.0 2.0 V in (V) 3.0 4.0 5.0 I peak depends on C L EE115C Winter 2017 17
Impact of C L on P SC I sc 0 I sc I max Vin Vout Vin Vout C L C L Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. Output fall time substantially smaller than the input rise time. EE115C Winter 2017 18
I peak as a Function of C L x 10-4 2.5 2 1.5 1 0.5 0-0.5 500 ps input slope C L = 20 ff C L = 100 ff 0 2 4 6 x 10-10 time (sec) C L = 500 ff Small C L I peak is large. Use small C in and large C L Gate delay is higher and the input rise time of the next gate (fanout gate) is higher Higher I sc in fanout gate!! Local optim. is not good Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. EE115C Winter 2017 19
How to Keep Short-Circuit Currents Down? Short-circuit current goes to zero if t slope,out >> t slope,in, but can t do this for cascade logic, so... EE115C Winter 2017 20
Minimizing Short-Circuit Power 8 7 6 Vdd =3.3 P norm P norm 5 4 3 Vdd =2.5 2 1 Vdd =1.5 0 0 1 2 3 4 5 t sin / t sout t sin /t sout Keep the input and output rise/fall times the same (<10% of total consumption) From: Veendrick, IEEE Journal of Solid-State Circuits, Aug 84 If V dd < V Tn + V Tp then short-circuit power can be eliminated! EE115C Winter 2017 21
#3: Leakage Current Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-threshold current is one of the most compelling issues Sub-Threshold in low-energy Current circuit Dominant design! Factor EE115C Winter 2017 22
Reverse-Biased Diode Leakage GATE p + p+ N + - V dd Reverse Leakage Current I DL = J S A J S = 10-100 pa/ m J S = 1-5pA/ m 2 2 at 25 deg C for 0.25 m CMOS J for a 1.2 m CMOS technology S doubles for every 9 deg C! J s double with every 9 o C increase in temperature EE115C Winter 2017 23
Sub-Threshold Leakage Component Leakage control is critical for low-voltage operation EE115C Winter 2017 24
#4: Static Power Consumption V DD I stat V out V in = V DD C L Wasted energy Should be avoided in most cases, but could help reducing energy in others (e.g. sense amps) EE115C Winter 2017 25
General Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance EE115C Winter 2017 26
Power and Energy Figures of Merit Power consumption in Watts determines battery life in hours Peak power determines power ground wiring designs sets packaging limits impacts signal noise margin and reliability analysis Energy efficiency in Joules rate at which power is consumed over time Energy = power * delay Joules = Watts * seconds lower energy number means less power to perform a computation at the same frequency EE115C Winter 2017 27
PDP and EDP Power-delay product (PDP) = P av * t p = (C L V DD2 )/2 PDP is the average energy consumed per switching event (Watts * sec = Joule) Lower power design could simply be a slower design Energy-delay product (EDP) EDP = PDP * t p = P av * t p 2 EDP is the average energy consumed multiplied by the computation time required Takes into account that one can trade increased delay for lower energy/op (e.g. via V DD scaling) EE115C Winter 2017 28 Energy-Delay (normalized) 15 10 5 0 0.5 1 1.5 2 2.5 Vdd (V) energy-delay energy delay
CMOS Energy & Power Equations (Summary) Dynamic Short-circuit Leakage Energy C L V DD 2 t sc V DD I peak V DD I leakage / f clock Power C L V DD2 f 0 1 t sc V DD I peak f 0 1 V DD I leakage ~75% today and decreasing relatively ~5% today and decreasing absolutely ~20% today and slowly increasing Switching frequency / activity f 0 1 = a 0 1 f clock EE115C Winter 2017 29
Simplified Model for Circuit Analysis Often we assume that switching energy is dominant Similarly to delay analysis, we can find equivalent capacitance for power analysis It is to expect that this capacitance will be higher, because it includes short-circuit power and leakage In our process, C in (power) = 2.45fF Including output parasitic C in + C par = 3.95fF (1.61 * 2.45fF) Simplified model for hand analysis: power cap delay cap! EE115C Winter 2017 30