Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13
Outline (1) Why is the CMOS inverter gain not infinite? Large-signal and small-signal models Derive two small-signal parameters: Transconductance: gm Output conductance: 2
Outline (2) How derive small-signal schematic How to bias the transistor: Common-source amplifier Small-signal schematic Gain CS-amplifier w. active load vs inverter Current mirror (for completeness) 3
From lecture 3 & lab 1: noise margin 4
CMOS inverter voltage transfer curve (VTC) Spectre simulation 65 nm process L = 1 µm, Wn= 1 µm & Wp = 2 µm 5
CMOS inverter VTC closeup gain = ΔVOUT/ΔVIN -140 mv/2 mv = -70 L = 1 µm, Wn= 1 µm & Wp = 2 µm What is the gain? It is NOT infinite! 6
The gain curve remember from lab 1 L = 1 µm, Wn= 1 µm & Wp = 2 µm 7
How can we calculate the inverter transfer curve? And why is the gain not infinite when both transistors are in saturation? 8
Transistor operation: digital and analog Digital: switch V DD Analog: amplifier V DD v IN v OUT v OUT v IN v IN v IN vin = VIN + vin t t v OUT v OUT vout = VOUT + vout t t Large swings i D t 1 t 2 t 3 t 4 t 1 t 2 t 1 i D Small variations around operating (bias) point t 3 t 4 v DS v DS 9
Small-signal models Capture only the deviation part around the bias point Operating point can also be called bias point or quiescent point 10
Small-signal model (1) Drain current is a function of terminal voltages (here three terminals, source terminal is reference) i D = i D (v GS,v DS ) Taylor expansion around operating (bias) point: i D I D + v GS @i D @v GS + v DS @i D @v DS 11
Small-signal model (2) Divide all currents and voltages into bias point and small-signal variations around it: i D = I D + i d, v GS = V GS + v gs, v DS = V DS + v ds Drain-current variation may be expressed as: i d = g m v gs + g d v ds where g m = i D v GS vgs =V GS g ds = i D v DS vds =V DS 12
Small-signal model Our task today: find expressions for the two small-signal parameters: transconductance: g m output conductance: g d 1 r o Question to ponder: when is a set of small-signal parameters valid? 13
Corresponding smallsignal schematic G D + + vgs gmvgs gd vds S 14
Simplest current equations Saturation region: I D = µc ox 2 W L (V GS V T ) 2 Linear region: I D = µc ox W L ((V GS V T )V DS V 2 DS 2 ) MOSFETS in amplifiers are usually biased in saturation 15
Transconductance (in saturation) I D = µc ox 2 W L (V GS V T ) 2 g m = I D V GS Find an expression for gm! Also, express gm as a function of ID and either VGS or W/L. 16
Transconductance (in saturation) I D = µc ox 2 W L (V GS V T ) 2 g m = I D V GS Effective gate voltage and drain current determine gm! g m = W g m = µc ox L (V GS V T ) 2I D W g m = 2µC ox V GS V T L I D 17
MOSFET output diagram w. second-order effects Figure from Weste and Harris
Extended current model Shockley s model in saturation: I D = µc ox 2 W L (V GS V T ) 2 With second-order effects: I D = µc ox 2 I D = µc ox 2 in saturation W L (V GS 19 V DS V GS V T V T ) 2 (1 + V DS V A ) or often written like this W L (V GS V T ) 2 (1 + V DS ) Weste & Harris section 2.4.2
Output conductance With second-order effects: I D = µc ox 2 W L (V GS V T ) 2 (1 + V DS V A ) Derive expression for output conductance If Early voltage can be written as rds L (where L is the transistor length) what expression do we get? 20 Weste & Harris section 2.4.2
Output conductance g d = I D = λ µc ox V DS 2 Lambda is inverse of Early voltage: g d = λi D = λ I D L Some books use r o W L (V GS V T ) 2 λi D = λ = I D V A = Early voltage I D r ds L for transistor output resistance Both are drawn as resistors in model! Note: Longer transistors are more like current generators (lower output conductance) L I D 21
Complete small-signal schematic at low frequencies G D + + S vgs gmvgs gd vds S _ B v bs + _
Early Voltage VA (example from bipolar transistor) Large VA is good! More like current source 23
DIBL and channel-length modulation (in 65-nm process) 24
Small-signal parameters important in analog design (derivatives of drain current w r t voltages). Transconductance, gm, is the desired one! Is determined by ratio of drain current (should be large) and effective gate voltage (should be small) Output conductance, gd, undesired (should be as small/large as possible) => make transistors long(er) for analog! pmos and nmos transistors have the same smallsignal model Conclusion ss transistor models
How to bias and find the gain for entire circuits 26
Common-source amplifier 5 x 10 5 4.5 4 3.5 Id Vds Vgs=0.5 Vgs=0.6 Vgs=0.7 Vgs=0.8 Vgs=0.9 Vgs= 1 Note the load line 3 Id [A] 2.5 2 1.5 1 0.5 3 Common Source stage 0 0 0.5 1 1.5 2 2.5 3 Vds [V] 3V 2.5 2 W L = 10µm 3µm R D =100kΩ v OUT V OUT [V] 1.5 1 v IN 0.5 0 0 0.5 1 1.5 V [V] IN
Operating (or bias or quiescent) point 3 3 Common Source stage 2.5 2.5 2 2 1.5 v OUT [V] 1.5 1 1 0.5 0.5 0 03V 0.5 1 time 0 0 0.5 1 1.5 v IN [V] W L = 10µm 3µm v IN R D = 100kΩ v OUT time 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5
Large signal - small signal 3 3 Common Source stage 2.5 2.5 2 2 1.5 v OUT [V] 1.5 1 1 0.5 0.5 0 0 3V 0.5 1 time 0 0 0.5 1 1.5 v [V] IN W L = 10µm 3µm v IN R D = 100kΩ v OUT time 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 29
Common-source stage voltage gain V IN V OUT V OUT V IN 30
Deriving a small-signal schematic All constant voltage sources are shorts (because there is 0 change in the voltage = no small-signal voltage ) thus both VDD and VSS are small-signal ground All constant current sources are cuts (because there is 0 change in the current = no small-signal current) Small-signal schematics for NMOS and PMOS transistors are identical 31
CS stage example 3V W L = 10µm 3µm v IN R D = 100kΩ v OUT Parameters for 0.35 μm process: VT = 0.5 V k n= 110 μa/v 2 VA =55 V/μm What VIN gives VOUT = 1.5 V? Draw the small-signal diagram What is the gain AV then? 32
CS stage solution (1) What VIN (=VGS) gives VOUT= VDD/2 = 1.5 V? ID is known from resistor loadline: ID = VDD/(2*RD) = 1.5V/100 kω =15 µa To find VIN (=VGT+VT) solve this equation for VGT: ID =k /2*W/L VGT 2 (1+VOUT/VA) 1.5 =110*10/(2*3)VGT 2 (1+1.5/165) VGT 2 =1.5/(183.3*1.009)=0.09 => VGT = 0.3 V => VIN = 0.8 V 33
Small-signal schematic for CS stage G D + + + v in v gs g m v gs R D Gain for CS stage: r o v out 3V W L = 10µm 3µm v IN R D = 100kΩ v OUT A v = v out R D r o = g m (R D r o )= g m v in R D + r o I D = V R D = 1.5V if VOUT is VDD/2 R L 100k = 15µA r o = V A I D = Lr0 ds I D = 3µm 55V/µm 15µA = 11M 34
Transconductance for CS stage g m = I D V GS = I D V G = I OUT V IN Turns input voltage change into output current change 35
CS stage intrinsic gain If load resistance RD is large (as for an ideal current source) G D + + + v in v gs g m v gs R D r o v out Find an expression for the small-signal gain: Av = vout/vin Use expressions for the small-signal parameters to find an expression for the gain where ID is eliminated 36
CS stage intrinsic gain If load resistance RD is large (as for an ideal current source) G D + + + v in v gs g m v gs R D A v = g m r o = g m g m A v 2I D V GS V T g d g d = I D V A = v out For high gain choose low overdrive voltage and long transistor! r o I D LV 0 A 2V A = 2LV A 0 V GS V T V GS V T Early voltage, VA, traditionally scales linearly with length L but not in 65 nm process. We must use VA given for each L 37
MOS-transistor output resistance r o = V DS I D = 1 I D V DS 0.35-um process 38
Useful circuit analysis tools Sources can be transformed using Norton/ Thevenin transformations For linear circuits (also small-signal schematics!) superposition holds: Effects of several independent sources can be calculated separately and added together Sometimes one source can be split into several to take advantage of superposition 39
What is bad with biasing with a resistor? Talk to your neighbor! 40
Common-source amplifier Id [A] 4.5 4 3.5 3 2.5 2 1.5 1 0.5 5 x 10 5 Id Vds Vgs=0.5 Vgs=0.6 Vgs=0.7 Vgs=0.8 Vgs=0.9 Vgs= 1 0 0 0.5 1 1.5 2 2.5 3 Vds [V] 3V 3 Common Source stage With RD the load line is straight: R = V*I With some other current source Ohm s law does not hold: draw the line for an ideal current source! W L = 10µm 3µm v IN R D =100kΩ v OUT V OUT [V] 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 V IN [V] 41
CS stage with active load Biasing gain transistor with current source 42
CS amplifier with active V DD V DD v in v gs g mn v gs r on v out V B load + + + r op v OUT A v = g mn (r on r op ) I B v IN r out = r on r op Main purpose of active load: decouple biasing of transistor and load output impedance 43
Current mirror Use: to copy and scale currents Design principle: i IN R L Design ONE very accurate reference current source Copy (and scale) this current over entire chip for biasing M 1 M 2 i OUT 44
Current-mirror operation 1. M1 diode-connected (drain connected to gate): When on, v GS1 >V T, always in saturation because: v DS1 = v GS1 =>v DS1 v GS1 V T 2. M2 same v GS as M1: v GS1 = v GS2 = v GS 3. When M2 in saturation, v DS2 v GS V T we have: i OUT i IN µc W 2 ox (V L = 2 GS V T ) 2 µc W 1 ox (V L 1 GS V T ) 2 = W 2 L 2 W 1 L 1 Note! this is not a small-signal gain 45
Conclusions common-source amplifier A v = v out v in = g m (R D r o )= g m R D r o R D + r o r in = r out = R D r o Intrinsic gain: A v = 2V A V GS V T = 2Lr ds V GS V T Active load decouples biasing of transistor and load output impedance 46
Summary Small-signal gain is derivative of VOUT vs VIN curve Transistor small-signal parameters are derivatives: transconductance: gm (want it high!) drain conductance: gd (want it low!) Longer transistor are more like current sources Intrinsic transistor gain does not depend on current: 2VA/VGT 47
Biasing the amplifying transistor without decreasing the gain is tricky: Biasing resistor limits gain of CS stage RD CMOS inverter has high(er) small-signal gain but is biased by VIN (very sensitive!) Common-source amplifier with active load: Load transistor acts as current source = sets the bias current for gain transistor Result: Bias (current IB) and output resistance of CS amplifier are decoupled Summary 48