Chapter 2 Switched-Capacitor Circuits

Similar documents
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Topic 4. The CMOS Inverter

System on a Chip. Prof. Dr. Michael Kraft

Discrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2)

Discrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2)

Master Degree in Electronic Engineering. Analog and Telecommunication Electronics course Prof. Del Corso Dante A.Y Switched Capacitor

Sample-and-Holds David Johns and Ken Martin University of Toronto

Design of Analog Integrated Circuits

MOS Transistor Theory

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Lecture 5: DC & Transient Response

Electronic Circuits Summary

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

Chapter 10 Feedback. PART C: Stability and Compensation

Lecture 4: DC & Transient Response

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

EE141Microelettronica. CMOS Logic

Chapter 4 Field-Effect Transistors

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

EEE598D: Analog Filter & Signal Processing Circuits

Advanced Current Mirrors and Opamps

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

Lecture 5: DC & Transient Response

5. CMOS Gate Characteristics CS755

Lecture 37: Frequency response. Context

Lecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters

Lecture 6: DC & Transient Response

Appendix A Butterworth Filtering Transfer Function

MOSFET and CMOS Gate. Copy Right by Wentai Liu

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm-1 Exam (Solution)

Name: Lab Partner: Section:

Sophomore Physics Laboratory (PH005/105)

ELEN 610 Data Converters

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

MOS Transistor Theory

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Power Dissipation. Where Does Power Go in CMOS?

EE5780 Advanced VLSI CAD

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

6.012 Electronic Devices and Circuits Spring 2005

EDEXCEL NATIONALS UNIT 5 - ELECTRICAL AND ELECTRONIC PRINCIPLES. ASSIGNMENT No.2 - CAPACITOR NETWORK

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Digital Electronic Circuits Homework #4

Switched Capacitor: Sampled Data Systems

CMOS Inverter (static view)

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices

University of Toronto. Final Exam

Physics Investigation 10 Teacher Manual

The Physical Structure (NMOS)

Homework Assignment 11

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Very Large Scale Integration (VLSI)

Lecture 7 Circuit Delay, Area and Power

Lecture 4: CMOS Transistor Theory

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

[1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. Fig. 1.1

E40M Capacitors. M. Horowitz, J. Plummer, R. Howe

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.

Digital Integrated Circuits A Design Perspective

Homework Assignment 08

ECE 546 Lecture 10 MOS Transistors

Capacitor Action. 3. Capacitor Action Theory Support. Electronics - AC Circuits

Exact Analysis of a Common-Source MOSFET Amplifier

MODULE III PHYSICAL DESIGN ISSUES

Fig. 1 Fig. 2. Calculate the total capacitance of the capacitors. (i) when connected as in Fig. 1. capacitance =... µf

CE/CS Amplifier Response at High Frequencies

Capacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

1 Introduction 1. 2 Elements of filter design 2. 3 FPAA technology Capacitor bank diagram Switch technology... 6

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Digital Integrated Circuits A Design Perspective

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

COMBINATIONAL LOGIC. Combinational Logic

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

Lecture 12 Circuits numériques (II)

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

DC and Transient Responses (i.e. delay) (some comments on power too!)

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

Lecture 2: CMOS technology. Energy-aware computing

High-to-Low Propagation Delay t PHL

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

Designing Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM.

Transcription:

Chapter 2 Switched-Capacitor Circuits Abstract his chapter introduces SC circuits. A brief description is given for the main building blocks of a SC filter (operational amplifiers, switches, capacitors, and non-overlapping clock phases). A few examples of SC resistor emulation circuits are presented along with their equivalent resistance. wo examples of SC integrators are also shown, one with the resistors implemented with a branch (parasitic-sensitive integrator) and another with a branch in π (parasitic-insensitive integrator). A signal flow graph is presented which allows large circuits to be analyzed graphically. he chapter ends with the two Sallen-Key topologies designed in this book, in their continuous time version. 2.1 Switched-Capacitor Filters Building Blocks SC filters can be implemented using switches, capacitors, opamps, and nonoverlapping clock generators. 2.1.1 Operational Amplifiers Opamps in SC circuits provide a virtual ground node. Parasitic capacitances connected to this node do not influence the performance of the circuit, since they will be connected to ground during one clock phase and to the virtual ground during the other. Opamps also have non-ideal effects that affect the performance of SC circuits like DC gain, unity gain frequency and phase margin, slew-rate, and common mode voltage. 2.1.2 Switches SC circuits require switches with high off resistance in order to minimize the charge leakage when the switches are open, and low on resistance so that the circuit can settle in less than half a clock period. MOSFE transistors satisfy both these requirements, since they have very high off resistance and low on resistance (GΩ and kω, Springer International Publishing Switzerland 2015 3 H. A. de A. Serra, N. Paulino, Design of Switched-Capacitor Filter Circuits using Low Gain Amplifiers, SpringerBriefs in Electrical and Computer Engineering, DOI 10.1007/978-3-319-11791-1_2

4 2 Switched-Capacitor Circuits Fig. 2.1 Example of MOS transistors r ds resistance as function of the V in (V s ) voltage Fig. 2.2 NMOS switch model considering source and drain parasitic capacitances respectively), depending on the transistors size. Increasing the width of the transistor will decrease the value of both of these resistances. Switches can be implemented using NMOS transistors, PMOS transistors, or both in parallel (transmission gate). Using both in parallel will decrease not only the resistance value of the switch but also improve its linearity (Fig. 2.1). While NMOS transistors are better at conducting lower voltages (logic value 0 ) since they stop conducting when the input voltage is close to V DD V tn, PMOS transistors are better at conducting higher voltages (logic value 1 ) since they do not conduct until the voltage is higher than V tp. ransmission gates are good at transmitting 0 s and 1 s since lower voltages will travel via the NMOS transistor and higher voltages will travel via the PMOS transistor. Depending on the SC circuit, it may be necessary to consider the switch model including parasitics (Fig. 2.2), since they may influence the transfer function of the SC filter. Examples of SC networks that are sensitive and insensitive to these parasitic capacitances are given in Sect. 2.2. While the resistance of a switch will decrease with the increase in size of the switch, the parasitic capacitances increases. It is important to note that the parasitic capacitances of a MOS transistor are non-linear, i.e., their value varies with the applied voltage value.

2.2 Switched-Capacitor Resistor Emulation Networks 5 Fig. 2.3 wo-phase clock generator 2.1.3 Capacitors Capacitors are another element for which, depending on the SC network used, it may be necessary to consider the parasitic capacitances. he bottom plate parasitic capacitance can be as high as 20 % of the capacitance value, while the top plate parasitic capacitance can be as high as 5 % [1]. 2.1.4 Non-Overlapping Clock Phases he switches present in SC circuits require at least a pair of non-overlapping clock phases to preform the charge transfer. It is required that the phases do not overlap, so that no charge is accidentally lost by having two switches closed at the same time. An example of a two-phase clock generator is shown in Fig. 2.3. 2.2 Switched-Capacitor Resistor Emulation Networks SC circuits emulate resistors using a combination of switches and capacitors. In order to obtain the equivalent resistance it is necessary to first calculate the average current value that flows from the input into the circuit. Considering the parallel network (able 2.1), in which the input current only flows into the circuit during half a period (0 t /2), i rms = 1 /2 0 i C (t)dt (2.1) Since the relation between charge and current is i(t) = dq(t)/dt, i rms = 1 /2 0 dq C (t) = Q C(/2) Q C (0) (2.2) Considering the phase scheme shown in Fig. 2.4, and that at t = 0 the capacitor maintains the voltage from the last phase, then at t = 0 = phase 2 is active and at t = /2 phase 1 is active.

6 2 Switched-Capacitor Circuits Fig. 2.4 Non-overlapping clock phase scheme Using the charge values presented in able 2.1 for the parallel network, i rms = (V in V out )C (2.3) Considering that the average current that flows through the resistance, i rms = V in V out R (2.4) By equating both equations (Eqs. 2.3 and 2.4) the equivalent resistance for the parallel network is obtained. R eq = C (2.5) For the networks where the current flows into the network in both phases (seriesparallel and bilinear), the average current calculation must contemplate both phases. For the series-parallel network (able 2.1), i rms = 1 ( /2 0 = Q C 2 (/2) Q C2 (0) ) dq C2 (t) + dq C1 (t) /2 + Q C 1 ( ) Q C1 (/2) (2.6) Replacing the charge variables with the corresponding values that are shown in able 2.1, i rms = (V in V out )C 2 + (V in V out )C 1 0 (2.7) and by equating Eqs. 2.7 and 2.4, the equivalent resistance for the series-parallel network is obtained. R eq = C 1 + C 2 (2.8) able 2.1 shows a few examples of circuits that can emulate resistors, their equivalent resistance, and the charge in the capacitor(s) in each phase.

2.2 Switched-Capacitor Resistor Emulation Networks 7 able 2.1 SC resistor emulation circuits [5] Circuit Schematic R eq Q(φ 1 ) Q(φ 2 ) Parallel C V in C V out C Series C 0 (V in V out )C Series-Parallel C 1 +C 2 0 V in C 2 (V in V out )C 1 V out C 2 Bilinear 1 4 C (V in V out )C (V out V in )C Fig. 2.5 Switched-capacitor parasitic-sensitive integrator 2.2.1 Parasitic-Sensitive Integrator he SC parasitic-sensitive integrator (Fig. 2.5) was suggested in [6] by replacing the resistor in a Miller integrator with a parallel switch network. Analyzing the charge across the capacitors in each phase, and considering that the output of the circuit will be sampled at the end of phase φ 1, able 2.2 is obtained. Capacitance C p1 represents the top plate parasitic capacitance of C R1 and the parasitic

8 2 Switched-Capacitor Circuits able 2.2 Charge in the capacitors in each phase (n 1) (n 0.5) n Q CR1 V in [(n 1) ]C R1 0 V in [n ]C R1 Q C1 V out [(n 1) ]C 1 V out [(n 0.5) ]C 1 V out [n ]C 1 Q Cp1 V in [(n 1) ]C p1 0 V in [n ]C p1 Q Cp2 0 0 0 Q Cp3 0 0 0 Q Cp4 V out [(n 1) ]C p4 V out [(n 0.5) ]C p4 V out [n ]C p4 capacitances of both switches; capacitance C p2 represents the bottom plate parasitic capacitance of C R1 ; capacitance C p3 represents the top plate parasitic capacitance of C 1, the input capacitance of the opamp, and the parasitic capacitance of switch φ 2 ; capacitance C p4 represents the bottom plate parasitic capacitance of C 1 and the input capacitance of the following stage. Considering the transition (n 1) (n 0.5) (φ 1 φ 2 ) and the transition (n 0.5) (n) (φ 2 φ 1 ), Eq. 2.9 is obtained from adding all the capacitors that are connected to the virtual ground at the end of that transition (φ 2 in the first case and φ 1 in the second). [(n 1) ] [(n 0.5) ]:V in [(n 1) ](C R1 + C p1 ) V out [(n 1) ]C 1 = = V out [(n 0.5) ]C 1 [(n 0.5) ] [n ]: V out [(n 0.5) ]C 1 = V out [n ]C 1 (2.9) Combining both equations in Eq. 2.9 and using the Z-ransform, the transfer function in Eq. 2.10 is obtained. H (z) = V ( out CR1 + C )( p1 z 1 ) = V in C 1 1 z 1 (2.10) aking into the account the parasitic capacitance, it can be seen that the gain coefficient of this circuit is dependent on C p1. From the calculations it can also be concluded that the parasitic capacitance C p3 does not influence the performance of the circuit due to the virtual ground node in the negative node of the opamp. 2.2.2 Parasitic-Insensitive Integrator o overcome the nonlinear effect of the parasitic capacitance C p1, new parasiticinsensitive structures were developed [7]. Figure 2.6 shows one of these structures. Analyzing the charge across the capacitors in each phase, and considering that the output of the circuit will again be sampled at the end of phase φ 1, able 2.3

2.2 Switched-Capacitor Resistor Emulation Networks 9 Fig. 2.6 Switched-capacitor parasitic-insensitive integrator able 2.3 Charge in the capacitors in each phase (n 1) (n 0.5) n Q CR1 V in [(n 1) ]C R1 0 V in [n ]C R1 Q C1 V out [(n 1) ]C 1 V out [(n 0.5) ]C 1 V out [n ]C 1 Q Cp1 V in [(n 1) ]C p1 0 V in [n ]C p1 Q Cp2 0 0 0 Q Cp3 0 0 0 Q Cp4 V out [(n 1) ]C p4 V out [(n 0.5) ]C p4 V out [n ]C p4 is obtained. Capacitance C p1 represents the bottom plate parasitic capacitance of C R1 and the parasitic capacitances of the switches connected to the bottom plate of C R1 ; capacitance C p2 represents the top plate parasitic capacitance of C R1 and the parasitic capacitances of the switches connected to the top plate of C R1 ; capacitance C p3 represents the top plate parasitic capacitance of C 1, the input capacitance of the opamp, and the parasitic capacitance of switch connected to the top plate of C 1 ; capacitance C p4 represents the bottom plate parasitic capacitance of C 1 and the input capacitance of the following stage. Considering the transition (n 1) (n 0.5) (φ 1 φ 2 ) and the transition (n 0.5) (n) (φ 2 φ 1 ), Eq. 2.11 is obtained from adding all the capacitors that are connected to the virtual ground at the end of that transition (φ 2 in the first case and φ 1 in the second). [(n 1) ] [(n 0.5) ]: V in [(n 1) ]C R1 V out [(n 1) ]C 1 = = V out [(n 0.5) ]C 1 [(n 0.5) ] [n ]: V out [(n 0.5) ]C 1 = V out [n ]C 1 (2.11) Combining both equations in Eq. 2.11 and using the Z-ransform, the transfer function in Eq. 2.12 is obtained. H (z) = V ( out CR1 )( = V in C 1 z 1 ) 1 z 1 (2.12)

10 2 Switched-Capacitor Circuits Fig. 2.7 Four-input switched-capacitor summing/integrator stage From the calculations it can be concluded that with the addition of these two new switches the parasitic capacitances in this circuit do not influence its performance, improving the linearity of the circuit and the accuracy of the transfer function. he parasitic capacitances have little effect on the circuit since they are connected to the virtual ground (C p2 and C p3 ) or the physical ground (C p2 ). C p4 also has little effect since it is driven by the circuits output. Although C p1 is charged by the input voltage during clock phase φ 1, it does not affect the charge in capacitor C R1 since the time constant RC is long enough to charge the capacitors in less than half the clocks period, and during clock phase φ 2 it is discharged to ground via the φ 2 switch, not influencing the charge that is being transferred to C 1. Although the parasitic capacitances do not influence the circuits transfer function, they do increase the time constant RC making the settling time slower. 2.2.3 Signal Flow Graph Analysis Using the superposition principle it is possible to determine the charge transfer functions of large circuits by analyzing the circuits graphically. Figure 2.7 shows an example of a circuit with several inputs [1]. his circuit can be analyzed using the same process as in the previous two examples. able 2.4 shows the charge across the capacitors.

2.3 Sallen-Key opology 11 able 2.4 Charge in the capacitors in each phase (n 1) (n 0.5) n Q Cf V out [(n 1) ]C f V out [(n 0.5) ]C f V out [n ]C f Q C1 V 1 [(n 1) ]C 1 V 1 [(n 0.5) ]C 1 V 1 [n ]C 1 Q C2 V 2 [(n 1) ]C 2 0 V 2 [n ]C 2 Q C3 V 3 [(n 1) ]C 3 0 V 3 [n ]C 3 Q C4 V 4 [(n 1) ]C 4 0 V 4 [n ]C 4 Fig. 2.8 Equivalent signal flow graph of Fig. 2.7 circuit Analyzing the charge values in able 2.4 individually, it is possible to obtain the charge transfer function of each subcircuit individually. hese results will make it easier to analyze large circuits once the subcircuits are identified. he results of each subcircuit in Fig. 2.7 are shown in Fig. 2.8. he signal flow graph (SFG) can be analyzed and the circuits transfer function is obtained. V out (z) = C 1 C f V 1 (z) + C 2 C f z 1 1 z 1 V 2(z) C 3 C f 1 1 z 1 V 3(z) C 4 C f z 1 1 z V 4(z) 1 (2.13) 2.3 Sallen-Key opology he SC low-pass and band-pass filters implemented in this book are based on the continuous time Sallen-Key second-order filters. In this section these topologies are presented and discussed.

12 2 Switched-Capacitor Circuits Fig. 2.9 Continuous-time Sallen-Key low-pass filter using an amplifier with gain G [8] 2.3.1 Low-Pass Sallen-Key opology he basis for the SC low-pass filter is the Sallen-Key low-pass filter. his filter is shown in Fig. 2.9. One of the characteristics of this type of filter is the opamp being configured as an amplifier instead of an integrator, reducing the gain-bandwidth requirements for the opamp. his means that when using this topology it is possible to implement higher frequency filters with lower gain when compared to other topologies. Another advantage of this filter is the low ratio between largest and lowest resistor/capacitor, which is important for manufacturability. At low frequencies the capacitors can be seen as open circuits and the signal is transferred from the input to the output. At high frequency the capacitors can be seen short circuits and the signal is discharged to ground. he transfer function of this second-order filter is shown in Eq. 2.14. H (s) = V out G = V in 1 + (C 1 R 1 + C 2 R 1 GC 1 R 1 + C 2 R 2 )s + (C 1 C 2 R 1 R 2 )s 2 (2.14) Knowing that the transfer function of second order systems is H (s) = G ω 2 p s 2 + ω p Q p s + ω 2 p (2.15) Using Eqs. 2.14 and 2.15, the pole frequency ω p is ω p = 1 C1 C 2 R 1 R 2 (2.16) the inverse of the quality factor 1 C 1 R 1 C 2 R 1 C 2 R 2 = (1 G) + + (2.17) Q p C 2 R 2 C 1 R 2 C 1 R 1

2.3 Sallen-Key opology 13 Fig. 2.10 Continuous-time Sallen-Key band-pass filter and the low frequency gain H (0) = G (2.18) Using these equations and selecting two of the five unknown variables it is possible to size the values of the components of the filter circuit. 2.3.2 Band-Pass Sallen-Key opology he basis for the SC band-pass filter is the Sallen-Key band-pass filter implemented with a voltage controlled voltage source (VCVS). he limitation of this topology is that the quality factor of the filter will determine the gain required for the amplifier. his filter is shown in Fig. 2.10. he transfer function of this second-order filter is shown in Eq. 2.19. H (s) = GC 2 R 2 R f s R 1 + R f + (C 1 R 1 R f + C 2 R f (R 1 + R 2 ) C 2 R 1 R 2 (G 1))s + C 1 C 2 R 1 R 2 R f s 2 (2.19) Where the pole frequency is R 1 + R f ω p = (2.20) C 1 C 2 R 1 R 2 R f and the inverse of the quality factor 1 Q p = C 1R 1 R f + C 2 R f (R 1 + R 2 ) C 2 R 1 R 2 (G 1) (R1 + R f )C 1 C 2 R 1 R 2 R f (2.21)

http://www.springer.com/978-3-319-11790-4

2024 © sciencedocbox.com Privacy Policy | Terms of Service | Feedback