Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 2 Circuit Optimization

Similar documents
Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits

DIGITAL ELECTRONICS & it0203 Semester 3

Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 1 Gate Circuits and Boolean Equations

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid

Textbook: Digital Design, 3 rd. Edition M. Morris Mano

Chap 2. Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits

Chapter 3 Combinational Logic Design

Possible logic functions of two variables

Goals for Lecture. Binary Logic and Gates (MK 2.1) Binary Variables. Notation Examples. Logical Operations

UNIT 5 KARNAUGH MAPS Spring 2011

K-map Definitions. abc

Number System conversions

Combinational Logic (mostly review!)

ECE/Comp Sci 352 Digital System Fundamentals Quiz # 1 Solutions

Simplifying Logic Circuits with Karnaugh Maps

Why digital? Overview. Number Systems. Binary to Decimal conversion

Unit 2 Session - 6 Combinational Logic Circuits

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا

Chapter 4 Optimized Implementation of Logic Functions

Digital Fundamentals

Chapter 2 Combinational Logic Circuits

ﻮﻧﺭﺎﮐ ﺔﺸﻘﻧ ﺎﺑ ﻱﺯﺎﺳ ﻪﻨﻴﻬﺑ

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

This form sometimes used in logic circuit, example:

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps

Karnaugh Maps Objectives

Chapter 2 Part 7 Combinational Logic Circuits

Boolean cubes EECS150. Mapping truth tables onto cubes. Simplification. The Uniting Theorem. Three variable example

211: Computer Architecture Summer 2016

II. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):

Chapter 2 Combinational

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Learning Objectives. Boolean Algebra. In this chapter you will learn about:

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

Lecture 5. Karnaugh-Map

12/31/2010. Overview. 05-Boolean Algebra Part 3 Text: Unit 3, 7. DeMorgan s Law. Example. Example. DeMorgan s Law

ENG2410 Digital Design Combinational Logic Circuits

Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).

Lecture 7: Karnaugh Map, Don t Cares

SIMPLIFICATION OF BOOLEAN ALGEBRA. Presented By: Ms. Poonam Anand

Minimization techniques

UNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY

ELCT201: DIGITAL LOGIC DESIGN

ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #2

ELC224C. Karnaugh Maps

Combinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions.

Boolean Algebra and Logic Simplification

Boolean Algebra. Boolean Variables, Functions. NOT operation. AND operation. AND operation (cont). OR operation

CMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification

Digital Logic Design. Combinational Logic

ELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3)

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

EC-121 Digital Logic Design

Chapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction

COMP2611: Computer Organization. Introduction to Digital Logic

CS/EE 181a 2008/09 Lecture 4

Working with Combinational Logic. Design example: 2x2-bit multiplier

Contents. Chapter 3 Combinational Circuits Page 1 of 36

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

12/31/2010. Overview. 10-Combinational Circuit Design Text: Unit 8. Limited Fan-in. Limited Fan-in. Limited Fan-in. Limited Fan-in

EE 110 Practice Problems for Exam 1: Solutions, Fall 2008

Optimizations and Tradeoffs. Combinational Logic Optimization

ELEC Digital Logic Circuits Fall 2014 Logic Minimization (Chapter 3)

Combinational Logic Circuits Part II -Theoretical Foundations

Digital- or Logic Circuits. Outline Logic Circuits. Logic Voltage Levels. Binary Representation

WEEK 3.1 MORE ON KARNAUGH MAPS

Lecture 4: More Boolean Algebra

CHAPTER III BOOLEAN ALGEBRA

Introduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps

Karnaugh Map & Boolean Expression Simplification

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates

CHAPTER III BOOLEAN ALGEBRA

MC9211 Computer Organization

Karnaugh Maps (K-Maps)

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

Chapter 7 Logic Circuits

L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES

Chapter 2: Princess Sumaya Univ. Computer Engineering Dept.

L2: Combinational Logic Design (Construction and Boolean Algebra)

Week-I. Combinational Logic & Circuits

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Simlification of Switching Functions

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

Signals and Systems Digital Logic System

Theorem/Law/Axioms Over (.) Over (+)

Chapter 2 Boolean Algebra and Logic Gates

CHAPTER 5 KARNAUGH MAPS

Gate-Level Minimization

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

CHAPTER 7. Solutions for Exercises

Boolean Algebra & Logic Gates. By : Ali Mustafa

3. PRINCIPLES OF COMBINATIONAL LOGIC

Combinational Logic Design

Logic. Basic Logic Functions. Switches in series (AND) Truth Tables. Switches in Parallel (OR) Alternative view for OR

L2: Combinational Logic Design (Construction and Boolean Algebra)

Slide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Transcription:

Logic and omputer Design Fundamentals hapter 2 ombinational Logic ircuits Part 2 ircuit Optimization harles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Part Gate ircuits and oolean Equations inary Logic and Gates oolean lgebra Standard Forms Part 2 ircuit Optimization Two-Level Optimization Map Manipulation Practical Optimization (Espresso) Multi-Level ircuit Optimization Part 3 dditional Gates and ircuits Other Gate Types Eclusive-OR Operator and Gates High-Impedance Outputs hapter 2 - Part 2 2

ircuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm Optimization requires a cost criterion to measure the simplicity of a circuit Distinct cost criteria we will use: Literal cost (L) Gate input cost (G) Gate input cost with NOTs (GN) hapter 2 - Part 2 3 Literal ost Literal a variable or it complement Literal cost the number of literal appearances in a oolean epression corresponding to the logic circuit diagram Eamples: F = D + + D L = 8 F = D + + D + L = F = ( + )( + D)( + + D)( + + D) L = Which solution is best? hapter 2 - Part 2 4 2

Gate Input ost Gate input costs - the number of inputs to the gates in the implementation corresponding eactly to the given equation or equations. (G - inverters not counted, GN - inverters counted) For SOP and POS equations, it can be found from the equation(s) by finding the sum of: all literal appearances the number of terms ecluding single literal terms,(g) and optionally, the number of distinct complemented single literals (GN). Eample: F = D + + D G = 8, GN = F = D + + D + G =, GN = F = ( + )( + D)( + + D)( + + D) G =, GN = Which solution is best? hapter 2 - Part 2 5 ost riteria (continued) Eample : GN F = + + L = = 5 G + 2 = 9 G = L + 2 = 7 F L (literal count) counts the ND inputs and the single literal OR input. G (gate input count) adds the remaining OR gate inputs GN(gate input count with NOTs) adds the inverter inputs hapter 2 - Part 2 6 3

ost riteria (continued) Eample 2: F = + L = 6 G = 8 GN = F = ( + )( + )( + ) L = 6 G = 9 GN = 2 Same function and same literal cost ut first circuit has better gate input count and better gate input count with NOTs Select it! F F hapter 2 - Part 2 7 oolean Function Optimization Minimizing the gate input (or literal) cost of a (a set of) oolean equation(s) reduces circuit cost. We choose gate input cost. oolean lgebra and graphical techniques are tools to minimize cost criteria values. Some important questions: When do we stop trying to reduce the cost? Do we know when we have a minimum cost? Treat optimum or near-optimum cost functions for two-level (SOP and POS) circuits first. Introduce a graphical technique using Karnaugh maps (K-maps, for short) hapter 2 - Part 2 8 4

Karnaugh Maps (K-map) K-map is a collection of squares Each square represents a minterm The collection of squares is a graphical representation of a oolean function djacent squares differ in the value of one variable lternative algebraic epressions for the same function are derived by recognizing patterns of squares The K-map can be viewed as reorganized version of the truth table topologically-warped Venn diagram as used to visualize sets in algebra of sets hapter 2 - Part 2 9 Some Uses of K-Maps Provide a means for: Finding optimum or near optimum SOP and POS standard forms, and two-level ND/OR and OR/ND circuit implementations for functions with small numbers of variables Visualizing concepts related to manipulating oolean epressions, and Demonstrating concepts used by computeraided design programs to simplify large circuits hapter 2 - Part 2 0 5

Two Variable Maps 2-variable Karnaugh Map: Note that minterm m0 and minterm m are adjacent and differ in the value of the variable y Similarly, minterm m0 and minterm m2 differ in the variable. y = 0 y = = 0 m 0 = m = y y = m 2 = m 3 = y y lso, m and m3 differ in the variable as well. Finally, m2 and m3 differ in the value of the variable y hapter 2 - Part 2 K-Map and Truth Tables The K-Map is just a different form of the truth table. Eample Two variable function: We choose a,b,c and d from the set {0,} to implement a particular function, F(,y). Function Table K-Map Input Values (,y) Function Value F(,y) 0 0 a 0 b 0 c d y = 0 y = = 0 a b = c d hapter 2 - Part 2 2 6

K-Map Function Representation Eample: F(,y) = F = y = 0 y = = 0 0 0 = For function F(,y), the two adjacent cells containing s can be combined using the Minimization Theorem: F (, y) = y + y = hapter 2 - Part 2 3 K-Map Function Representation Eample: G(,y) = + y G = +y y = 0 y = = 0 0 = For G(,y), two pairs of adjacent cells containing s can be combined using the Minimization Theorem: ( y + y) + ( y + y) = y G (, y) = + Duplicate y hapter 2 - Part 2 4 7

Three Variable Maps three-variable K-map: yz=00 yz=0 yz= yz=0 =0 m 0 m m 3 m 2 = m 4 m 5 m 7 m 6 Where each minterm corresponds to the product terms: yz=00 yz=0 yz= yz=0 =0 = y z y z y z y z y z y z Note that if the binary value for an inde differs in one bit position, the minterms are adjacent on the K-Map y z y z hapter 2 - Part 2 5 lternative Map Labeling Map use largely involves: Entering values into the map, and Reading off product terms from the map. lternate labelings are useful: z y 0 3 2 4 z y 5 7 6 z y z 4 z y 0 0 3 2 00 0 0 5 7 6 hapter 2 - Part 2 6 8

Eample Functions y convention, we represent the minterms of F by a "" in the map and leave the minterms of F blank Eample: y F(, y, z) = Σ m (2,3,4,5) 4 Eample: G(a, b,c) = Σm(3,4,6,7) Learn the locations of the 8 indices based on the variable order shown (, most significant and z, least significant) on the map boundaries 0 3 2 5 7 6 z y 0 3 2 4 5 7 6 z hapter 2 - Part 2 7 ombining Squares y combining squares, we reduce number of literals in a product term, reducing the literal cost, thereby reducing the other two cost criteria On a 3-variable K-Map: One square represents a minterm with three variables Two adjacent squares represent a product term with two variables Four adjacent terms represent a product term with one variable Eight adjacent terms is the function of all ones (no variables) =. hapter 2 - Part 2 8 9

Eample: ombining Squares Eample: Let F = Σm(2,3,6,7) pplying the Minimization Theorem three times: F (, y, z) = y z + y z + y z + y z = yz + yz = y Thus the four terms that form a 2 2 square correspond to the term "y". y 0 3 2 4 5 7 6 z hapter 2 - Part 2 9 Three-Variable Maps Reduced literal product terms for SOP standard forms correspond to rectangles on K-maps containing cell counts that are powers of 2. Rectangles of 2 cells represent 2 adjacent minterms; of 4 cells represent 4 minterms that form a pairwise adjacent ring. Rectangles can contain non-adjacent cells as illustrated by the pairwise adjacent ring above. hapter 2 - Part 2 20 0

Three-Variable Maps Topological warps of 3-variable K-maps that show all adjacencies: Venn Diagram ylinder 0 Y 4 6 7 5 2 3 Z hapter 2 - Part 2 2 Three-Variable Maps Eample Shapes of 2-cell Rectangles: y 0 3 2 4 5 7 6 z Read off the product terms for the rectangles shown hapter 2 - Part 2 22

Three-Variable Maps Eample Shapes of 4-cell Rectangles: y 0 3 2 4 5 7 6 Read off the product terms for the rectangles shown z hapter 2 - Part 2 23 Three Variable Maps K-Maps can be used to simplify oolean functions by systematic methods. Terms are selected to cover the s in the map. Eample: Simplify F(, y, z) = Σm(,2,3,5,7) z y y z F(, y, z) = z + y hapter 2 - Part 2 24 2

Three-Variable Map Simplification Use a K-map to find an optimum SOP equation for F(, Y, Z) = Σm(0,,2,4,6,7) hapter 2 - Part 2 25 Four Variable Maps Map and location of minterms: Y 0 3 2 Variable Order W 5 6 4 7 2 3 5 4 8 9 0 Z hapter 2 - Part 2 26 3

Four Variable Terms Four variable maps can have rectangles corresponding to: single = 4 variables, (i.e. Minterm) Two s = 3 variables, Four s = 2 variables Eight s = variable, Siteen s = zero variables (i.e. onstant "") hapter 2 - Part 2 27 Four-Variable Maps Eample Shapes of Rectangles: Y 0 3 2 4 5 7 6 W 2 3 5 4 8 9 0 Z hapter 2 - Part 2 28 4

Four-Variable Maps Eample Shapes of Rectangles: Y 0 3 2 W 4 5 7 6 2 3 5 4 8 9 0 Z hapter 2 - Part 2 29 Four-Variable Map Simplification F(W,, Y, Z) = Σm(0, 2,4,5,6,7,8,0,3,5) hapter 2 - Part 2 30 5

Four-Variable Map Simplification F(W,, Y, Z) = Σm(3,4,5,7,9,3,4,5) hapter 2 - Part 2 3 Systematic Simplification Prime Implicant is a product term obtained by combining the maimum possible number of adjacent squares in the map into a rectangle with the number of squares a power of 2. prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers (includes) one or more minterms. Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map. set of prime implicants "covers all minterms" if, for each minterm of the function, at least one prime implicant in the set of prime implicants includes the minterm. hapter 2 - Part 2 32 6

Eample of Prime Implicants D D Find LL Prime Implicants D D D ESSENTIL Prime Implicants D D D Minterms covered by single prime implicant hapter 2 - Part 2 33 Prime Implicant Practice Find all prime implicants for: F(,,, D) = Σ m (0,2,3,8,9,0,,2,3,4,5) hapter 2 - Part 2 34 7

nother Eample Find all prime implicants for: G(,,, D) = Σm(0,2,3,4,7,2,3,4,5) Hint: There are seven prime implicants! hapter 2 - Part 2 35 Five Variable or More K-Maps For five variable problems, we use two adjacent K-maps. It becomes harder to visualize adjacent minterms for selecting PIs. You can etend the problem to si variables by using four K-Maps. V = 0 V = Y Y W W Z Z hapter 2 - Part 2 36 8

Don't ares in K-Maps Sometimes a function table or map contains entries for which it is known: the input values for the minterm will never occur, or The output value for the minterm is not used In these cases, the output value need not be defined Instead, the output value is defined as a don't care y placing don't cares ( an entry) in the function table or map, the cost of the logic circuit may be lowered. Eample : logic function having the binary codes for the D digits as its inputs. Only the codes for 0 through 9 are used. The si codes, 00 through never occur, so the output values for these codes are to represent don t cares. hapter 2 - Part 2 37 Don't ares in K-Maps Eample 2: circuit that represents a very common situation that occurs in computer design has two distinct sets of input variables:,, and which take on all possible combinations, and Y which takes on values 0 or. and a single output Z. The circuit that receives the output Z observes it only for combinations of,, and such = and = or = 0, otherwise ignoring it. Thus, Z is specified only for those combinations, and for all other combinations of,, and, Z is a don t care. Specifically, Z must be specified for + =, and is a don t care for : + = ( + ) = + = Ultimately, each don t care entry may take on either a 0 or value in resulting solutions For eample, an may take on value 0 in an SOP solution and value in a POS solution, or vice-versa. ny minterm with value need not be covered by a prime implicant. hapter 2 - Part 2 38 9

Eample: D 5 or More w The map below gives a function F(w,,y,z) which is defined as "5 or more" over D inputs. With the don't cares used for the 6 non-d combinations: y F (w,,y,z) = w + z + y G = 7 0 3 2 This is much lower in cost than F2 where the don't cares were treated as "0s." 4 5 7 6 F 2 (w,,y, z) = w z + w y + w y 0 0 0 0 0 2 3 5 4 8 9 0 z G = 2 For this particular function, cost G for the POS solution for F (w,,y,z) is not changed by using the don't cares. hapter 2 - Part 2 39 Product of Sums Eample Find the optimum POS solution: F(,,, D) = Σm (3,9,,2,3,4,5) + Σd (,4,6) Hint: Use F and complement it to get the result. hapter 2 - Part 2 40 20

Optimization lgorithm Find all prime implicants. Include all essential prime implicants in the solution Select a minimum cost set of non-essential prime implicants to cover all minterms not yet covered: Obtaining an optimum solution: See Reading Supplement - More on Optimization Obtaining a good simplified solution: Use the Selection Rule hapter 2 - Part 2 4 Prime Implicant Selection Rule Minimize the overlap among prime implicants as much as possible. In particular, in the final solution, make sure that each prime implicant selected includes at least one minterm not included in any other prime implicant selected. hapter 2 - Part 2 42 2

Selection Rule Eample Simplify F(,,, D) given on the K- map. Selected Essential D Minterms covered by essential prime implicants D hapter 2 - Part 2 43 Selection Rule Eample with Don't ares Simplify F(,,, D) given on the K-map. Selected Essential D Minterms covered by essential prime implicants D hapter 2 - Part 2 44 22

Practical Optimization Problem: utomated optimization algorithms: require minterms as starting point, require determination of all prime implicants, and/or require a selection process with a potentially very large number of candidate solutions to be found. Solution: Suboptimum algorithms not requiring any of the above in the general case hapter 2 - Part 2 45 Eample lgorithm: Espresso Illustration on a K-map: D Original F & EPND D ESSENTIL & IRREDUNDNT OVER hapter 2 - Part 2 46 23

Eample lgorithm: Espresso ontinued: D REDUE D EPND hapter 2 - Part 2 47 Eample lgorithm: Espresso ontinued: D IRREDUNDNT OVER D fter REDUE, EPND, IRREDUNDNT OVER, LST GSP, QUIT hapter 2 - Part 2 48 24

Eample lgorithm: Espresso This solution costs 2 + 2 + 3 + 3 + 4 = 4 Finding the optimum solution and comparing: Essential Selected Minterms covered by essential prime implicants D There are two optimum solutions one of which is the one obtained by Espresso. hapter 2 - Part 2 49 Multiple-Level Optimization Multiple-level circuits - circuits that are not two-level (with or without input and/or output inverters) Multiple-level circuits can have reduced gate input cost compared to two-level (SOP and POS) circuits Multiple-level optimization is performed by applying transformations to circuits represented by equations while evaluating cost hapter 2 - Part 2 50 25

Transformations Factoring - finding a factored form from SOP or POS epression lgebraic - No use of aioms specific to oolean algebra such as complements or idempotence oolean - Uses aioms unique to oolean algebra Decomposition - epression of a function as a set of new functions hapter 2 - Part 2 5 Transformations (continued) Substitution of G into F - epression function F as a function of G and some or all of its original variables Elimination - Inverse of substitution Etraction - decomposition applied to multiple functions simultaneously hapter 2 - Part 2 52 26

Transformation Eamples lgebraic Factoring F = D + + + D G = 6 Factoring: F = ( D + ) + ( + D ) G = 6 Factoring again: F = ( + D ) + ( + D ) G = 2 Factoring again: F = ( + ) ( + D) G = 0 hapter 2 - Part 2 53 Transformation Eamples Decomposition The terms + Dand + can be defined as new functions E and H respectively, decomposing F: F = E H, E = + D, and H = + G = 0 This series of transformations has reduced G from 6 to 0, a substantial savings. The resulting circuit has three levels plus input inverters. hapter 2 - Part 2 54 27

Transformation Eamples Substitution of E into F Returning to F just before the final factoring step: F = ( + D) + ( + D) G = 2 Defining E = + D, and substituting in F: F = E + E G = 0 This substitution has resulted in the same cost as the decomposition hapter 2 - Part 2 55 Transformation Eamples Elimination eginning with a new set of functions: = + Y = + Z = + Y G = 0 Eliminating and Y from Z: Z = ( + ) + ( + ) G = 0 Flattening (onverting to SOP epression): Z = + + + G = 2 This has increased the cost, but has provided an new SOP epression for two-level optimization. hapter 2 - Part 2 56 28

Transformation Eamples Two-level Optimization The result of 2-level optimization is: Z = + G = 4 This eample illustrates that: Optimization can begin with any set of equations, not just with minterms or a truth table Increasing gate input count G temporarily during a series of transformations can result in a final solution with a smaller G hapter 2 - Part 2 57 Transformation Eamples Etraction eginning with two functions: E = D + D H = D + D G = 6 Finding a common factor and defining it as a function: F = D + D We perform etraction by epressing E and H as the three functions: F = D + D, E = F, H = F G = 0 The reduced cost G results from the sharing of logic between the two output functions hapter 2 - Part 2 58 29

Terms of Use ll (or portions) of this material 2008 by Pearson Education, Inc. Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and omputer Design Fundamentals as the course tetbook. These materials or adaptations thereof are not to be sold or otherwise offered for consideration. This Terms of Use slide or page is to be included within the original materials or any adaptations thereof. hapter 2 - Part 2 59 30