MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small signal dynamic model when the rate of change of bias with time is small so that the device is represented by resistors capacitors current sources, and so on large-signal dynamic model when the rate of change of bias with time is large and the device is represented by analytical nonlinear model capacitors. HO #18: ELEN 51 - MOS Cap Models Page 1
MOSFET Capacitance Model Both types of dynamic operations are influenced by the capacitive effects of the device. Thus, a capacitance model describing the intrinsic and extrinsic components of the device capacitance is an essential part of a compact model for circuit simulation besides DC model. In most circuit simulator, the same capacitance model is used for both: large-signal transient analysis small-signal AC analysis. A capacitance model is always based on quasi-static assumptions, i.e. charge in a device can follow the varying terminal voltage instantaneously without any delay. HO #18: ELEN 51 - MOS Cap Models Page
Capacitance Components in MOSFETs Two groups of MOS capacitances: A. intrinsic: capacitances between source and drain metallurgical junctions such as C, C, and C GB B. extrinsic: parasitic capacitances such as overlap C O and C O junction - C BS and C BD. HO #18: ELEN 51 - MOS Cap Models Page 3
Intrinsic Capacitance: Meyer Model Meyer model treats MOSFET intrinsic capacitance as three separate lumped capacitors: C, C, and C GB. Capacitances are derived on the following assumptions: MOSFET capacitances are reciprocal, i.e. C GB C BG, C C DG, and C C SG the rate of change of Q G rate of change of Q inv when G, S, and D bias changes, i.e. Q g Q g Q Q inv inv (1 the bulk charge Q B is a constant along the channel and depends only on applied bias GB. HO #18: ELEN 51 - MOS Cap Models Page 4
Meyer Intrinsic Capacitance Model From the law of charge conservation, we know: Where Q g + Q i + Q + Q b 0. ( Q g charge on the gate per unit area Q i mobile inversion layer charge per unit area Q ide charge / interface defects per unit area Q b bulk charge/area in the depletion layer under the channel Typically, Q << Q g, therefore, Q g (Q i + Q b (3 Neglecting bulk charge effect we have at strong inversion, Q i C [ gs th (y] (4 Here (y channel potential at any point y along the channel direction with reference to source potential. HO #18: ELEN 51 - MOS Cap Models Page 5
Meyer Intrinsic Capacitance Model We have shown (HO #17: I DS dy Wµ s Q i d (5 where µ s surface mobility W device width. Integrating (5 from (y 0, 0 to (y L, DS we get: I DS W µ sc L 0 W L µ sc [ ( y ] Substituting for DS I Wµ C L DS th th 1 DS d [ ( ] [ ] s DS th DS (6 HO #18: ELEN 51 - MOS Cap Models Page 6 (7
Meyer Intrinsic Capacitance Model From (7, we get: Wµ sc I DS ( th + ( th ( th ( L Wµ sc [( th ( th ] L Now, from (3 the total gate charge is given by: Q G [ ][ ] L L L W Qi y dy W Qb ( y dy W 0 0 0 Where we assumed that Q b is constant along the channel. Substituting for dy from (5 into (9 we get: i B th (8 ( Q ( y dy Q (9 Q G W µ s I DS 0 DS Q i ( y d Q B (10 HO #18: ELEN 51 - MOS Cap Models Page 7
Meyer Intrinsic Capacitance Model Substituting for Q i (y from (4 and I DS from (8 in (10, we get: Q G WLC DS ( th ( y ( th ( th 0 3 3 ( th DS ( th WLC 3 ( ( WLC 3 3 ( th ( th ( ( th th th 3 th Q B Q d Q B B (11 Where in (11 we have used DS Differentiating (11 we obtain three components of intrinsic capacitance in different operation region of MOSFETs. HO #18: ELEN 51 - MOS Cap Models Page 8
Meyer Model - Linear Region Capacitance From (11 we get the intrinsic capacitances in the strong inversion region: C C C GB Q G Q Q G G GB,,, GB GB WLC 3 WLC 3 0. 1 1 ( th ( + ( th ( + Note that C GB 0 in the strong inversion is expected since the inversion charge in the channel from S to D shields the gate from the bulk and therefore, prevents any response of Q G due to substrate bias BS. th th (1a (1b (1c HO #18: ELEN 51 - MOS Cap Models Page 9
Meyer Model - Saturation Region Capacitance In saturation, DS DSAT and we can obtain Q G by replacing DS in (11 by DSAT. For long channel devices: DSAT th. Also, in saturation we can write: DS DSAT th at DS > DSAT. Then substituting for in (11, we get: Q G WLC 3 WLC 3 3 ( th th ( th ( ( th th ( th QB th 3 Q B (13 HO #18: ELEN 51 - MOS Cap Models Page 10
Meyer Model - Saturation Region Capacitance From (13 we get the saturation region intrinsic capacitances at DS DSAT : C Q G, GB WLC 3 (14a C Q G, GB 0 (14b C GB Q G GB, 0. (14c Note that the saturation region capacitances are independent of DS. Since in saturation, the channel is pinched-off at the drain end it is electrically isolated from the drain. Thus, the charge on the gate is not influenced by a change in DS and the capacitances do not change. HO #18: ELEN 51 - MOS Cap Models Page 11
Meyer Model - Subthreshold Region Capacitance In the weak inversion region ( < th, Q i << Q b so that (9 becomes: Q Q W Q ( y dy WLQ (15 G B L 0 b The depletion charge density in the bulk for long channel devices is given by: Q γ b C φ s Where ε SiqN sub γ body effect coefficient given by: γ C φ s surface potential in weak inversion region given by: φ s γ γ 4 + + GB FB b (16 (17 HO #18: ELEN 51 - MOS Cap Models Page 1
Meyer Model - Subthreshold Region Capacitance Substituting for Q b and φ s from (16 and (17 in Q G (15 we get: 1 QG QB WLCγ 1 1+ 4 ( GB FB (18 γ From (18 we get the capacitance in the weak inversion region: QG C 0 (19a C C GB Q Q G G GB,,, GB GB 0 (19b 4 1+ γ WLC ( GB FB. (19c HO #18: ELEN 51 - MOS Cap Models Page 13
Meyer Intrinsic Capacitance Model Finally, the accumulation region capacitances are given by: C GB C, and C 0 C. The following Fig. illustrates the capacitances in the Meyer model. G C C S C GB D C JS C JD Here C JS Source-substrate junction capacitance C JD Drain-substrate junction capacitance. B HO #18: ELEN 51 - MOS Cap Models Page 14
Summary of Meyer-Capacitance Model Mode of operation C C CGB Accumulation 0 0 C Sub-threshold 0 0 1+ γ 4 WLC ( GB FB ( ( Linear WLC WLC 0 ( th 1 ( th 1 3 + 3 th + th Saturation (/3WLC 0 0 Total gate capacitance C t WLC HO #18: ELEN 51 - MOS Cap Models Page 15
Meyer Intrinsic Capacitance Model The normalized C, C, and C GB vs. plots for DS 1 and 3 are shown below: The capacitances are normalized with respect to the total gate capacitor C t WLC. The maximum device capacitance C t occurs in accumulation. In strong inversion, the maximum capacitance occurs at saturation and is (/3C t. HO #18: ELEN 51 - MOS Cap Models Page 16
Meyer Intrinsic Capacitance Model: Equivalent Circuit The Meyer model is represented by a simple equivalent circuit as shown below: HO #18: ELEN 51 - MOS Cap Models Page 17
Limitations of Meyer Model Meyer model is sufficiently accurate for many circuit applications and has been widely used over many years in SPICE. However, it has been found to yield non-physical results due to: charge non-conservation problem because of improper model implementation in circuit simulators like SPICE reciprocity assumption. More accurate charge-based capacitance model is developed for accurate capacitance modeling. HO #18: ELEN 51 - MOS Cap Models Page 18
Gate Overlap Capacitance The overlap capacitances are parasitic elements that originate due to lateral diffusion of the S/D dopants. Typically, MOSFET S/D regions are symmetrical, we can assume S/D overlap distance l ov to be equal. Assuming the parallel plate formulation, the overlap capacitance C O and C O for the source and drain regions, respectively can be apprimated as: ε C O CO Wlov t C Wl ov (0 HO #18: ELEN 51 - MOS Cap Models Page 19
If Gate Overlap Capacitance C gso gate-source overlap capacitance/width C gdo gate-source overlap capacitance/width then C gso C gdo C l ov (1 A significant component of C gso and C gdo is C GBO due to the overlap between the gate and bulk. C GBO is: due to the overhung of the MOS gate at one or both ends a function of the drawn polysilicon channel length. HO #18: ELEN 51 - MOS Cap Models Page 0
Gate Overlap Capacitance If C gbo gate bulk overlap capacitance/length, then the total gate-bulk overlap capacitance becomes: C GBO C gbo L poly ( where L poly polysilicon gate length. Typically, C GBO << C O and C O and is often neglected. The overlap capacitance models discussed in (0 - ( are found significantly different from that of he measured in advanced devices due to the fringing capacitances associated with: the gate perimeter the finite polysilicon gate thickness. HO #18: ELEN 51 - MOS Cap Models Page 1
Gate Overlap Capacitance Model MOS overlap capacitance can be apprimated by parallel combination three components: direct overlap capacitance C 1 between gate-source/drain fringing capacitance C on the outer side between the gate and the source/drain fringing capacitance C 3 on the channel (inner side between the gate and sidewall of the source/drain junction. HO #18: ELEN 51 - MOS Cap Models Page
Gate Overlap Capacitance Model Thus, the total overlap capacitance per unit width of the MOS device is given by: ε t poly ε X ( + + + + si j C ln 1 ln gso Cgdo C lov 1 + sinα1 α1 t π t C 1 C C3 In (3, C 1 parallel plate component of length (l ov + (3 where correction factor due to slope α 1 of polysilicon thickness and is given by: t 1 cosα1 1 cosα + sinα1 sinα πε where α ε si (4 HO #18: ELEN 51 - MOS Cap Models Page 3
Gate Overlap Capacitance Model C gso ε t poly ε X ( + + + + si j C ln 1 ln gdo C lov 1 + sinα1 α1 t π t C 1 C C3 (3 Note: C 3 >> C since ε si 3ε C gso /C gdo 0 due to fringing components even l ov 0 C gso /C gdo is bias dependent, particularly for LDD devices C 3 f(, DS C 3 in (3 is the maximum value of inner fringing capacitance C 3 as from sub-threshold to strong inversion and C 3 0 when device operates at strong inversion. HO #18: ELEN 51 - MOS Cap Models Page 4
Hot-Carrier Effects For DS > DSAT, lateral e-field increases beyond E c and reaches a maximum value at the drain end. From pseudo-d analysis it can be shown that maximum e-filed is: E (5 c DS DSAT E m + l c Where, l c L depends on: E E m gate ide thickness t junction depth X j S L D l c ε Si t X j (6 ε E c y DS DSAT DS DSAT if >> Ec then : Em (7 lc lc HO #18: ELEN 51 - MOS Cap Models Page 5
Hot-Carrier Effects Channel electrons traveling through high electric field, E > E c near the drain end can: n+ Source Gate I g hot e hole I sub n+ Drain become highly energetic, i.e. hot cause impact ionization and generate e and holes holes go into the substrate creating substrate current, I sub. Some channel e have enough energy to overcome the SiO -Si energy barrier generating gate current, I g. The maximum e-field, E m near the drain has the greatest control of hot carrier effects. HO #18: ELEN 51 - MOS Cap Models Page 6
Substrate Current I sub DS > DS1 DS1 DS Note that: I sub as DS I sub as for * and I sub (max at * I sub as for *. * Impact ionization may cause long term degradation in MOSFET device performance. I sub is a measure of impact ionization in MOSFETs. I sub must be minimized. This is, generally, achieved by reducing E m near the drain end of the device. HO #18: ELEN 51 - MOS Cap Models Page 7
Substrate Induced Body Effect I sub flowing into the substrate causes an IR drop in the substrate resulting in Body bias Substrate induced Body Effect (SCBE. SCBE results in th drop and manifold increase in I sub I DS. HO #18: ELEN 51 - MOS Cap Models Page 8
Substrate Current Modeling Impact ionization coefficient, α A i exp( B i /E. Then the substrate current due to impact ionization is: I sub l I αdx o l c c o I D D A e i Bi E( x dx Where x 0 start of impact ionization region with E E c x l c length of impact ionization region with E E m. (8 Changing the limits of integration to E in (8 and after integration we get: A i B i I sub lcemi D exp (9 Bi Em as E, I m sub HO #18: ELEN 51 - MOS Cap Models Page 9
Substrate Current, I sub Model Thus, I sub generated due to impact ionization is given by: I sub A B exp i, E i lcemi DS Bi m where A i and B i are impact ionization parameters l c characteristic length of impact ionization region E m maximum lateral electric field near the drain DS l c DSAT E c critical electric field for velocity saturation. + E c HO #18: ELEN 51 - MOS Cap Models Page 30
Substrate Current, I sub Model At strong inversion ( DS >> DSAT E m is given by: E m DS l c DSAT I sub Ai B i B ilc ( I exp DS DSAT DS DS DSAT where DSAT E E c c L L eff eff ( th ( + th L eff effective channel length of device th threshold voltage of device. HO #18: ELEN 51 - MOS Cap Models Page 31
Substrate Current, I sub Model in BSIM I sub α 0 α 1 + exp Leff 0 ( DS DSAT I DS DS β DSAT Substrate current model parameters: α 0 α 1 first parameter of substrate current model length scaling parameter of substrate current model β 0 second parameter of substrate current model HO #18: ELEN 51 - MOS Cap Models Page 3