Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 2 Quality Metrics of Digital Design guntzel@inf.ufsc.br
Reliability Noise in Digital Integrated Circuits i ( t ) v ( t ) V DD Inductive coupling Capacitive coupling Power and ground noise Slide 2.2
DC Operation Voltage Transfer Characteristic VOH = f(vol) VOL = f(voh) VM = f(vm) Nominal voltage levels Slide 2.3
Mapping Between Analog and Digital Levels 1 V OH V out V OH Slope = -1 V IH Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in Slide 2.4
Definition of Noise Margins "1" V OH NM H V IH Undefined Region Noise margin high NM L V IL Noise margin low V OL "0" Gate Output Stage M Gate Input Stage M+1 Slide 2.5
Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources Slide 2.6
Impact of Impedance on Robustness VDD R o Receiver Driver R i GND Courtesy: Prof. Luiz C. V. dos Santos (ine5442, 2008 UFSC) Slide 2.7
Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; Slide 2.8
Key Reliability Properties v 0 v 1 v 2 v 3 v 4 v 5 v 6 d V out / d V in > 1 d V out / d V in < 1 Regenerative Adapted from Rabaey; Chandrakasan; Nikolic, 2003 by Luiz C. V. dos Santos Slide 2.9 Non-regenerative
Key Reliability Properties A chain of inverters v 0 v 1 v 2 v 3 v 4 v 5 v 6 Simulated response V (volt) - Slide 2.10 t (ns)
Fan-in and Fan-out N M Fan-out N Slide 2.11 Fan-in M
The Ideal Gate V out R i = g = R o = 0 Fanout = NM H = NM L = V DD /2 V in Slide 2.12
An Old-Time Inverter (from the 1970 s) VDD = 5.00V 5.0 V OH = 3.50 V V IH = 2.35 V NM H = 1.15 V 4.0 3.0 NM L V OL = 0.45 V V IL = 0.66 V NM L = 0.21 V (V) 2.0 out V 1.0 V M NM H V M = 1.64 V (V) 0.0 1.0 2.0 3.0 4.0 5.0 V in (V) Slide 2.13
V in Quality Metrics of Digital Design Delay Definitions 50% Propagation delay (V in x V out ): where t p = t plh + t phl 2 t phl = propagation delay for 1 0 transition t plh = propagation delay for 0 1 transition V out t phl 50% 10% t plh 90% t Fall and Rise Times: t f = fall time t r = all time t f t r t Adapted from: Rabaey; Chandrakasan; Nikolic, 2003 Slide 2.14
Ring Oscilator T = 2 x t p x N Slide 2.15
A First Order RC Network R V out C V out (t) = (1 e -t/τ ) [V] t p = ln (2) τ = 0.69 RC Important model matches delay of inverter Slide 2.16
Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: Slide 2.17
Energy and Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p Slide 2.18
A First Order RC Network R V out C L Slide 2.19
Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation Slide 2.20
Reference Rabaey J.; Chandrakasan A.; Nikolic B. Digital Integrated Circuits: a design perspective., 2 nd Edition, Prentice Hall, USA, 2003. pages 18-31 Slide 2.21