Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY

Similar documents
NEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES

From Spin Torque Random Access Memory to Spintronic Memristor. Xiaobin Wang Seagate Technology

Experiment 7: Magnitude comparators

A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.

A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology

Perpendicular MTJ stack development for STT MRAM on Endura PVD platform

Solid-State Electronics

Page 1. A portion of this study was supported by NEDO.

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

Author : Fabrice BERNARD-GRANGER September 18 th, 2014

MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application

Center for Spintronic Materials, Interfaces, and Novel Architectures. Spintronics Enabled Efficient Neuromorphic Computing: Prospects and Perspectives

Memory and computing beyond CMOS

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1

RE-ENGINEERING COMPUTING WITH NEURO- MIMETIC DEVICES, CIRCUITS, AND ALGORITHMS

Additional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Neuromorphic computing with Memristive devices. NCM group

Introduction to Computer Engineering ECE 203

This document is an author-formatted work. The definitive version for citation appears as:

SPICE Modeling of STT-RAM for Resilient Design. Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu (Kevin) Cao School of ECEE, ASU

Gates and Flip-Flops

Hopfield Neural Network and Associative Memory. Typical Myelinated Vertebrate Motoneuron (Wikipedia) Topic 3 Polymers and Neurons Lecture 5

Novel VLSI Implementation for Triplet-based Spike-Timing Dependent Plasticity

Nonvolatile CMOS Circuits Using Magnetic Tunnel Junction

Kaushik Roy Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Floating Point Representation and Digital Logic. Lecture 11 CS301

Addressing Challenges in Neuromorphic Computing with Memristive Synapses

Digital Circuits. 1. Inputs & Outputs are quantized at two levels. 2. Binary arithmetic, only digits are 0 & 1. Position indicates power of 2.

Wouldn t it be great if

Lecture 6 NEW TYPES OF MEMORY

CPE100: Digital Logic Design I

Switches: basic element of physical implementations

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

Cs302 Quiz for MID TERM Exam Solved

Digital Electronics Part 1: Binary Logic

A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies

Embedded MRAM Technology For logic VLSI Application

Quasi Analog Formal Neuron and Its Learning Algorithm Hardware

Digital Logic (2) Boolean Algebra

ECE 342 Electronic Circuits. Lecture 34 CMOS Logic

Implementation of Boolean Logic by Digital Circuits

Computer organization

Unit 8A Computer Organization. Boolean Logic and Gates

An Overview of Spin-based Integrated Circuits

Low Energy Spin Transfer Torque RAM (STT-RAM / SPRAM) Zach Foresta April 23, 2009

Introduction to CMOS VLSI Design Lecture 1: Introduction

MRAM: Device Basics and Emerging Technologies

Spin-Based Logic and Memory Technologies for Low-Power Systems

Chapter 2 Combinational Logic Circuits

Synaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics

New Approaches to Reducing Energy Consumption of MRAM write cycles, Ultra-high efficient writing (Voltage-Control) Spintronics Memory (VoCSM)

Designing Information Devices and Systems II Spring 2018 J. Roychowdhury and M. Maharbiz Discussion 1A

Computer Organization: Boolean Logic

2.0 Basic Elements of a Quantum Information Processor. 2.1 Classical information processing The carrier of information

University of Toronto. Final Exam

Chapter 2 Combinational Logic Circuits

Low Energy SPRAM. Figure 1 Spin valve GMR device hysteresis curve showing states of parallel (P)/anti-parallel (AP) poles,

Test System Requirements For Wafer Level MRAM Test

Learning Objectives 10/7/2010. CE 411 Digital System Design. Fundamental of Logic Design. Review the basic concepts of logic circuits. Dr.

CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned

4 Switching Algebra 4.1 Axioms; Signals and Switching Algebra

MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

SOLID STATE ELECTRONICS DIGITAL ELECTRONICS SOFT CONDENSED MATTER PHYSICS

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

Fundamentals of Digital Design

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

Center for Spintronic Materials, Interfaces, and Novel Architectures. Voltage Controlled Antiferromagnetics and Future Spin Memory

The N3XT Technology for. Brain-Inspired Computing

A nanoparticle-organic memory field-effect transistor behaving as a programmable spiking synapse

ECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks

Chapter 2: Boolean Algebra and Logic Gates

EGC221: Digital Logic Lab

Bipolar Junction Transistor (BJT) - Introduction

NEM Relay Design for Compact, Ultra-Low-Power Digital Logic Circuits

arxiv: v1 [cond-mat.mtrl-sci] 28 Jul 2008

Simple Neural Nets For Pattern Classification

Simple Neural Nets for Pattern Classification: McCulloch-Pitts Threshold Logic CS 5870

Machine Learning. Neural Networks. (slides from Domingos, Pardo, others)

NTE74LS181 Integrated Circuit TTL Arithmetic Logic Unit/Function Generator

EC/EE DIGITAL ELECTRONICS

Logic Gates and Boolean Algebra

EE141-Fall 2011 Digital Integrated Circuits

ECE521 Lectures 9 Fully Connected Neural Networks

Neural Networks Introduction CIS 32

School of Computer Science and Electrical Engineering 28/05/01. Digital Circuits. Lecture 14. ENG1030 Electrical Physics and Electronics

F14 Memory Circuits. Lars Ohlsson

Reification of Boolean Logic

Thermal Magnetic Random Access Memory

Applications of Memristors in ANNs

Chapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms

CIRCUITS AND ELECTRONICS. The Digital Abstraction

Boolean algebra. Examples of these individual laws of Boolean, rules and theorems for Boolean algebra are given in the following table.

Intro To Digital Logic

EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping

A design methodology and device/circuit/ architecture compatible simulation framework for low-power magnetic quantum cellular automata systems

Low-power non-volatile spintronic memory: STT-RAM and beyond

Transcription:

Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY

Magnetic Tunnel Junctions (MTJs) Structure High density memory Free layer (FM 1) Tunneling barrier (Insulator: MgO) Pinned layer (FM 2) Bit line (BL) Word line (WL) AP or P state 0 or 1 Function Representation of non-volatile binary state according to magnetization configuration Source line (SL) 1 Transistor + 1 MTJ Advantage Scalability Low energy High speed High endurance CMOS compatibility 1GB STT-MRAM, Everspin (2016) - 2 -

Content To find computing functions beyond memory from MTJ for integrated circuits Construction of 2-input MTJ MTJ Logic gates Neuromorphic computing Artificial MTJ neuron Artificial MTJ synapse Artificial Neurotransmission system - 3 -

Basic configuration of MTJ Single input configuration for switching to achieve the binary state FM 1 FM 2 MTJ switching FM 1 FM 2 Anti-parallel state (R AP ) Parallel state (R P ) Methods for magnetization reversal of free layer Switching variable 1: magnetic field switching (current induced Ampere field) I Switching variable 2: Spin-transfer torque (STT) switching (spin polarized current) I - 4 -

Two-input configuration of MTJ Motivation for multiple input extension Increase of functional flexibility - Reduction of switching stress by breakup of biases - Increase of switching bias margin Physical variables for MTJ switching H in by applying I AF V in for I STT R MTJ - Ampere field-induce switching - Spin-transfer torque (STT) switching - Thermally assisted switching (TAS) I OF - Voltage-assisted switching (ME effect) - Spin-orbit torque (SOT) switching Multiple input is available for MTJ I STT X I AF Structure of 2-input MTJ Our choice: STT & Ampere field for two switching inputs Sharing integration methods developed for MRAM - 5 -

Switching characteristics of 2-input MTJ MTJs for switching characteristics due to mixed inputs of STT & Ampere field Size : (80 80) ~ (150 600) nm 2-6 -

Interpretation of 2-input switching H a = 0 (at coercive center) H a = 30 Oe H a = -30 Oe Magnetic field assisted STT switching Case for switching to be P state Energy due to Ampere field (H ext = H a ) : Required energy for STT switching E b+ = E b0 - E b * H s : Switching field E 0 : Energy barrier at zero magnetic field a J : Spin transfer torque a c : Critical spin transfer torque β = 2-7 -

NAND/NOR representation Definition of binary states for each input Assignment of input values to the STT input terminal Logic value Input 1 (V) Input 2 (H) MTJ OUT 1 V H H H R AP 0 V L H L R P V H R 0 0 0 1 0 0 0 1 0 1 1 1 V L =0.2 V(<V S1 ), V H =0.3 V (V S1 <V H <V S2 ) H L =-5 (Oe), H H = 5 (Oe) V H R 0 0 1 1 0 0 0 1 0 1 1 0 V L =0.3 V (V S1 <V L <V S2 ), V H =0.4 V (>V S2 ) H L =-5 (Oe), H H = 5 (Oe) - 8 -

All logical representation founded in MTJ 7 Boolean logic representations from possible 12 binary inputs of voltage biases for the STT switching No. Initial Input set Input (V, H), Output (R) Logic function State V L V H H L H H (V L,H L ) (V H,H L ) (V L,H H ) (V H,H H ) R AP = 1, R P = 0 R AP = 0, R P = 1 1 0.2 0.3 R AP R AP R AP R P NAND AND 2 0.3 0.4 R AP R P R P R P NOR OR 3 0.2 0.4 R R AP R P R AP R P NOT V V 4 AP 0.2 0.2 R AP R AP R AP R AP TRUE FALSE 5 0.3 0.3 R AP R AP R P R P NOT H H 6 0.3 0.3 R 5 Oe 5 Oe P R P R P R P FALSE TRUE 7 0.25 0.35 R P R AP R P R P V NIMP H V IMP H 8 0.35 0.45 R AP R AP R P R AP H IMP V H NIMP V 9 0.25 0.45 R R P R AP R P R AP V NIMP H V IMP H 10 P 0.25 0.25 R P R P R P R P FALSE TRUE 11 0.35 0.35 R AP R AP R P R P NOT H H 12 0.45 0.45 R AP R AP R AP R AP TRUE FALSE - 9 -

MTJ Logic gate Logic gate for digital computing - Cascading computing Full schematic of a logic gate - 10 -

14 Boolean functions computed in MTJ logic gate - Each function is confirmed by SPICE simulation modified with MTJ micro-model - XOR and XNOR are missing among full 16 Boolean logics - 11 -

XOR/XNOR MTJ Logic gate - XOR/XNOR gate could be completed by using cascading computing Conclusively, we have two types of MTJ logic gate which allow any digital computing - 12 -

Reconfigurable Logic Reconfigurability: further advantage of MTJ logic < Truth table > - 13 -

Practical example for reconfigurable Logic Carry-out function with reconfigurable logic < Truth table > - 14 -

Neurotransmission spike signal carrying information < Slowly Adapting> < Fast Adapting > Stimulus for tactile sense Pressure Frequency Slowly Adapting Fast Adapting - 15 -

Neural coding Neural (Biological) coding To find carrier for information according to Strength and frequency of input stimulus - Rate coding Information spiking rate - Temporal coding Information Spiking pattern (Spike ordering in timing) - Time-to-first-spike, Phase Correlations, Spiking sequence, Synchrony etc. - 16 -

Telegraphic switching Telegraphic switching by mixed effect of STT & Ampere field in 2-inpt MTJ I = -10 µa 40 20 μa H = 80 Oe R (kω) 30 20 10 10 μa 10 μa 20 μa 0 10 20 30 Time (s) Total Energy (E M + E STT ) ~ E S Toggling between AP and P state Stochastic characteristic Switching probability P(H, I) is defined as the carried information M. Pufall et al., Phys. Rev. B (2004) - 17 -

Rate coding Construction of neural coding : Rate coding RRRRRRRR(BBBBBBBBBBBBBB) = nn ssss (nnnnnnnnnnnn oooo ssssssssssss TT (tttttttt wwwwwwwwwwww) RRRRRRRR MMMMMM = ) tt AAAA (oooo tt PP ) TT (tttttttttt bbbbbb oooo P AP 1 ( H, I) = 1+ exp( α H + βi + γ ) Information carrier : rate Stimulus : H and I applied by independent inputs - 18 -

Artificial neuron function MTJ-based neuron architecture representing the rate coding - 19 -

Neurotransmission Neuron system connected by Synapse (Spike-rate-dependent plasticity) Neuron # : 10 11~12 Synapse # : 10 14~15 10 3~4 /neuron - Spike(=Action potential) generation (when the signal is above threshold) - Neural coding Information is coded through spike train Rate coding - Synaptic weight: plasticity for connection strength - Weight modulation Potentiation / Depression Spike-timing-dependent plasticity (STDP) - 20 -

Memristive character of MTJ - 21 -

MTJ-based artificial synapse Construction of input signal for Spike-timing dependent plasticity <Biological STDP> Δt > 0 Δt < 0 R. Froemke et al., Nature (2002) - 22 -

Artificial neurotransmission Neurotransmission system Artificial neurotransmission system MTJs are commonly used for neural and synaptic functions Learning rule of Spike-rate dependent plasticity is possibly applied - 23 -

SRDP learning rule - 24 -

Summary MTJ was modified with two inputs for switching to achieve functional flexibility. Then we found various computing functions for digital to neuromorphic computing. - 25 -