Lecture 28 Field-Effect Transistors

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Transcription:

Lecture 8 Field-Effect Transistors

Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits.

4. Use small-signal equialent circuits to analyze FET amplifiers. 5. Compute the performance parameters of seeral FET amplifier configurations. 7. Understand the basic operation of CMOS logic gates.

NMOS Transistor

NMOS Transistor

Operation in the Cutoff Region i D 0 for GS V to

Operation Slightly Aboe Cut-Off By applying a positie bias between the Gate (G) and the body (B), electrons are attracted to the gate to form a conducting n-type channel between the source and drain. The positie charge on the gate and the negatie charge in the channel form a capacitor where: C gate A ε d ε WL t ox

Operation Slightly Aboe Cut-Off The amount of negatie charge that accumulates in the channel is gien by: Q C gate ( GS V This amount of charge is able to moe a distance L from the source to the drain in a time τ gien by: to ) τ L elocity L μe L μ

Operation Slightly Aboe Cut-Off The initial current flow for low drain-source oltage is gien by: i charge in transit C Lt transit time ( V gate μεw ox ( GS L μ GS V to to ) ) Q τ

Operation Slightly Aboe Cut-Off W i με ( GS Vto ) Lt ox For small alues of, i D is proportional to. The deice behaes as a resistance whose alue depends on GS.

Operation in the Triode Region i D C [ ( ) ] GS to C W L KP

oundaryoperation in the Saturation Region i D GD GD GS i D ( ) V C GS to athetranstionintosaturati Vto athb GS C + V to GS V to one

Exercise 1.1 Consider an NMOS transistor haing V to V. What is the region of operation (triode, saturation, or cutoff) if: 1. GS 1V and 5V? Cutoff since GS <V to. GS 3V and 0.5V? Triode since GS >V to and < GS -V to 3. GS 3V and 6V? Saturation since GS >V to and > GS V to 4. GS 5V and 6V? Saturation since GS >V to and > GS -V to

Exercise 1. Suppose that we hae an NMOS transistor with KP 50μA/V, V to 1V, L μm and W 80μm. Sketch the drain characteristics for from 0 to 10V and GS 0, 1,, 3 and 4V. For GS 0 or 1V, the transistor is cutoff and the drain current is zero. In the saturation region: C I D KP C( W L GS V to 1 (50x10 ) 6 80 ) 1ma / V The boundary between the triode and saturation regions occurs when V GS to I D C 3 4 GS ( V ) id ( ma) 1 1 4 9 3

Exercise 1.

PMOS Transistor p+ p+ n

MOSFET Summary

Exercise 1.3 Suppose that we hae an PMOS transistor with KP 5μA/V, V to -1V, L μm and W 00μm. Sketch the drain characteristics for from 0 to -10V and GS 0, -1, -, -3 and -4V. For GS 0 or -1V, the transistor is cutoff and the drain current is zero. In the saturation region: C I D KP C( W L GS V to 1 (5x10 ) 6 ) 00 1.5ma / V The boundary between the triode and saturation regions occurs when V GS to I D C GS 3 4 ( V ) i 1.5 5 D ( ma) 11.5 1 3

Exercise 1.3

Load-Line Analysis of a Simple NMOS Circuit R i + DD D D ( t) ( t)

Load-Line Analysis of a Simple NMOS Circuit To establish the load line, we first locate two points on it: DD R D i D ( t) + ( t) For DD 0V and R D 1kΩ 0V i D 1kΩi 0 0 D i D () t + () t 0V 0V 1kΩ 0mA

Load-Line Analysis of a Simple NMOS Circuit

Load-Line Analysis of a Simple NMOS Circuit The quiescent operating point (Q point) is found for in 0V GS ( t) in 4V ( t) + 4V for in 0V

Load-Line Analysis of a Simple NMOS Circuit The maximum gate-to-source oltage is found for in 1V GS ( t) in 5V ( t) + 4V for in 1V

Load-Line Analysis of a Simple NMOS Circuit The minimum gate-to-source oltage is found for in -1V GS ( t) in 3V ( t) + 4V for in 1V

Load-Line Analysis of a Simple NMOS Circuit

Peak to peak swing of GS is V 1 Peak to peak swing of is 1V A"V " 6

The output is not proportional to the input. The output goes down by 7V for a change of +1V on the input. The output goes up by 5V for a change of -1V on the input. The output is said to be distorted. This is due to the uneen spacing of the characteristic cures. Q 11V -7V +5V

Load-Line Analysis of a Simple NMOS Circuit Uneen spacing of the drain characteristics

Exercise 1.4 Find Q, min and max if the circuit alues are changed to V DD 15V, V GG 3V: 15V GS ( t) 3V in 3V V for 4V ( t) + 3V for for in in in 0V -1V + 1V

Exercise 1.4 To establish the load line, we first locate two points on it: DD R D i D ( t) + ( t) For DD 15V and R D 1kΩ 15V i D 1kΩi 0 0 D i D () t + () t 15V 15V 15mA 1kΩ

Exercise 1.4 GS Q GS GS min max 3V for V for 4V for in in in 0V -1V + 1V Q 11V min 6V max 14V

FET Logic

CMOS Inerter

Two-Input CMOS NAND Gate

Two-Input CMOS NOR Gate

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