1 EE 560 MOS TRANSISTOR THEORY PART 1
TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM: n p = n 2 i (n i 1.45 x 10 10 cm -3 ) Let SUBSTRATE be uniformy doped @ N A 2 n p0 n i and p N p0 = N A A (BULK concentrations)
ENERGY BAND DIAGRAM FOR p - TYPE SUBSTRATE 3 qχ = electron affinity of Si φ F = E F E i q Work Function qφ S = q χ + (E c E F ) φ Fp = kt (N A >> n i ) (N D >> n i ) q ln n i φ F n = kt N A q ln N D n i n i = 1.45 x 10-10 cm -3 @ room temp, k = 1.38 x 10-23 J/ o K, => kt/q = 26 mv @ room temp q = 1.6 x 10-19 C
ENERGY BAND DIAGRAMS FOR COMPONENTS OF MOS STRUCTURE 4 E o E Fm METAL (Al) qφ M = qχ m = 4.1 ev Ec OXIDE SEMICONDUCTOR (Si) qχ ox = 0.95 ev qφ S qχ Si = 4.15 ev E c band-gap: E g = 8 ev E Fp E i band-gap: E g = 1.1 ev qφ Fp E v E v Φ S > Φ M => p-type Si Φ M > Φ S => n-type Si
Equilibrium V G = 0 5 Oxide p-type Si Substrate Flat-band voltage: V FB = Φ M - Φ S volts Built-in potential: V B = 0 Equilibrium E c qφ M qφ S E Fm φ s = surface potential qφ s qφ F E Fp E v E i METAL (Al) OXIDE SEMICONDUCTOR (Si)
MOS SYSTEM WITH EXTERNAL BIAS Accumulation Region V G < 0 7 E OX E OX Oxide p-type Si Substrate holes ACCUMULATED on the Si surface V B = 0 V G = 0 Equilibrium Oxide p-type Si Substrate V B = 0
Depletion Region MOS SYSTEM WITH EXTERNAL BIAS V G > 0 (small) 8 E OX E OX Oxide p-type Si Substrate DEPLETION Region V B = 0 E c E Fm qv G E i E Fp E v METAL (Al) OXIDE SEMICONDUCTOR (Si)
MOS SYSTEM BIASED IN DEPLETION REGION 9 V G > 0 (small) 0 x d x x d E OX E OX Oxide p-type Si Substrate DEPLETION Region V B = 0 Mobile charge in thin layer parallel to Si surface Change in surface potential to displace dq Depletion Region Charge
Inversion Region MOS SYSTEM WITH EXTERNAL BIAS V G > 0 (large) 10 x dm E OX E OX Oxide p-type Si Substrate Electrons attracted to Si surface Inversion Condition φ s = -φ F V B = 0 x dm = x d φ s = φf = 2ε Si 2φ F qn A E c E Fm qv G φ s = -φ F E i E Fp E v METAL (Al) OXIDE SEMICONDUCTOR (Si)
G G G G G G 11 D S D S B B n-channel enhancement S B DS B D S D B p-channel enhancement B S I DS DS -V Tp I DS DS 0 V GS GS 0 +V Tn Tn V GS GS n-channel depletion G I DS DS D S I DS DS 0 +V Tp +V Tp p-channel depletion V GS GS B -V Tn Tn 0 V GS GS
B S G W D 12 L oxide n + n + substrate or bulk B p conducting channel depletion layer N-CHANNEL ENHANCEMENT-TYPE MOSFET nmos Layout polysilicon gate L W active area metal contact area
B S G D D G S B 13 p+ p+ n+ n+ n-well p -substrate V GS < V Tn CUT-OFF REGION 0 < V GS < V Tn DEPLETION REGION V GS V DS B ( G 2 ) S n + C GC GC CC BC BC G oxide D n + n + depletion region depletion region substrate or or bulk bulk B B p p
V GS > V Tn INVERSION REGION 14 V GS VDS B ( G 2 ) S n + C GC GC C C BC BC G oxide D n + n + n + substrate or or bulk B p conducting channel or inversion region depletion region Underneath Gate V G = V Tn E c E Fm qv Tn 2φ F -φ F φ F E i E Fp E v METAL (Al) OXIDE SEMICONDUCTOR (Si)
MOS Capacitance t ox = 50 nm, ε ox = 0.34 pf/cm => = 6.8 x 10-8 F/cm 2 W x L = 50 µm x 50 µm => C GC = 170 ff Depletion Capacitance C j = ε Si C BC = WLC j, x d φ Fp = kt q ln n i N A N A = 3 x 10 17 cm -3, n i = 1.45 x 10 10 cm -3 => φ F = -0.438 V (recall that at room temp or 27 o C kt/q = 26 mv) C GC = WL = ε ox t ox 15 [t ox -> TOX in SPICE] [ -> COX in SPICE] V SB = 0 V, ε Si = 1.06 pf/cm, q = 1.6 x 10-19 C, N A, φ F => x d = 6.22 µm, N SUB ε Si, x d => C j = 0.17 x 10-8 F/cm 2 [N SUB -> NSUB in SPICE] (p - substrate) W x L = 50 µm x 50 µm => C BC = 42.5 ff
Threshold Voltage for MOS Transistors n-channel enhancement [V T0 -> VT0 in SPICE] For V SB = 0, the threshold voltage is denoted as V T0 or V T0n,p 16 Threshold Voltage factors: -> Gate conductor material; -> Gate oxide material & thickness; -> Channel doping; -> Impurities in Si-oxide interface; -> Source-bulk voltage V sb ; -> Temperature. V T0 = Φ GC 2φ F Q B0 Q ox (+ for nmos and - for pmos) Φ GC = φ F (substrate) -φ M Φ GC = φ F (substrate) -φ F (gate) [Q ox = qnss in SPICE] [2φ F = PHI in SPICE] [N A = NSUB in SPICE] metal gate polysilicon gate
Threshold Voltage for MOS Transistors n-channel enhancement For : the threshold voltage is denoted as V T or V Tn,p 17 V T = Φ GC 2φ F Q B Q ox where = Φ GC 2φ F Q B0 V T0 Q ox Q B Q B0 (γ = Body-effect coefficient) [γ = GAMMA in SPICE] +
Threshold Voltage for MOS Transistors 18 n-channel -> p-channel ****BE CAREFULL*** WITH SIGNS φ F is negative in nmos, positive in pmos Q B0, Q B are negtive in nmos, positive in pmos γ is positive in nmos, negative in pmos V SB is negative in nmos, positive in pmos NOTE: γ C BC C GC
Threshold Voltage for MOS Transistors 19 3V V T0 nmos N BULK = N A 10 14 10 16 pmos N ABULK -3V N BULK = N D 3V V T 16 3 (nmos 10 /cm ) 14 (nmos 3 x10 /cm 3) 0 3 16 3 (pmos 10 /cm ) 6 V BS SB -3V
EXAMPLE 3.2 Calculate the threshold voltage V T0 at V BS = 0, for a polysilicon gate n-channel MOS transistor with the following parameters: substrate doping density N A = 10 16 cm -3, polysilicon doping density N D = 2 x 10 20 cm -3, gate oxide thickness t ox = 500 Angstroms, oxide-interface fixed charge density N ox = 4 x 10 10 cm -2. 20 φ F(sub), Φ GC : V T0 = Φ GC 2φ F(sub) Q B0 Φ GC = φ F(sub) φ F(gate) Q ox φ F(sub) = kt q ln n i = 0.026Vln 1.45x1010 N A 10 16 = 0.35V φ F(gate) = kt q ln N D n i 2x10 20 = 0.026Vln 1.45x10 10 = 0.60V Φ GC = φ F(sub) φ F(gate) = -0.35 V - 0.60 V = -0.95 V
EXAMPLE 3-2 CONT. Q B0 : V T0 = Φ GC 2φ F(sub) Q B0 Q ox 21 : Q ox : = 2(1.6x10 19 C)(10 16 cm 3 )(1.06 x10 12 Fcm 1 ) 2x0.35V F = C/V = - 4.87 x 10-8 C/cm 2 = ε ox t ox = 0.34x10 12 Fcm 1 500x10 8 cm = 6.8x10 8 F/cm 2 Q ox = qn ox = (1.6x10 19 C)(4 x10 10 cm 2 ) = 6.4x10 9 C/cm 2 Q B0 = 4.87x10 8 C/cm 2 6.8x10 8 F/cm 2 = 0.716V Q ox = 6.4x10 9 C/cm 2 6.8x10 8 F/cm 2 = 0.094V V T0 = 0.95V ( 0.70V) ( 0.72V) (0.09V) = 0.38V
EXAMPLE 3.3 Consider the n-channel MOS transistor with the following process parameters: substrate doping density N A = 10 16 cm -3, polysilicon doping density N D = 2 x 10 20 cm -3, gate oxide thickness t ox = 500 Angstroms, oxide-interface fixed charge density N ox = 4 x 10 10 cm -2. In digital circuit design, the condition V SB = 0 can not always be quaranteed for all transistors. Plot the threshold voltage V T as a function of V SB. 22 γ - Body-effect coefficient: γ = F = C/V 2qN e A Si = 2(1.6 x10 19 C)(10 16 cm 3 )(1.06 x10 12 Fcm 1 ) 6.8x10 8 F/cm 2 = 5.824x10 8 C/V 1/ 2 cm 2 6.8x10 8 C/Vcm 2 = 0.85V 1/ 2
EXAMPLE 3-3 CONT. 23 where VT0 = 0.38V (from EX 3-2) γ = 0.85V 1/2 1.60 1.40 V T (Volts) 1.20 1.00 0.80 0.60 0.40 0.20-1 0 1 2 3 4 5 6 V SB (Volts)