Chapter 10 FIEL EFFECT TRANITOR: MOFET The following overview gures describe important issues related to the most important electronic device.
NUMBER OF ACTIVE EVICE/CHIP MOORE' LAW Gordon Moore, co-founder of Intel: 1st law: Complexity (number of active devices) of a chip doubles every 18 months. 2nd law: Cost of a fabrication facility grows on a semi-log scale with time. Complexity increases at ~59% per year! At current pace, semiconductor fabrication facilities will cost $250 billion by 2010! 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 1960 1970 1980 1990 2000 2010 YEAR
AN OVERVIEW OF THE MOFET TURCTURE Gate width, Z Polysilicon or metal Oxide n-type semiconductor n-source Gate L n-drain p-substrate G B TRUCTURE chematic symbol Metal source contact Gate, G n-type polysilicon eposited insulator Metal source drain io 2 Field oxide n + n d + ox rain ource Channel region } L ilicon dioxide Channel length L io 2 p + p-type body, B CRO-ECTIONAL VIEW Modern MOFETs are enormously complex devices with great care taken to reduce parasitic elements.
A IMPLE CHEMATIC OF PROCEE IN A MOFET FABRICATION Coat the entire wafer with i 3 N 4. i 3 N 4 is impervious to dopants. i 3 N 4 G n + source and drain are produced by ion implantation. p-i n + p-i p + (d) First mask: efine transistor area and remove i 3 N 4. Implant p + regions to serve as device isolation. Grow thick field oxide. io 2 p + io 2 is deposited on the entire structure. A mask is used to open windows for contacts. Al is evaporated. B G Etch i 3 N 4 and grow thin gate oxide. On the gate oxide, grow polysilicon and define the gate via a mask. polysilicon gate p-i io 2 p + (e) G B Top view of the device (c) (f)
BAN PROFILE IN A METAL, OXIE, EMICONUCTOR, AN A MO Metal Oxide (insulator) p-type semiconductor Band profiles in a metal, io 2, and p-i. E vac E vac E c (oxide) eφ s eχ s Evac eφ m E c Metal d ox Oxide emi-conductor E v ev fb Band profile in a MO structure E vac eφ m eχ s E c ev fb = eφ m eφ s eφ s Metal Oxide E v emiconductor (c)
BAN PROFILE AN CARRIER ENITY IN ACCUMULATION, EPLETION AN INVERION V G < 0 Electric field F Accumulation ρ p ev G E c i n p 0 n 0 Carrier density + + + M O E v W z Electric field F epletion ρ V G > 0 ev G M O E c i E v Na p n W p 0 z Carrier density Electric field F Inversion n (interface) > p o V G >> 0 E c ρ ev G i E v N a p n p 0 n 0 Carrier density M O (c) W z
AN MO TRUCTURE UNER INVERION V >> 0 W E c d ev G E i E v M O emiconductor z Q m Q (charge per unit area) Charge density W z Q d : charge from background dopants Q n : free carrier charge Electric field F ox F s W z V(x) Electrostatic potential V V ox V G = V fb + V W V s z = V fb + V ox + V s W max = ( 4ε s φ 1/2 F ; φ F = i en a 1 C ox Q ss = interface areal charge density ( V T = V fb 2φ F + [2eε s N a 2φ F + V B ] 1/2 Q ss C ox
CAPACITANCE-VOLTAGE RELATION IN A MO CAPACITOR Oxide emiconductor A typical C-V curve C = C ox C mos (fb) Accumulation C Low frequency (~1Hz) C mos (min) C = C ox (i) High frequency (10 3 Hz) (ii) Inversion C ox C s V fb 0 V T V G Flat band Accumulation epletion region Weak inversion trong inversion Once the MO is in inversion, the sheet charge density increases rapidly with bias. AREAL CHARGE ENITY, Q s (C/cm 2 ) 10 5 10 6 10 7 10 8 2φ F 10 9 0.2 1.0 0 URFACE VOLTAGE, V s (volt) 1.0 0.2 0.3 0.4
CURRENT VOLTAGE RELATION IN A MOFET A CHEMATIC OF THE TRUCTURE Gate width Z ource Gate L Oxide p-semiconductor rain z ource, n+ Gate, G n-channel n+ x = 0 x = L p-substrate rain, y B x V = V (sat) RAIN CURRENT I Linear region aturated region: I (V G V T ) 2 RAIN TO OURCE BIA V k = µzc ox L LINEAR REGIME: I = k[v G V T ]V ATURATION REGIME: k I (sat) = (V G V T ) 2 2
EFFECT OF BOY BIA ON MOFET PROPERTIE V G G n + n + p-substrate V n-mofet with V B bias V B E c Ιnversion condition when V B = 0 ev s = 2eφ F i E v W max W(V B ) E c Ιnversion condition when V B > 0 ev s = e( 2φ F + V B ) (c) n Electron quasi- Fermi level i E v hift in threshold voltage 2eε V T = s N a 2φ C F +V B 2φ F ox
EPLETION AN ENHANCEMENT MOFET ource Gate rain Oxide n-channel n + n + p-substrate epletion FET: evice is ON at zero gate bias. G substrate Ohmic region rain current I aturated region rain bias V A typical n-channel depletion-mode device V G = +2.0 volts V G = +1.0 V G = 0.0 V G = 1.0 V G = 2.0 V G = 3.0 Enhancement FET: evice is OFF at zero gate bias. G (c) substrate rain current I Ohmic region aturated region rain bias V A typical n-channel enhancement-mode device V G = +7.0 Volts V G = +6.0 V G = +5.0 V G = +4.0 V G = +3.0 Ion implantation of the channel is used to fabricate depletion mode MOFETs.
COMLIMENTARY MOFET: LOW POWER FET By combining an NMO and a PMO a CMO is constructed. ince only one device (NMO or PMO) conducts for any gate bias the CMO does not draw any current and is very useful for low power applications. ource + PMO Gate rain NMO Output rain Gate ource io 2 p + + + ++ p + io 2 n + n + io 2 p well Hole conduction Electron conduction n-type body +V PMO NMO CHEMATIC YMBOL A cross-section of a CMO device. ymbol representing the CMO. +V V in V out t p-channel I t t V in V out n-channel A complimentary MO structure shown to function as an inverter. The circuit draws current only during the input voltage switching. A schematic of the CMO structure.
LATCHUP PROBLEM IN CMO TECHNOLOGY The presence of npn, pnp bipolar pathways in a CMO can lead to parasitic transistor action and unintentional current flows. A B + V I p + p + n + p + n + n + R 1 R 2 npn R 4 n substrate pnp p well R 3 CURRENT, I lope = 1 R 3 R 4 VOLTAGE, V V L A schematic of the parasitic effects that lead to CMO latch-up problems. Current versus voltage effect. The onset of latch-up is represented by a sharp rise in the parasitic current.
CAPACITANCE OF IMPORTANCE IN A MOFET Gate Oxide Channel C GC ource rain CGO C n n+ + n GO + n n n n n n + n + n + n + p p p n + n+ p p p C BC1 C GB p p p p p p p C C B1 B1 p p p p Bulk (substrate) p p d 2 L L ource Z rain L d 1 Gate Region Cutoff Ohmic aturation C G C ox Z L C ox Z L + 1/2 ZL C ox C ox Z L C G C ox Z L C ox Z L + 1/2 Z LC ox C ox Z L + 2/3 Z LC ox C BG C ox Z L 0 0 (c) C B C B1 C C B1 + BC1 2 C B1 C B C B1 C B1 + C BC1 2 C B1 + 2/3 C BC1 A CIRUIT MOEL FOR A MOFET Total gate capacitance includes overlay effects (C G ) G Gate-drain capacitance includes parasitic effects (C G ) Miller capacitance: C M + C G (1+g m R L ) Cutoff frequency: f T = g m 2π(C G +C M ) ource-body capacitance n + R R g m V n + ' C G B C B p-substrate rain-body capacitance elf-aligned gate technology to minimize C M or C G.
CALING IUE IN MOFET TECHNOLOGY PARAMETER FULL CALING CONTANT-VOLTAGE CALING Gate width, Z 1/ 1/ Gate length, L Oxide thickness, d ox rain bias, V 1/ 1 Threshold bias, V T Oxide capacitance 1/ 1/ for the device rain current, I ~1/ ~ C power consumption ~1/ 2 ~ evice switching time ~1/ ~1/ 2 Power-delay product ~1/ 3 ~1/
EMICONUCTOR INUTRY AOCIATE ROAMAP YEAR 1997 1999 2001 2003 2006 2009 2012 RAM cell 250 180 150 130 100 70 50 half-pitch (nm) Gate length 200 140 120 100 70 50 35 for MPU (nm) Maximum 200 300 300 300 300 450 450 substrate diameter (mm) Acceptable 2080 1455 1310 1040 735 520 370 defect density at 60% yield for RAM efect density 1940 1710 1510 1355 1120 940 775 for MPU Power supply 1.8-2.5 1.5-1.8 1.2-1.5 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 (V) Power dissipation 70 90 110 130 160 170 175 with heat sink (W) Power dissipation 1.2 1.4 1.7 2.0 2.4 2.8 3.2 without heat sink (for portable electronics) (W) Cost per function 120 60 30 15 5.3 1.9 0.66 RAM (µcents/function) Cost per function 3000 1735 1000 580 255 110 49 MPU (µcents/function) KEY IUE: Gate tunneling current efect density Interconnect delays will dominate