Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 2.2 Add 48CSP-6x8mm package outline Revise 48CSP-8x10mm pkg code from W to K Mar. 08, 2005 Oct.25, 2005 1 Rev. 2.2
PRODUCT DESCRIPTION The is a high performance, high speed, low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.0uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable1 (/CE1), active HIGH chip enable2 (CE2) for BGA product and active LOW output enable (/OE) and three-state output drivers. The has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The is available in JEDEC standard 48-pin BGA and 44L TSOP 2 packages. FEATURES Low operation voltage: 2.7 ~ 3.6V Ultra low power consumption: Vcc = 3.0V: 55mA (Max.) operating current, 6 ua (Max.) CMOS standby current High speed access time: 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supply voltage as low as 1.5V. Easy expansion with /CE1&CE2 and /OE options. Product Family Product Family Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type 0~70 o C 2.7`~3.6 55/70-40~85 o C 2.7`~3.6 55/70 1.0 ua (Vcc = 3.0V) 1.5uA (Vcc= 3.0V) 44 TSOP 2 48 CSP-0608 48 CSP-0810 44 TSOP 2 48 CSP-0608 48 CSP-0810 2 Rev. 2.2
PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM 3 Rev. 2.2
PIN DESCRIPTIONS Name Type Function A0 A18 Input 19 address inputs for selecting one of the 262,144 x 16 bit words in the RAM /CE1 & CE2 Input /CE1 is active LOW and CE2 is active high. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and in a standby power mode. The DQ pins will be in high impedance state when the device is deselected. /WE Input The Write enable input is active LOW. It controls read and write operations. With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. /OE Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. /LB and Lower byte and upper byte data input/output control pins. Input /UB DQ0~DQ15 I/O These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Power Supply Gnd Power Ground 4 Rev. 2.2
TRUTH TABLE MODE /CE1 CE2 /WE /OE /LB /UB DQ0~7 DQ8~15 Vcc Current Fully H X X X X X High Z High Z I CCSB, I CCSB1 Standby X L X X X X High Z High Z I CCSB, I CCSB1 Output Disabled L H H H X X High Z High Z I CC Read L H H L L L D OUT D OUT I CC H L High Z D OUT I CC L H D OUT High Z I CC Write L H L X L L D IN D IN I CC H L High Z D IN I CC L H D IN High-Z I CC ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Rating Unit Terminal Voltage with Respect to V TERM GND -0.5 to Vcc+0.5 V T BIAS Temperature Under Bias -40 to +125 O C T STG Storage Temperature -60 to +150 O C P T Power Dissipation 1.0 W I OUT DC Output Current 55 ma Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5 Rev. 2.2
DC ELECTRICAL CHARACTERISTICS ( TA = 0~+70 o C / -40 0 C~+85 0 C, Vcc = 3.0V ) Paramete r Name V IL V IH I IL I OL Parameter Test Conduction MIN TYP (1) MAX Unit Guaranteed Input -0.5 0.8 V Low Voltage (2) Guaranteed Input 2.0 Vcc+0. High Voltage (2) 2 Input Leakage Current Output Leakage Current V CC =MAX, V IN =0 to V CC -1 1 ua V CC =MAX, /CE1=V IH and CE2=V IL, or /OE=V IH, V IO =0V to V -1 1 ua V OL Output Low Voltage V CC V CC =MAX, I OL = 2 ma 0.4 V V OH I CC I CCSB I CCSB1 Output High Voltage V CC =MIN, I OH = -1mA 2.4 V Operating Power /CE1=V IL and CE2=V IH, 55 ma Supply Current (3) I DQ =0mA, F=F MAX Standby Supply /CE1=V IH and CE2=V IL, 1 ma -TTL I DQ =0mA, Standby /CE1 V CC -0.2V or 0.5 6 ua Current-TTL CE2 0.2V, V IN V CC -0.2V or V IN 0.2V 1. Typical characteristics are at TA = 25 o C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/t RC. 6 Rev. 2.2
OPERATING RANGE Range Ambient Temperature Vcc Commercial 0~70 o C 2.7V ~ 3.6V Industrial -40~85 o C 2.7V ~ 3.6V DATA RETENTION CHARACTERISTICS ( TA = 0~+70 o C / -40 0 C~+85 0 C ) Parameter Name V DR I CCDR T CDR t R Parameter Test Conduction MIN TYP (1) MAX Unit V CC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time /CE1 V CC -0.2V or CE2 0.2V, V IN V CC -0.2V or V IN 0.2V /CE1 V CC -0.2V or CE2 0.2V, V CC =1.5V V IN V CC -0.2V or V IN 0.2V See Retention Waveform 1. Vcc = 3.0V, TA = + 25 o C2. = Read Cycle Time. 1.5 V 0.5 3 ua 0 ns t RC (2) ns CAPACITANCE (1) (TA = 25 o C, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit C IN Input Capacitance V IN =0V 6 pf C DQ Input/Output Capacitance V I/O =0V 8 pf 1. This parameter is guaranteed and not tested. 7 Rev. 2.2
LOW Vcc DATA RETENTION WAVEFORM (1) ( /CE1 Controlled ) LOW Vcc DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS Input Pulse Levels Vcc/0V WAVEFORMS INPUTS OUTPUTS Input Rise and Fall Times 5ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level Output Load 0.5Vcc See FIGURE 1A and 1B MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE 8 Rev. 2.2
AC TEST LOADS AND WAVEFORMS TERMINAL EQUIVALENT 667Ω OUTPUT 1.73V ALL INPUT PULSES V CC GND 10% 90% 90% 10% FIGURE 1A FIGURE 1B FIGURE 2 5ns 5ns AC ELECTRICAL CHARACTERISTICS( TA = 0~+70 o C / -40 0 C~+85 0 C, Vcc = 3.0V ) < READ CYCLE > JEDEC -55-70 Parameter Parameter Description Name MIN MAX MIN MAX Unit Name t AVAX t RC Read Cycle Time 55 70 ns t AVQV t AA Address Access Time 55 70 ns t ELQV t CO Chip Select Access Time (/CE1,CE2) t BA t BA Data Byte Control Access Time (/LB, /UB) 55 70 ns 55 70 ns t GLQV t OE Output Enable to Output Valid 30 35 ns t ELQX t LZ Chip Select to Output Low Z (/CE1, CE2) t BE t BLZ Data Byte Control to Output Low Z (/LB, /UB) t GLQX t OLZ Output Enable to Output in Low Z t EHQZ t HZ Chip Deselect to Output in High Z (/CE1, CE2) t BDO t BHZ Data Byte Control to Output High Z (/LB, /UB) t GHQZ t OHZ Output Disable to Output in High Z 10 10 ns 0 0 ns 5 5 ns 0 25 0 30 ns 0 25 0 30 ns 0 25 0 30 ns t AXOX t OH Out Disable to Address Change 10 10 ns 9 Rev. 2.2
SWITCHING WAVEFORMS (READ CYCLE) NOTES: 1. t HZ and t OHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 10 Rev. 2.2
AC ELECTRICAL CHARACTERISTICS ( TA = 0~+70 o C / -40 0 C~+85 0 C, Vcc = 3.0V ) < WRITE CYCLE > JEDEC Parameter Description -55-70 Unit Parameter Name Name MIN MAX MIN MAX t AVAX t WC Write Cycle Time 55 70 ns t E1LWH t CW Chip Select to End of Write 50 60 ns t AVWL t AS Address Setup Time 0 0 ns t AVWH t AW Address Valid to End of Write 55 70 ns t WLWH t WP Write Pulse Width 45 50 ns t WHAX t WR Write Recovery Time (/CE1, CE2, /WE) 0 0 ns t BW t BW Data Byte Control to End of Write (/LB, /UB) 55 70 ns t WLQZ t WHZ Write to Output in High Z 20 25 ns t DVWH t DW Data to Write Time Overlap 25 30 ns t WHDX t DH Data Hold from Write Time 0 0 ns t WHOX t OW End of Write to Output Active 5 10 ns SWITCHING WAVEFORMS (WRITE CYCLE) 11 Rev. 2.2
12 Rev. 2.2
NOTES: 1. A write occurs during the overlap(t WP ) of low /CE1, high CE2 and low /WE. A write begins when /CE1 goes low and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The t WP is measured from the beginning of the write to the end of write. 2. t CW is measured from the /CE1 going low or CE2 going low to end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. T WR applied in case a write ends as /CE1 or /WE going high or CE2 going low. ORDER INFORMATION Note: Package material code R meets ROHS 13 Rev. 2.2