SN74LS151D LOW POWER SCHOTTKY

Similar documents
SN74LS153D 74LS153 LOW POWER SCHOTTKY

SN74LS151MEL. 8 Input Multiplexer LOW POWER SCHOTTKY

74LS195 SN74LS195AD LOW POWER SCHOTTKY

SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY

SN74LS147, SN74LS Line to 4 Line and 8 Line to 3 Line Priority Encoders LOW POWER SCHOTTKY

SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY

SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY

LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648

SN74LS157MEL LOW POWER SCHOTTKY

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION

LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION

SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY

SN74LS125A, SN74LS126A. Quad 3 State Buffers LOW POWER SCHOTTKY. LS125A LS126A TRUTH TABLES ORDERING INFORMATION

2 Input NAND Gate L74VHC1G00

MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop

MC14060B. 14 Bit Binary Counter and Oscillator

74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Logic Diagram. Connection Diagram. Function Table (Each Latch)

SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY

74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS

MM74HC151 8-Channel Digital Multiplexer

74LS165 8-Bit Parallel In/Serial Output Shift Registers

MC74AC138, MC74ACT of 8 Decoder/Demultiplexer

CD4028BC BCD-to-Decimal Decoder

MC10ELT22, MC100ELT V Dual TTL to Differential PECL Translator

MM74HC157 Quad 2-Input Multiplexer

LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738

MM74HC138 3-to-8 Line Decoder

MM74HCT138 3-to-8 Line Decoder

MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger

NE522 High Speed Dual Differential Comparator/Sense Amp

MC74AC109, MC74ACT109. Dual JK Positive Edge Triggered Flip Flop

NTE74LS181 Integrated Circuit TTL Arithmetic Logic Unit/Function Generator

BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA

74LS393 Dual 4-Bit Binary Counter

74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS

MC74AC259, MC74ACT Bit Addressable Latch

MM74HC154 4-to-16 Line Decoder

SN74LS42MEL. One of Ten Decoder LOW POWER SCHOTTKY

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

Schmitt-Trigger Inverter/ CMOS Logic Level Shifter

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163. Synchronous Presettable Binary Counter

MM74HC175 Quad D-Type Flip-Flop With Clear

FACT DATA 5-1 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

MM74HC139 Dual 2-To-4 Line Decoder

74F153 Dual 4-Input Multiplexer

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

FACT DATA 5-1 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS

SN74LS166MEL. 8 Bit Shift Registers LOW POWER SCHOTTKY

74FST Bit Bus Switch

CD4028BC BCD-to-Decimal Decoder

SN74LS138MEL LOW POWER SCHOTTKY

MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger

DM74LS14 Hex Inverter with Schmitt Trigger Inputs

74AC153 74ACT153 Dual 4-Input Multiplexer

DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear

FST Bit Bus Switch

SN74LS85MEL LOW POWER SCHOTTKY

MC74VHC132. Quad 2 Input NAND Schmitt Trigger

MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS

MC74VHC14. Hex Schmitt Inverter

74LS240 / 74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver

NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output

MM74HC00 Quad 2-Input NAND Gate

LOW POWER SCHOTTKY. MODE SELECT TRUTH TABLE ORDERING INFORMATION GUARANTEED OPERATING RANGES OPERATING MODE

MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop

MC74HC138A. 1-of-8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS

MC1403, B. Low Voltage Reference PRECISION LOW VOLTAGE REFERENCE

DM74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Connection Diagram. Logic Diagram. Function Table (Each Latch)

MM74HC251 8-Channel 3-STATE Multiplexer

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

NTE74177 Integrated Circuit TTL 35Mhz Presettable Binary Counter/Latch

74FST Bit, 4 Port Bus Exchange Switch

MC74HC139A. Dual 1 of 4 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS

Dual JK Flip-Flop IW4027B TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE. Rev. 00

Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS

MC74AC259, MC74ACT Bit Addressable Latch

MM74HC244 Octal 3-STATE Buffer

74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver

MM74HC175 Quad D-Type Flip-Flop With Clear

MM74HC32 Quad 2-Input OR Gate

1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS

NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

MM74HCT540 MM74HCT541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer

MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register

FEATURES OF 74F06A, 74F07A

MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

74F Bit Random Access Memory with 3-STATE Outputs

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS160A and LS161A *SR for LS162A and LS163A

NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs

MM74HCT08 Quad 2-Input AND Gate

MM54HCT193 MM74HCT193 Synchronous Binary Up Down Counters

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.

Transcription:

The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Fully Buffered Complementary Outputs Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature Range 0 25 70 C I OH Output Current High 0.4 ma I OL Output Current Low 8.0 ma PLASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 75B ORDERING INFORMATION Device Package Shipping SN74LS5N Pin DIP 00 Units/Box SN74LS5D Pin 2500/Tape & Reel

CONNECTION DIAGRAM DIP (TOP VIEW) V CC I 4 I 5 I 6 I 7 S 0 S S 2 5 4 3 2 0 9 2 3 4 5 6 7 8 I 3 I 2 I I 0 Z Z E GND LOADING (Note a) PIN NAMES HIGH LOW S 0 S 2 E I 0 I 7 Z Z Select Inputs Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output 0.5 U.L. 0.5 U.L. 0.5 U.L. 0 U.L. 0 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) TTL Unit Load (U.L.) = 40 A HIGH/.6 ma LOW. b) The Output LOW drive factor is 5 U.L. for Commercial (74) Temperature Ranges. LOGIC SYMBOL 7 4 3 2 5 4 3 2 0 9 E I 0 S 0 I I 2 I 3 I 4 I 5 I 6 I 7 S S 2 Z Z 6 5 V CC = PIN GND = PIN 8 2

LOGIC DIAGRAM I 0 I I 2 I 3 I 4 I 5 I 6 I 7 S 2 S S 0 E 9 0 7 4 3 2 5 4 3 2 V CC = PIN GND = PIN 8 = PIN NUMBERS 6 5 Z Z FUNCTIONAL DESCRIPTION The LS5 is a logical implementation of a single pole, 8-position switch with the switch position controlled by the state of three Select inputs, S 0, S, S 2. Both assertion and negation outputs are provided. The Enable input (E) is active LOW. When it is not activated, the negation output is HIGH and the assertion output is LOW regardless of all other inputs. The logic function provided at the output is: Z = E (I 0 S 0 S S 2 + I S 0 S S 2 + I 2 S 0 S S 2 + I 3 S 0 S S 2 + I 4 S 0 S S 2 + I 5 S 0 S S 2 + I 6 S 0 S S 2 + I 7 S 0 S S 2 ). The LS5 provides the ability, in one package, to select from eight sources of data or control information. By proper manipulation of the inputs, the LS5 can provide any logic function of four variables and its negation. TRUTH TABLE E S 2 S S 0 I 0 I I 2 I 3 I 4 I 5 I 6 I 7 Z Z H X X X X X X X X X X X H L L L L L L X X X X X X X H L L L L L H X X X X X X X L H L L L H X L X X X X X X H L L L L H X H X X X X X X L H L L H L X X L X X X X X H L L L H L X X H X X X X X L H L L H H X X X L X X X X H L L L H H X X X H X X X X L H L H L L X X X X L X X X H L L H L L X X X X H X X X L H L H L H X X X X X L X X H L L H L H X X X X X H X X L H L H H L X X X X X X L X H L L H H L X X X X X X H X L H L H H H X X X X X X X L H L L H H H X X X X X X X H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care 3

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditio V IH Input HIGH Voltage 2.0 V V IL Input LOW Voltage 0.8 V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp Diode Voltage 0.65.5 V V CC = MIN, I IN = 8 ma V OH Output HIGH Voltage 2.7 3.5 V V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V OL I IH Output LOW Voltage Input HIGH Current 0.25 0.4 V I OL = 4.0 ma V CC = V CC MIN, V IN = V IL or V IH 0.35 0.5 V I OL = 8.0 ma per Truth Table µa V CC = MAX, V IN = 2.7 V 0. ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note ) 00 ma V CC = MAX I CC Power Supply Current 0 ma V CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CHARACTERISTICS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditio Select to Output Z Select to Output Z Enable to Output Z Enable to Output Z Data to Output Z Data to Output Z 27 8 4 26 5 8 3 2 43 30 23 32 42 32 24 30 32 26 2 V CC = 5.0 V C L = 5 pf AC WAVEFORMS V IN V IN V OUT V OUT Figure. Figure 2. 4

PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648 08 ISSUE R A 8 H G F 9 D PL B S C K 0.25 (0.00) M T SEATING T PLANE A M J L M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 8.80 9.55 B 0.250 0.270 6.35 6.85 C 0.45 0.75 3.69 4.44 D 0.05 0.02 0.39 0.53 F 0.040 0.70.02.77 G 0.00 BSC 2.54 BSC H 0.050 BSC.27 BSC J 0.008 0.05 0.2 0.38 K 0.0 0.30 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 0 0 0 S 0.0 0.040 0.5.0 5

PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 75B 05 ISSUE J T SEATING PLANE 9 8 G A K B D PL 0.25 (0.00) M T B S A S P 8 PL 0.25 (0.00) M B S C M R X 45 J F NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.80 0.00 0.386 0.393 B 3.80 4.00 0.50 0.57 C.35.75 0.054 0.068 D 0.35 0.49 0.04 0.09 F 0.40.25 0.0 0.049 G.27 BSC 0.050 BSC J 0.9 0.25 0.008 0.009 K 0.0 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6. 0.229 0.244 R 0.25 0.50 0.00 0.09 6