CMOS Low Cost, 0-Bit Multiplying DAC FEATUES Low cost 0-bit DAC Low cost AD750 replacement Linearity: ½,, or Low power dissipation Full -quadrant multiplying DAC CMOS/TTL direct interface Latch free (protection Schottky not required) Endpoint linearity APPLICATIONS Digitally controlled attenuators Programmable gain amplifiers Function generation Linear automatic gain controls GENEAL DESCIPTION The is a low cost, 0-bit, -quadrant multiplying DAC manufactured using an advanced thin-film-on-monolithic- CMOS wafer fabrication process. Pin and function equivalent to the AD750 industry standard, the is recommended as a lower cost alternative for old AD750 sockets or new 0-bit DAC designs. application flexibility is demonstrated by its ability to interface to TTL or CMOS, operate on 5 V to 5 V power, and provide proper binary scaling for reference inputs of either positive or negative polarity. FUNCTIONAL BLOCK DIAGAM 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ S S S SN I OUT 0kΩ FB BIT () BIT BIT BIT 0 () S (DTL/TTL/CMOS COMPATIBLE) Figure. 0-00 ev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA 006-906, U.S.A. Tel: 78.9.700 www.analog.com Fax: 78.6. 007 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... evision History... Specifications... Absolute Maximum atings... ESD Caution... Terminology... 5 Pin Configurations and Function Descriptions... 6 Circuit Description...7 General Circuit Information...7 Equivalent Circuit Analysis...7 Operation...8 Unipolar Binary Code...8 Bipolar (Offset Binary) Code...8 Applications...9 Outline Dimensions... 0 Ordering Guide... EVISION HISTOY /07 ev. B to ev. C Changes to Table... Changes to Table... Changes to Figure, Figure, and Figure 7... 9 Updated Outline Dimensions... 0 Changes to Ordering Guide... /0 ev. 0 to ev. A Changes to Specifications... Changes to Absolute Maximum atings... Changes to Ordering Guide... Updated Outline Dimensions...7 /06 ev. A to ev. B Updated Format...Universal Changes to Absolute Maximum atings... Added Pin Configurations and Function Descriptions Section... 6 Updated Outline Dimensions... 0 Changes to Ordering Guide... ev. C Page of
SPECIFICATIONS VDD = 5 V, VOUT = VOUT = 0 V, VEF = 0 V, unless otherwise noted. Table. Parameter TA = 5 C TA = Operating ange Test Conditions STATIC ACCUACY esolution 0 Bits 0 Bits elative Accuracy JN, AQ, ±0.% FS maximum ±0.% FS maximum SQ, JP KN, BQ, ±0.% FS maximum ±0.% FS maximum KP, TE LN, CQ, UQ ±0.05% FS maximum ±0.05% FS maximum DNL ± maximum ± maximum Gain Error, ±% FS maximum ±% FS maximum Digital input = VINH Supply ejection Gain/ VDD 0.00%/% maximum 0.00%/% maximum Digital inputs = VINH, VDD = V to 7 V Output Leakage Current IOUT ±5 na maximum ±00 na maximum Digital inputs = VINL, VEF = ±0 V IOUT ±5 na maximum ±00 na maximum Digital inputs = VINH, VEF = ±0 V DYNAMIC ACCUACY Output Current Settling Time 600 ns maximum 800 ns 5 To 0.05% FS; LOAD = 00 Ω, digital inputs = VINH to VINL or VINL to VINH Feedthrough Error ±0.05% FS maximum 5 ±0.% FS maximum 5 Digital inputs = VINL, VEF = ±0 V, 00 khz sine wave Propagation Delay 00 ns typical 00 ns typical Glitch Impulse 00 nv-s typical 00 nv-s typical EFEENCE Input esistance (VEF) 5 kω min, 0 kω maximum 5 kω min, 0 kω maximum 6 kω nominal ANALOG OUTPUTS Output Capacitance CIOUT 50 pf maximum 5 00 pf maximum 5 Digital inputs = VINH CIOUT 0 pf maximum 5 5 pf maximum 5 CIOUT 0 pf maximum 5 5 pf maximum 5 CIOUT 50 pf maximum 5 00 pf maximum 5 Digital inputs = VINL S Input High Voltage (VINH). V minimum. V minimum Input Low Voltage (VINL) 0.8 V maximum 0.8 V maximum Input Leakage Current (IIN) ± μa maximum ± μa maximum VIN = 0 V and VDD Input Capacitance (CIN) 8 pf maximum 5 8 pf maximum 5 POWE EQUIEMENTS VDD 5 V ± 0% 5 V ± 0% ated accuracy VDD anges 5 5 V to 6 V 5 V to 6 V Functionality with degraded performance IDD ma maximum ma maximum Digital inputs = VINL or VINH D 5 μa maximum 50 μa maximum Digital inputs over VIN FS = full-scale range. Full scale (FS) = VEF. Maximum gain change from TA = 5 C to TMIN or TMAX is ±0.% FS. AC parameter, sample tested to ensure specification compliance. 5 Guaranteed, not tested. 6 Absolute temperature coefficient is approximately 00 ppm/ C. ev. C Page of
ABSOLUTE MAXIMUM ATINGS TA = 5 C unless otherwise noted. Table. Parameter ating VDD to 0. V, +7 V FB to ±5 V VEF to ±5 V Digital Input Voltage ange 0. V to VDD + 0. V IOUT, IOUT to 0. V to VDD Power Dissipation (Any Package) To 75 C 50 mw Derates above 75 C by 6 mw/ C Operating Temperature ange Plastic (JN, JP, KN, KP, LN Versions) 0 C to +85 C Hermetic (AQ, BQ, CQ Versions) 0 C to +85 C Hermetic (SQ, TE, UQ Versions) 55 C to +5 C Storage Temperature ange 65 C to +50 C Lead Temperature (Soldering, 0 sec) 00 C Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ev. C Page of
TEMINOLOGY elative Accuracy elative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for ideal zero and full scale and is expressed in % of full-scale range or (sub) multiples of. esolution Value of the. For example, a unipolar converter with n bits has a resolution of ( n ) (VEF). A bipolar converter of n bits has a resolution of [ (n ) ] (VEF). esolution in no way implies linearity. Settling Time Time required for the output function of the DAC to settle to within ½ for a given digital input stimulus, that is, 0 to full scale. Gain Error Gain error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all s in the DAC after offset error is adjusted out and is expressed in s. Gain error is adjustable to zero with an external potentiometer. Feedthrough Error Error caused by capacitive coupling from VEF to output with all switches off. Output Capacitance Capacity from IOUT and IOUT terminals to ground. Output Leakage Current Current that appears on IOUT terminal with all digital inputs low or on IOUT terminal when all inputs are high. ev. C Page 5 of
PIN CONFIGUATIONS AND FUNCTION DESCIPTIONS I OUT BIT () BIT 5 BIT 6 BIT 7 TOP VIEW (Not to Scale) 6 FB 5 V DD BIT 0 () BIT 9 BIT 8 0 BIT 7 BIT 5 8 9 BIT 6 0-00 BIT () 5 NC 6 BIT 7 BIT 8 I OUT NC FB 0 9 TOP VIEW (Not to Scale) 8 V DD 7 BIT 0 () 6 NC 5 BIT 9 BIT 8 Figure. 6-Lead PDIP Pin Configuration 9 0 NC = NO CONNECT BIT BIT 5 NC BIT 6 BIT 7 0-005 I OUT 6 FB 5 V DD BIT () TOP VIEW BIT 0 () BIT 5 (Not to Scale) BIT 9 BIT 6 BIT 8 BIT 7 0 BIT 7 BIT 5 8 9 BIT 6 Figure. 6-Lead SOIC Pin Configuration 0-00 Figure 5. 0-Terminal LCC Pin Configuration BIT () 5 NC 6 BIT 7 BIT 8 I OUT NC FB 0 9 PIN INDENTFIE TOP VIEW (Not to scale) 8 V DD 7 BIT 0 () 6 NC 5 BIT 9 BIT 8 I OUT 6 FB 5 V DD BIT () TOP VIEW BIT 0 () BIT 5 (Not to Scale) BIT 9 BIT 6 BIT 8 BIT 7 0 BIT 7 BIT 5 8 9 BIT 6 0-00 9 0 BIT BIT 5 NC BIT 6 BIT 7 NC = NO CONNECT Figure 6. 0-Lead PLCC Pin Configuration 0-006 Figure. 6-Lead CEDIP Pin Configuration Table. Pin Function Descriptions Pin Number 6-Lead PDIP, SOIC, CEDIP 0-Lead LCC, PLCC Mnemonic Description IOUT DAC Current Output. IOUT DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground. to 5, 7 to 0, to 5, 7 BIT to BIT 0 to. 8 VDD Positive Power Supply Input. These parts can be operated from a supply of 5 V to 6 V. 5 9 VEF DAC eference Voltage Input Terminal. 6 0 FB DAC Feedback esistor Pin. Establish voltage output for the DAC by connecting FB to external amplifier output. NA, 6,, 6 NC No Connect. ev. C Page 6 of
CICUIT DESCIPTION GENEAL CICUIT INFOMATION The is a 0-bit multiplying DAC that consists of a highly stable thin-film - ladder and ten CMOS current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. The simplified D/A circuit is shown in Figure 7. An inverted - ladder structure is used, that is, the binarily weighted currents are switched between the IOUT and IOUT bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. 0kΩ BIT () 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ S S S SN BIT BIT 0kΩ S (DTL/TTL/CMOS COMPATIBLE) Figure 7. Functional Diagram BIT 0 () 0kΩ 0kΩ I OUT One of the CMOS current switches is shown in Figure 8. The geometries of Device, Device, and Device are optimized to make the digital control inputs DTL/TTL/CMOS compatible over the full military temperature range. The input stage drives two inverters (Device, Device 5, Device 6, and Device 7), which in turn drive the two output N channels. The on resistances of the switches are binarily sealed so that the voltage drop across each switch is the same. For example, Switch in Figure 8 is designed for an on resistance of 0 Ω, Switch for 0 Ω, and so on. For a 0 V reference input, the current through Switch is 0.5 ma, the current through Switch is 0.5 ma, and so on, thus maintaining a constant 0 mv drop across each switch. It is essential that each switch voltage drop be equal if the binarily weighted current division property of the ladder is to be maintained. FB 0-00 DTL/TTL/ CMOS V+ 50Ω Figure 8. CMOS Switch EQUIVALENT CICUIT ANALYSIS 5 6 7 8 9 TO LADDE I OUT The equivalent circuits for all digital inputs high and digital inputs low are shown in Figure 9 and Figure 0. In Figure 9 with all digital inputs low, the reference current is switched to IOUT. The current source ILEAKAGE is composed of surface and junction leakages to the substrate, while the I/0 current source represents a constant -bit current drain through the termination resistor on the - ladder. The on capacitance of the output N channel switch is 00 pf, as shown on the IOUT terminal. The off switch capacitance is 5 pf, as shown on the IOUT terminal. Analysis of the circuit for all digital inputs high, as shown in Figure 0, is similar to Figure 9; however, the on switches are now on Terminal IOUT. Therefore, there is the 00 pf at that terminal. I EF 0kΩ I/0 I LEAKAGE I LEAKAGE 5pF 00pF Figure 9. Equivalent Circuit All Digital Inputs Low I EF I/0 0kΩ I LEAKAGE I LEAKAGE 00pF 5pF Figure 0. Equivalent Circuit All Digital Inputs High FB I OUT FB I OUT 0-008 0-009 0-007 ev. C Page 7 of
OPEATION UNIPOLA BINAY CODE Table. Unipolar Binary Operation (-Quadrant Multiplication) Digital Input Analog Output (VOUT as shown in Figure ) 0 EF 0 0 0 0 0 0 0 0 0 5 EF 0 0 0 0 0 0 0 0 0 0 5 VEF = EF 0 0 5 EF 0 0 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 0 0 0 0 EF = 0 0 Nominal magnitude for the circuit of Figure is given by = UNIPOLA 0 5 BIPOLA ANALOG ±0V kω V DD FB 0Ω 6 I OUT NOTES. AND USED ONLY IF GAIN ADJUSTMENT IS EQUIED.. C PHASE COMPENSATION (5pF TO 5pF) MAY BE EQUIED WHEN USING HIGH SPEED AMPLIFIE. Figure. Unipolar Binary Operation (-Quadrant Multiplication) C V OUT 0-00 BIPOLA (OFFSET BINAY) CODE Table 5. Unipolar Binary Operation (-Quadrant Multiplication) Digital Input Analog Output (VOUT as shown in Figure ) 5 + V EF 5 0 0 0 0 0 0 0 0 + V EF 5 0 0 0 0 0 0 0 0 0 0 0 EF 5 0 0 0 0 0 0 0 0 0 5 EF 5 0 0 0 0 0 0 0 0 0 0 5 EF 5 Nominal magnitude for the circuit of Figure is given by BIPOLA = kω 5 5 BIPOLA ANALOG ±0V V DD 6 0Ω I OUT NOTES.,, AND 5 SELECTED FO MATCHING AND TACKING.. AND USED ONLY IF GAIN ADJUSTMENT IS EQUIED.. C PHASE COMPENSATION (5pF TO 5pF) MAY BE EQUIED WHEN USING HIGH SPEED AMPLIFIES. C A 0kΩ 0kΩ 6 5kΩ 5 0kΩ Figure. Bipolar Operation (-Quadrant Multiplication) A V OUT 0-0 ev. C Page 8 of
APPLICATIONS BIPOLA ANALOG ±0V V DD MAGNITUDE BITS SIGN BIT 5 FB 0kΩ 6 I OUT / AD75DIJN 5kΩ OP97 Figure. 0-Bit and Sign Multiplying DAC 0kΩ OP97 V OUT 0-0 FEQUENCY CONTOL WOD CALIBATE 0V 5 +5V V DD NC 6 I OUT 6.8V () kω OP97 0kΩ % Ct OP97.7kΩ 0kΩ % f = N ( ) 8tCt t = 0kΩ 0 < N ( 0 ) Figure. Programmable Function Generator SQUAE WAVE TIANGULA WAVE 0-0 V IN I OUT FB 6 +5V 5 BIT D BIT 0 V OUT = V IN D where: BIT BIT BIT 0 V OUT D= + + 0 0 0 < D 0 Figure 5. Divider (Digitally Controlled Gain) 0-0 (TEST LIMIT) 5 +5V TEST (0 TO ) 6 I OUT Figure 7. Digitally Programmable Limit Detector AD790 COMPAATO FAIL/PASS TEST 0-06 +5V V OUT. BIT D BIT 0 5 FB 6 I OUT D V OUT = = D + + where: BIT BIT BIT 0 D= + + 0 0 0 < D 0 Figure 6. Modified Scale Factor and Offset 0-05 ev. C Page 9 of
OUTLINE DIMENSIONS 0.800 (0.) 0.790 (0.07) 0.780 (9.8) 0.0 (5.) MAX 0.50 (.8) 0.0 (.0) 0.5 (.9) 0.0 (0.56) 0.08 (0.6) 0.0 (0.6) 6 0.00 (.5) BSC 0.070 (.78) 0.060 (.5) 0.05 (.) 9 8 0.80 (7.) 0.50 (6.5) 0.0 (6.0) 0.05 (0.8) MIN SEATING PLANE 0.005 (0.) MIN 0.060 (.5) MAX 0.05 (0.8) GAUGE PLANE 0.5 (8.6) 0.0 (7.87) 0.00 (7.6) 0.0 (0.9) MAX 0.95 (.95) 0.0 (.0) 0.5 (.9) 0.0 (0.6) 0.00 (0.5) 0.008 (0.0) COMPLIANT TO JEDEC STANDADS MS-00-AB CONTOLLING DIMENSIONS AE IN INCHES; MILLIMETE DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF INCH EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. CONE LEADS MAY BE CONFIGUED AS WHOLE O HALF LEADS. Figure 8. 6-Lead Plastic Dual In-Line Package [PDIP] (N-6) Dimensions shown in inches and (millimeters) 0706-B 0.50 (0.) 0.0 (0.976) 6 9 7.60 (0.99) 7.0 (0.9) 8 0.65 (0.9) 0.00 (0.97) 0.0 (0.08) 0.0 (0.009) COPLANAITY.7 (0.0500) BSC.65 (0.0).5 (0.095) 0.0 0.5 (0.00) SEATING PLANE 0. (0.00) 0. (0.0) 0.0 (0.0079) 8 0 0.75 (0.095) 0.5 (0.0098) 5.7 (0.0500) 0.0 (0.057) COMPLIANT TO JEDEC STANDADS MS-0-AA CONTOLLING DIMENSIONS AE IN MILLIMETES; INCH DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF MILLIMETE EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure 9. 6-Lead Standard Small Outline Package [SOIC_W] Wide Body (W-6) Dimensions shown in millimeters and (inches) 906-B ev. C Page 0 of
0.005 (0.) MIN 0.098 (.9) MAX 6 9 8 0.0 (7.87) 0.0 (5.59) PIN 0.00 (.5) BSC 0.80 (.) MAX 0.00 (5.08) MAX 0.00 (5.08) 0.5 (.8) 0.0 (0.58) 0.0 (0.6) 0.070 (.78) 0.00 (0.76) 0.060 (.5) 0.05 (0.8) 0.50 (.8) MIN SEATING PLANE 0.0 (8.) 0.90 (7.7) 5 0 0.05 (0.8) 0.008 (0.0) CONTOLLING DIMENSIONS AE IN INCHES; MILLIMETE DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF INCH EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure 0. 6-Lead Ceramic Dual In-Line Package [CEDIP] (Q-6) Dimensions shown in inches and (millimeters) 0.58 (9.09) 0. (8.69) SQ 0.00 (.5) 0.06 (.6) 0.58 (9.09) MAX SQ 0.088 (.) 0.05 (.7) 0.075 (.9) EF 0.095 (.) 0.075 (.90) 0.0 (0.8) 0.007 (0.8) TYP 0.075 (.9) EF 0.055 (.0) 0.05 (.) 9 8 0 BOTTOM VIEW 0.00 (5.08) EF 0.00 (.5) EF 8 9 0.50 (.8) BSC 0.05 (0.8) MIN 0.08 (0.7) 0.0 (0.56) 0.050 (.7) BSC 5 TYP CONTOLLING DIMENSIONS AE IN INCHES; MILLIMETE DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF INCH EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure. 0-Terminal Ceramic Leadless Chip Carrier [LCC] (E-0-) Dimensions shown in inches and (millimeters) 006-A 0.08 (.) 0.0 (.07) 0.00 (0.5) 0.08 (. ) 0.0 (.07) 9 PIN 8 IDENTIFIE TOP VIEW (PINS DOWN) 8 9 0.56 (9.0) 0.50 (8.89) SQ 0.95 (0.0) 0.85 (9.78) SQ 0.056 (.) 0.0 (.07) 0.050 (.7) BSC 0.80 (.57) 0.65 (.9) 0.0 (.0) 0.090 (.9) 0.0 (0.5) MIN 0.0 (0.5) 0.0 (0.) 0.0 (8.8) 0.0 (0.8) 0.90 (7.7) 0.06 (0.66) 0.05 (.) 0.05 (0.6) 0.00 (0.50) COMPLIANT TO JEDEC STANDADS MO-07-AA CONTOLLING DIMENSIONS AE IN INCHES; MILLIMETE DIMENSIONS (IN PAENTHESES) AE OUNDED-OFF INCH EQUIVALENTS FO EFEENCE ONLY AND AE NOT APPOPIATE FO USE IN DESIGN. Figure. 0-Lead Plastic Leaded Chip Carrier [PLCC] (P-0) Dimensions shown in inches and (millimeters) BOTTOM VIEW (PINS UP) ev. C Page of
T TTT ODEING GUIDE Model Temperature ange Package Description Package Option Nonlinearity (% FS max) ACHIPS DIE JN 0 C to +85 C 6-Lead Plastic Dual In-Line Package [PDIP] N-6 ±0. JNZ 0 C to +85 C 6-Lead Plastic Dual In-Line Package [PDIP] N-6 ±0. KN 0 C to +85 C 6-Lead Plastic Dual In-Line Package [PDIP] N-6 ±0. KNZ 0 C to +85 C 6-Lead Plastic Dual In-Line Package [PDIP] N-6 ±0. LN 0 C to +85 C 6-Lead Plastic Dual In-Line Package [PDIP] N-6 ±0.05 LNZ 0 C to +85 C 6-Lead Plastic Dual In-Line Package [PDIP] N-6 ±0.05 JP 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. JP-EEL 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. JPZ 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. JPZ-EEL 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. KP 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. KP-EEL 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. KPZ 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. KPZ-EEL 0 C to +85 C 0-Lead Plastic Leaded Chip Carrier [PLCC] P-0 ±0. K 0 C to +85 C 6-Lead Standard Small Outline Package [SOIC_W] W-6 ±0. K-EEL 0 C to +85 C 6-Lead Standard Small Outline Package [SOIC_W] W-6 ±0. KZ 0 C to +85 C 6-Lead Standard Small Outline Package [SOIC_W] W-6 ±0. KZ-EEL 0 C to +85 C 6-Lead Standard Small Outline Package [SOIC_W] W-6 ±0. AQ 0 C to +85 C 6-Lead Ceramic Dual In-Line Package [CEDIP] Q-6 ±0. BQ 0 C to +85 C 6-Lead Ceramic Dual In-Line Package [CEDIP] Q-6 ±0. CQ 0 C to +85 C 6-Lead Ceramic Dual In-Line Package [CEDIP] Q-6 ±0.05 SQ 55 C to +5 C 6-Lead Ceramic Dual In-Line Package [CEDIP] Q-6 ±0. UQ 55 C to +5 C 6-Lead Ceramic Dual In-Line Package [CEDIP] Q-6 ±0.05 UQ/88B 55 C to +5 C 6-Lead Ceramic Dual In-Line Package [CEDIP] Q-6 ±0.05 TE/88B 55 C to +5 C 0-Terminal Ceramic Leadless Chip Carrier [LCC] E-0- ±0. Z = ohs compliant part. 007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C0-0-/07(C) ev. C Page of