INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23
FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified from 40 to +85 C and 40 to +25 C. DESCRIPTION The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7. The 74HC/HCT04 provide six inverting buffers. QUICK REFERENCE DT GND = 0 V; T amb =25 C; t r =t f 6.0 ns. TYPICL SYMBOL PRMETER CONDITIONS HC04 HCT04 UNIT t PHL /t PLH propagation delay n to ny C L = 5 pf; V CC = 5 V 7 8 ns C I input capacitance 3.5 3.5 pf C PD power dissipation capacitance per gate notes and 2 2 24 pf Notes. C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts; N = total load switching outputs; Σ(C L V 2 CC f o ) = sum of the outputs. 2. For 74HC04: the condition is V I = GND to V CC. For 74HCT04: the condition is V I = GND to V CC.5 V. FUNCTION TBLE See note. INPUT n L H OUTPUT ny H L Note. H = HIGH voltage level; L = LOW voltage level. 2003 Jul 23 2
ORDERING INFORMTION PCKGE TYPE NUMBER TEMPERTURE RNGE PINS PCKGE MTERIL CODE 74HC04N 40 to +25 C 4 DIP4 plastic SOT27-74HCT04N 40 to +25 C 4 DIP4 plastic SOT27-74HC04D 40 to +25 C 4 SO4 plastic SOT08-74HCT04D 40 to +25 C 4 SO4 plastic SOT08-74HC04DB 40 to +25 C 4 SSOP4 plastic SOT337-74HCT04DB 40 to +25 C 4 SSOP4 plastic SOT337-74HC04PW 40 to +25 C 4 TSSOP4 plastic SOT402-74HCT04PW 40 to +25 C 4 TSSOP4 plastic SOT402-74HC04BQ 40 to +25 C 4 DHVQFN4 plastic SOT762-74HCT04BQ 40 to +25 C 4 DHVQFN4 plastic SOT762- PINNING PIN SYMBOL DESCRIPTION data input 2 Y data output 3 2 data input 4 2Y data output 5 3 data input 6 3Y data output 7 GND ground (0 V) 8 4Y data output 9 4 data input 0 5Y data output 5 data input 2 6Y data output 3 6 data input 4 V CC supply voltage handbook, halfpage Fig. Y 2 2Y 3 3Y GND 2 3 4 5 6 04 7 8 MN340 4 3 2 0 9 V CC 6 6Y 5 5Y 4 4Y Pin configuration DIP4, SO4 and (T)SSOP4. 2003 Jul 23 3
handbook, halfpage Y 2 V CC 4 3 6 handbook, halfpage Y 2 2 3 2 6Y 3 2 2Y 4 2Y 4 GND () 5 5 3 3Y 6 3 5 0 5Y 9 4 4Y 8 3Y 6 9 4 5 5Y 0 Top view 7 GND 8 4Y MBL760 3 6 6Y 2 MN342 () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN4. Fig.3 Logic symbol. handbook, halfpage 2 3 4 5 6 9 8 handbook, halfpage MN34 Y 0 3 2 MN343 Fig.4 IEC logic symbol. Fig.5 Logic diagram (one inverter). 2003 Jul 23 4
RECOMMENDED OPERTING CONDITIONS SYMBOL PRMETER CONDITIONS 74HC04 74HCT04 MIN. TYP. MX. MIN. TYP. MX. UNIT V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 V CC 0 V CC V V O output voltage 0 V CC 0 V CC V T amb ambient temperature see DC and C characteristics per device 40 +25 +25 40 +25 +25 C t r, t f input rise and fall times V CC = 2.0 V 000 ns V CC = 4.5 V 6.0 500 6.0 500 ns V CC = 6.0 V 400 ns LIMITING VLUES In accordance with the bsolute Maximum Rating System (IEC 6034); voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER CONDITIONS MIN. MX. UNIT V CC supply voltage 0.5 +7.0 V I IK input diode current V I < 0.5 V or V I >V CC + 0.5 V ±20 m I OK output diode current V O < 0.5 V or V O >V CC + 0.5 V ±20 m I O output source or sink 0.5V<V O <V CC + 0.5 V ±25 m current I CC, I GND V CC or GND current ±50 m T stg storage temperature 65 +50 C P tot power dissipation DIP4 package T amb = 40 to +25 C; note 750 mw other packages T amb = 40 to +25 C; note 2 500 mw Notes. For DIP4 packages: above 70 C derate linearly with 2 mw/k. 2. For SO4 packages: above 70 C derate linearly with 8 mw/k. For SSOP4 and TSSOP4 packages: above 60 C derate linearly with 5.5 mw/k. For DHVQFN4 packages: above 60 C derate linearly with 4.5 mw/k. 2003 Jul 23 5
DC CHRCTERISTICS Type 74HC04 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb =25 C V IH HIGH-level input voltage 2.0.5.2 V 4.5 3.5 2.4 V 6.0 4.2 3.2 V V IL LOW-level input voltage 2.0 0.8 0.5 V 4.5 2..35 V 6.0 2.8.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 2.0.9 2.0 V I O = 20 µ 4.5 4.4 4.5 V I O = 4.0 m 4.5 3.98 4.32 V I O = 20 µ 6.0 5.9 6.0 V I O = 5.2 m 6.0 5.48 5.8 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 2.0 0 0. V I O =20µ 4.5 0 0. V I O = 4.0 m 4.5 0.5 0.26 V I O =20µ 6.0 0 0. V I O = 5.2 m 6.0 0.6 0.26 V I LI input leakage current V I =V CC or GND 6.0 0. ±0. µ I OZ 3-state output OFF current V I =V IH or V IL ; 6.0 ±.0.5 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O = 0 6.0 2 µ 2003 Jul 23 6
SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb = 40 to +85 C V IH HIGH-level input voltage 2.0.5 V 4.5 3.5 V 6.0 4.2 V V IL LOW-level input voltage 2.0 0.5 V 4.5.35 V 6.0.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 2.0.9 V I O = 20 µ 4.5 4.4 V I O = 4.0 m 4.5 3.84 V I O = 20 µ 6.0 5.9 V I O = 5.2 m 6.0 5.34 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 2.0 0. V I O =20µ 4.5 0. V I O = 4.0 m 4.5 0.33 V I O =20µ 6.0 0. V I O = 5.2 m 6.0 0.33 V I LI input leakage current V I =V CC or GND 6.0 ±.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; 6.0 ±.5.0 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O = 0 6.0 20 µ 2003 Jul 23 7
SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb = 40 to +25 C V IH HIGH-level input voltage 2.0.5 V 4.5 3.5 V 6.0 4.2 V V IL LOW-level input voltage 2.0 0.5 V 4.5.35 V 6.0.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 2.0.9 V I O = 20 µ 4.5 4.4 V I O = 20 µ 6.0 5.9 V I O = 4.0 m 4.5 3.7 V I O = 5.2 m 6.0 5.2 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 2.0 0. V I O =20µ 4.5 0. V I O =20µ 6.0 0. V I O = 4.0 m 4.5 0.4 V I O = 5.2 m 6.0 0.4 V I LI input leakage current V I =V CC or GND 6.0 ±.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; 6.0 ±0.0 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O = 0 6.0 40 µ 2003 Jul 23 8
Type 74HCT04 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. UNIT T amb =25 C V IH HIGH-level input voltage 4.5 to 5.5 2.0.6 V V IL LOW-level input voltage 4.5 to 5.5.2 0.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 4.5 4.4 4.5 V I O = 4.0 m 4.5 3.84 4.32 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 4.5 0 0. V I O = 4.0 m 4.5 0.5 0.26 V I LI input leakage current V I =V CC or GND 5.5 ±0. µ I OZ 3-state output OFF current V I =V IH or V IL ; V O =V CC or GND; I O =0 5.5 ±0.5 µ I CC quiescent supply current V I =V CC or GND; 5.5 2 µ I O =0 I CC additional supply current per input V I =V CC 2. V; I O =0 4.5 to 5.5 20 432 µ T amb = 40 to +85 C V IH HIGH-level input voltage 4.5 to 5.5 2.0 V V IL LOW-level input voltage 4.5 to 5.5 0.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 4.5 4.4 V I O = 4.0 m 4.5 3.84 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 4.5 0. V I O = 4.0 m 4.5 0.33 V I LI input leakage current V I =V CC or GND 5.5 ±.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; V O =V CC or GND; I O =0 5.5 ±5.0 µ I CC quiescent supply current V I =V CC or GND; I O =0 I CC additional supply current per input V I =V CC 2. V; I O =0 5.5 20 µ 4.5 to 5.5 540 µ 2003 Jul 23 9
SYMBOL PRMETER TEST CONDITIONS OTHER T amb = 40 to +25 C V IH HIGH-level input voltage 4.5 to 5.5 2.0 V V IL LOW-level input voltage 4.5 to 5.5 0.8 V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 4.5 4.4 V I O = 4.0 m 4.5 3.7 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 4.5 0. V I O = 4.0 m 4.5 0.4 V I LI input leakage current V I =V CC or GND 5.5 ±.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; V O =V CC or GND; I O =0 5.5 ±0 µ I CC quiescent supply current V I =V CC or GND; I O =0 I CC additional supply current per input V I =V CC 2. V; I O =0 V CC (V) MIN. TYP. MX. UNIT 5.5 40 µ 4.5 to 5.5 590 µ 2003 Jul 23 0
C CHRCTERISTICS Family 74HC04 GND = 0 V; t r =t f 6.0 ns; C L =50pF. SYMBOL PRMETER TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT T amb =25 C t PHL /t PLH propagation delay see Figs 6 and 7 2.0 25 85 ns n to ny 4.5 9 7 ns 6.0 7 4 ns t THL /t TLH output transition time see Figs 6 and 7 2.0 9 75 ns 4.5 7 5 ns 6.0 6 3 ns T amb = 40 to +85 C t PHL /t PLH propagation delay see Figs 6 and 7 2.0 05 ns n to ny 4.5 2 ns 6.0 8 ns t THL /t TLH output transition time see Figs 6 and 7 2.0 95 ns 4.5 9 ns 6.0 6 ns T amb = 40 to +25 C t PHL /t PLH propagation delay see Figs 6 and 7 2.0 30 ns n to ny 4.5 26 ns 6.0 22 ns t THL /t TLH output transition time see Figs 6 and 7 2.0 0 ns 4.5 22 ns 6.0 9 ns 2003 Jul 23
Family 74HCT04 GND = 0 V; t r =t f 6.0 ns; C L =50pF. SYMBOL PRMETER TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT T amb =25 C t PHL /t PLH propagation delay see Figs 6 and 7 4.5 0 9 ns n to ny t THL /t TLH output transition time see Figs 6 and 7 4.5 7 5 ns T amb = 40 to +85 C t PHL /t PLH propagation delay see Figs 6 and 7 4.5 24 ns n to ny t THL /t TLH output transition time see Figs 6 and 7 4.5 9 ns T amb = 40 to +25 C t PHL /t PLH propagation delay see Figs 6 and 7 4.5 29 ns n to ny t THL /t TLH output transition time see Figs 6 and 7 4.5 22 ns C WVEFORMS handbook, halfpage V I n input GND V M V M t PHL t PLH V OH ny output V OL 90% V M V M 0% t THL t TLH MN722 For 74HC04: V M = 50%; V I = GND to V CC. For 74HCT04: V M =.3 V; V I = GND to 3.0 V. Fig.6 Waveforms showing the data input (n) to data output (ny) propagation delays and the output transition times. 2003 Jul 23 2
handbook, halfpage V CC PULSE GENERTOR V I D.U.T V O R T C L 50 pf MGK565 Definitions for test circuit: C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. Fig.7 Load circuitry for switching times. 2003 Jul 23 3
PCKGE OUTLINES DIP4: plastic dual in-line package; 4 leads (300 mil) SOT27- D M E seating plane 2 L Z 4 e b b 8 w M c (e ) M H pin index E 7 0 5 0 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2 () () min. max. b b c D E e e L M E M H 4.2 0.5 3.2 0.7 0.02 0.3.73.3 0.068 0.044 0.53 0.38 0.02 0.05 0.36 0.23 0.04 0.009 9.50 8.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 0. 0.3 3.60 3.05 0.4 0.2 8.25 7.80 0.32 0.3 0.0 8.3 0.39 0.33 w 0.254 0.0 () Z max. 2.2 0.087 Note. Plastic or metal protrusions of 0.25 mm (0.0 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT27-050G04 MO-00 SC-50-4 99-2-27 03-02-3 2003 Jul 23 4
SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max..75 2 3 b p c D () E () e H () E L L p Q v w y Z 0.25 0.0 0.069 0.00 0.004.45.25 0.057 0.049 0.25 0.0 0.49 0.36 0.09 0.04 0.25 0.9 0.000 0.0075 8.75 8.55 0.35 0.34 Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included. 4.0 3.8 0.6 0.5.27 0.05 6.2 5.8 0.244 0.228.05 0.04.0 0.4 0.039 0.06 0.7 0.6 0.028 0.024 0.25 0.25 0. 0.0 0.0 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.02 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS-02 99-2-27 03-02-9 2003 Jul 23 5
SSOP4: plastic shrink small outline package; 4 leads; body width 5.3 mm SOT337- D E X c y H E v M Z 4 8 Q 2 ( ) 3 pin index 7 L detail X L p θ e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E () e H E L L p Q v w y Z() max. mm 2 0.2 0.05.80.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 7.9.03 0.9 0.65.25 0.2 7.6 0.63 0.7 0.3 0..4 0.9 θ o 8 o 0 Note. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337- MO-50 99-2-27 03-02-9 2003 Jul 23 6
TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M L detail X L p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm. 0.5 0.05 0.95 0.80 0.25 0.30 0.9 0.2 0. 5. 4.9 4.5 4.3 0.65 6.6 6.2 0.75 0.50 0.4 0.3 0.2 0.3 0. 0.72 0.38 θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE 99-2-27 03-02-8 2003 Jul 23 7
DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e 4 8 3 9 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm 0.05 0.00 0.30 0.8 0.2 3. 2.9.65.35 2.6 2.4.5 0.85 0.5 2 0.5 0.3 0. 0.05 0.05 0. Note. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT762- - - - MO-24 - - - EUROPEN PROJECTION ISSUE DTE 02-0-7 03-0-27 2003 Jul 23 8
DT SHEET STTUS LEVEL DT SHEET STTUS () PRODUCT STTUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Notes. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 6034). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Jul 23 9
a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +3 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Koninklijke Philips Electronics N.V. 2003 SC75 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 63508/03/pp20 Date of release: 2003 Jul 23 Document order number: 9397 750 256