ECE223 R eouven Elz reouven@uwterloo.c Office room: DC3576
Outline Decoders Decoders with Enle VHDL Exmple Multiplexers Multiplexers with Enle VHDL Exmple From Decoder to Multiplexer 3-stte Gtes Multiplexers constructed from 3-stte uffers VHDL Exmple
Decoders An n-to-m (m 2 n ) decoder converts inry informtion from n input lines (n-it coded informtion) to mximum of 2 n unique output lines. I 2 3-to-8 Decoder How? It t genertes e ll the minterms of the n input vriles (to hve exctly one of the outputs t 1 for ech comintion of inputs) O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7
Exmple: 3-to-8 Decoder c O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 0 0 0 1 0 0 0 0 0 0 0 O 0 0 0 1 0 1 0 0 0 0 0 0 O 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 O 0 = c c 3-to-8 Decoder O 2 O 3 O 4 O 5 O 6 O 7 c c O 1 = c O 2 = c O 3 = c O 4 = c O 5 = c O 6 = c O 7 = c
Decoder with Enle Input O 0 e O 0 O 1 O 2 O 3 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 2-to-4 Decoder O 1 O 2 0 1 1 0 0 0 1 1 X X 0 0 0 0 O 3 e O 0 = e O 1 = e O 2 = e O 3 = e e
How to construct 3-to-8 Decoder from 2-to-4 Decoders with Enle? O 0 e 2-to-4 Decoder 2-to-4 Decoder O 1 O 2 O 3 O 4 O 5 O 6 e O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 O 7
VHDL Exmple entity DECODER2-to-4 is port( I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0)); end DECODER2-to-4; rchitecture ehv of DECODER2-to-4 is egin cse I is when "00" => O <= "0001"; when "01" => O <= "0010"; when "10" => O <= "0100"; when "11"" => O <= "1000";" when others => O <= 0000"; end cse; end; 2-to-4 Decoder 2-to-4 Decoder O 0 O 1 O 2 O 3 I O ( ) ( O 1 O 2 O 3 O 4 ) 2 4
Outline Decoders Decoders with Enle VHDL Exmple Multiplexers Multiplexers with Enle VHDL Exmple From Decoder to Multiplexer 3-stte Gtes Multiplexers constructed from 3-stte uffers VHDL Exmple
Multiplexers A 2 n -to-1 multiplexer selects one of its 2 n input vlues nd outputs it dt selector. How? Using control signls tht encode the position of the trgeted input I 2 I 3 I 4 I 5 I 6 8-to-1 Output I 7 How mny control signls? For 2 n inputs, n control signls c
2-to-1 Multiplexer Output = + 2-to-1 Output 0 1 Output
4-to-1 Multiplexer Output = I + I + I + I 0 1 2 3 I 2 4-to-1 Output I 3 I 2 ' ' Output 0 I 3 0 1 1 0 I 2 1 1 I 3
Generl Cse: 2 n -to-1 multiplexer Output = n 2 1 k =0 m k I k I 2 2 n -to-1 Output I 2 n S 0 S 1 S n Minterm k of the n control signls Input designted y the minterm k
4-to-1 Multiplexer with Enle I 2 4-to-1 Output I 3 e e Output 1 0 0 1 0 1 1 1 0 I 2 1 1 1 I 3 0 X X 0
How to construct 8-to-1 Mux from 4-to-1 Muxes with Enle? O 1 e O 1 O 2 Y I 2 I 3 4-to-1 1 0 0 0 e I 4 Or Y 1 0 1 0 1 1 0 I 2 0 I 2 1 1 1 I 3 0 I 3 0 0 0 0 I 4 I 4 I 5 I I6 4-to-1 0 0 1 0 I 5 I 5 O 2 0 1 0 0 I 6 I 6 0 1 1 0 I 7 I 7 I 7
VHDL Exmple entity Mux4-to-1 is port( I0, I1, I2, I3: in std_logic; CTRL: in std_logic_vector(1 downto 0); Output: out std_logic ); end Mux4-to-1; rchitecture ehv of Mux4-to-1 is egin cse CTRL is when "00" => Output <= I0; when "01" => Output <= I1; when "10" => Output <= I2; when "11" => Output <= I3; when others => Output <= I1; end cse; end; I 2 4-to-1 I 3 2 CTRL Output
Outline Decoders Decoders with Enle VHDL Exmple Multiplexers Multiplexers with Enle VHDL Exmple From Decoder to Multiplexer 3-stte Gtes Multiplexers constructed from 3-stte uffers VHDL Exmple
From Decoder to Multiplexer O 0 O 1 O 2 O 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 Output 0 0 0 1 1 0 I 2 1 1 I 3 O 0 O 1 2-to-4 Decoder O 2 O 3 I 2 I 3 4-to-1 Output Output = + + I 2 + I 3 O 0 = O 1 = O 2 = O 3 = I 2 I 3 Or Output
Outline Decoders Decoders with Enle VHDL Exmple Multiplexers Multiplexers with Enle VHDL Exmple From Decoder to Multiplexer 3-stte Gtes Multiplexers constructed from 3-stte uffers VHDL Exmple
3-stte Gtes Component exhiiting three sttes: Logic 1 nd logic 0 sttes s in conventionl gtes High impednce Z stte. Wht is high impednce? (1) The gte ehves like n open circuit Output disconnected (2) The circuit hs no logic significnce (3) The circuit connected to 3-stte gte in high impednce is not ffected y the inputs to the gte. 3-stte uffer: y = if s = 1 Z if s = 0 s
Multiplexers constructed from 3-stte uffers 2-to-1 Mux 4-to-1 Mux 2-to-1 s y s y 0 1 c d 4-to-1 y s 0 s 1 y 0 0 0 1 1 0 c 1 1 d 1 y s 0 s 1 y 2 s 0 s 1 2-to-4 Decoder c s d
VHDL Exmple entity 3-stte_uffer is port( : in std_logic_vector(7 downto 0); s: in std_logic; y: out std_logic_vector(7 downto 0)); end 3-stte_uffer; rchitecture ehv of 3-stte_uffer is egin if s = '1' then y <= ; else y <= "ZZZZZZZZ"; end if; end; s 8 8 y = if s = 1 Z if s = 0