Low-Sensitivity, Highpass Filter Design with Parasitic Compensation

Similar documents

DS0026 Dual High-Speed MOS Driver

Application Note OA-29 Low-Sensitivity, Highpass Filter Design With Parasitic Compensation. Kumen Blake

54AC32 Quad 2-Input OR Gate

DS1691A/DS3691 (RS-422/RS-423) Line Drivers with TRI-STATE Outputs

DS1691A/DS3691 (RS-422/RS-423) Line Drivers with TRI-STATE Outputs

54AC258 54ACT258 Quad 2-Input Multiplexer with TRI-STATE Outputs

54AC174/54ACT174 Hex D Flip-Flop with Master Reset

LP8340 Low Dropout, Low I Q, 1.0A CMOS Linear Regulator

IC Temperature Sensor Provides Thermocouple Cold-Junction Compensation

LM135/LM235/LM335, LM135A/LM235A/LM335A Precision Temperature Sensors

onlinecomponents.com

LM /LM /LM Micropower Voltage Reference Diode

DM74LS154 4-Line to 16-Line Decoder/Demultiplexer

DM7442A BCD to Decimal Decoders

DM7445 BCD to Decimal Decoders/Drivers

Understanding Integrated Circuit Package Power Capabilities

LM /LM /LM Micropower Voltage Reference Diode

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

74LCX138 Low Voltage 1-of-8 Decoder/Demultiplexer with 5V Tolerant Inputs

DM74LS11 Triple 3-Input AND Gates

DM74LS02 Quad 2-Input NOR Gates

DM74LS138, DM74LS139 Decoders/Demultiplexers

LM135/LM235/LM335, LM135A/LM235A/LM335A Precision Temperature Sensors

LM4040 Precision Micropower Shunt Voltage Reference

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application

74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset

MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter

Features. Y Wide supply voltage range 3 0V to 15V. Y Guaranteed noise margin 1 0V. Y High noise immunity 0 45 VCC (typ )

MM74C908 Dual CMOS 30-Volt Relay Driver

LM50 SOT-23 Single-Supply Centigrade Temperature Sensor

54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker

54153 DM54153 DM74153 Dual 4-Line to 1-Line Data Selectors Multiplexers

54LS352 DM74LS352 Dual 4-Line to 1-Line Data Selectors Multiplexers

DM74LS174/DM74LS175 Hex/Quad D Flip-Flops with Clear

74F138 1-of-8 Decoder/Demultiplexer

DM54LS450 DM74LS Multiplexer

DM74LS90/DM74LS93 Decade and Binary Counters

DM74LS181 4-Bit Arithmetic Logic Unit

9312 DM9312 One of Eight Line Data Selectors Multiplexers

MM54C14 MM74C14 Hex Schmitt Trigger

Features. Y Wide supply voltage range 3V to 15V. Y Guaranteed noise margin 1V. Y High noise immunity 0 45 VCC (typ )

LM108/LM108AQML Operational Amplifiers

CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch

MM54C221 MM74C221 Dual Monostable Multivibrator

74F139 Dual 1-of-4 Decoder/Demultiplexer

CD4028BM CD4028BC BCD-to-Decimal Decoder

54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates

54LS00 DM54LS00 DM74LS00 Quad 2-Input NAND Gates

CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger

DM54LS73A DM74LS73A Dual Negative-Edge-Triggered

54LS153 DM54LS153 DM74LS153 Dual 4-Line to 1-Line Data Selectors Multiplexers

MM74C906 Hex Open Drain N-Channel Buffers

CD4023M CD4023C Triple 3-Input NAND Gate CD4025M CD4025C Triple 3-Input NOR Gate

DM7417 Hex Buffers with High Voltage Open-Collector Outputs

A Guide to Board Layout for Best Thermal Resistance for Exposed Packages

54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops

54AC 74AC11 Triple 3-Input AND Gate

74F365 Hex Buffer/Driver with 3-STATE Outputs

CD4013BM CD4013BC Dual D Flip-Flop

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset

54LS85 DM54LS85 DM74LS85 4-Bit Magnitude Comparators

DM Quad 2-Input NAND Buffers with Open-Collector Outputs

MM54HC08 MM74HC08 Quad 2-Input AND Gate

LM35 Precision Centigrade Temperature Sensors

MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear

Features. Y LS174 contains six flip-flops with single-rail outputs. Y LS175 contains four flip-flops with double-rail outputs

Features. Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L

9321 DM9321 Dual 1-of-4 Decoder

DM7404 Hex Inverting Gates

CD4024BC 7-Stage Ripple Carry Binary Counter

CD4029BM CD4029BC Presettable Binary Decade Up Down Counter

Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics

54LS256 DM74LS256 Dual 4-Bit Addressable Latch

CD4028BC BCD-to-Decimal Decoder

Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics

54173 DM54173 DM74173 TRI-STATE Quad D Registers

DM74184 DM74185A BCD-to-Binary and Binary-to-BCD Converters

CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate

Homework Assignment 11

MM54HC148 MM74HC Line Priority Encoder

MM54HC175 MM74HC175 Quad D-Type Flip-Flop With Clear

Features Y Wide analog input voltage range g6v. Y Low on resistance 50 typ (VCC V EE e4 5V) Y Logic level translation to enable 5V logic with g5v

CD4093BM CD4093BC Quad 2-Input NAND Schmitt Trigger

Low Power Quint Exclusive OR/NOR Gate

MM54HC244 MM74HC244 Octal TRI-STATE Buffer

93L34 8-Bit Addressable Latch

LH0094 Multifunction Converter

Features. Y TRI-STATE versions LS157 and LS158 with same pinouts. Y Schottky-clamped for significant improvement in A-C.

DM54LS47 DM74LS47 BCD to 7-Segment Decoder Driver with Open-Collector Outputs

MM54HC154 MM74HC154 4-to-16 Line Decoder

9334 DM Bit Addressable Latch

74VHC574 74VHCT574 Octal D-Type Flip-Flop with 3-STATE Outputs

DM74LS375 4-Bit Latch

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

Understanding Integrated Circuit Package Power Capabilities

NC7SB3157 TinyLogic Low Voltage UHS Analog Switch 2-Channel Multiplexer/Demultiplexer (Preliminary)

CGS74CT to 4 Minimum Skew (300 ps) Clock Driver

Features. Y Wide supply voltage range 3V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL compatibility Fan out of 2

DM5490 DM7490A DM7493A Decade and Binary Counters

Transcription:

Low-Sensitivity, Highpass Filter Design with Parasitic Compensation Introduction This Application Note covers the design of a Sallen-Key highpass biquad. This design gives low component and op amp sensitivities. It also shows how to compensate for the op amp s bandwidth (pre-distortion) and parasitic capacitances. A design example illustrates this method. These biquads are also called KRC or VCVS [voltage-controlled, voltage-source]. Changes in component values over process, environment and time affect the performance of a filter. To achieve a greater production yield, the filter needs to be insensitive to these changes. This Application Note presents a design algorithm that results in low sensitivity to component variation. See [6] for information on evaluating the sensitivity performance of your filter. To achieve the best production yield, the nominal filter design must also compensate for component and board parasitics. The components are pre-distorted [5] to compensate for the op amp bandwidth. This Application Note expands the pre-distortion method in [5] to include compensation for parasitic capacitances. This method is valid for either voltage-feedback or current-feedback op amps. Parasitic Compensation To pre-distort your filter components and compensate for parasitic capacitances:. Use the method in [5] to include the op amp s effect on the filter response. The result is a transfer function of the same order whose coefficients include the op amp group delay (τ oa ) evaluated at the passband edge frequency (f c ).. For all parasitic capacitances in parallel with capacitors: Add the capacitors together Simplify the resulting coefficients Use the sum of time constants form for the coefficients when possible 3. For all parasitic capacitances in parallel with resistors: Replace the resistor R x in the filter transfer function with the parallel equivalent of R x and C p. Rx Rx R C s,s j + x p Alter this impedance to a convenient form and simplify: Do not create new terms (a coefficient times a new power of s) in the transfer function after simplifying OA-9 Kumen Blake October 996 The most useful approximations are: Rx Rx RxCps ( + RxCps) ( ) RCs x p Re x These approximations are valid when: << RC x p Convert ( + R x C p s) to the exponential form (a pure time delay) when it multiplies, or divides, the entire transfer function Do not change the gain at p in allpass sections When simplifying, discard any terms that are products of the error terms (kτ oa and R x C p ); they are negligible Use the sum of time constants form for the coefficients when possible Use an op amp with adequate bandwidth (f 3dB ) and slew rate (SR): f 3dB 0f H SR > 5f H V peak where f H is the highest frequency in the passband of the filter, and V peak is the largest peak voltage. This increases the accuracy of the pre-distortion algorithm. It also reduces the filter s sensitivity to op amp performance changes over temperature and process. Make sure the op amp is stable at a gain of A V K. KRC Highpass Biquad Design The biquad shown in Figure is a Sallen-Key highpass biquad. V in needs to be a voltage source with low output impedance. The transfer function is: Vo Vin + H s p s + pq p p s Low-Sensitivity, Highpass Filter Design with Parasitic Compensation OA-9 00 Corporation AN0796 www.national.com

OA-9 KRC Highpass Biquad Design (Continued) K + R f Rg H K RC 5 RC 5 3 RC 4 3 K ( pqp) + ( ) RRCC p 4 5 3 FIGURE. Highpass Biquad To achieve low sensitivities, use this design algorithm:. Partition the gain for good Q p sensitivity and dynamic range performance: Use a low noise amplifier before this biquad if you need a large gain Select K with this empirical formula:, 0. Qp. K. Qp 0.9 Q 0.,. < Q p < 5 p + 079630 These values also reduce the op amp bandwidth s impact on the filter response. This biquad s sensitivities are too high when Q p 5. Select an op amp with adequate bandwidth (f 3dB ) and slew rate (SR): f 3dB f H f 3dB 0f c SR > 5f H V peak where f H is the highest signal frequency, f c is the corner frequency of the filter, and V peak is the largest peak voltage. Make sure the op amp is stable at a gain of A v K. 3. For current-feedback op amps, use the recommended value of R f for a gain of A V K. For voltage-feedback op amps, select R f for noise and distortion performance. Then set R g for the correct gain: Rg Rf K 4. Initialize the resistance level. R R 4 R 5 Increasing R will: Increase the output noise Reduce the distortion Improve the isolation between the op amp outputs and C and C 3 Make the parasitic capacitances a larger fraction of C and C 3 5. Initialize the capacitance level, and the component ratios C c 3 C and r 3 R5 R : 4 c ( pr) c 0.0 + + 4Q c K p ( + ) r max 0.0, Qp ( + c ) c 6. Recalculate C and initialize the capacitors: rq p c + + 4Qp K r C C c C3 cc 7. Set C and C 3 to the nearest standard values. www.national.com

KRC Highpass Biquad Design (Continued) 8. Recalculate C, C, R and r : C CC3 C c 3 C R pc 4Q c K p + + + r Qp ( + c ) c 9. Calculate the resistors: R R4 r R5 rr The component sensitivity formulas are in the table below. The sensitivities formulas are in the table below. The sensitivities to α i K are a measure of this biquad s sensitivity to the op amp group delay [5]. To evaluate this biquad is sensitivity performance, use the method in [6]. H Q p αi Sα Sα Sα i i C 0 Q r p c C3 0 Q r p c R4 0 K Q c ( ) p + r R5 0 K Q c ( ) p + r K Rf 0 c ( K ) Qp K r Rf K K 0 ( K ) Q c p r K 0 K Q c p r KRC Highpass Biquad Parasitic Compensation To pre-distort this biquad, and compensate for the [parasitic] non-inverting input capacitance of the op amp (C ni ), do the following (see Appendix A for the derivation of the formulas):. Start the iterations by ignoring the parasitics: τ 0 τ 4 0 p. Estimate the pre-distorted values of p and Q p ( p(pd) and Q p(pd) that will compensate for τ oa and C ni : p(pd) p(nom) τ4 p(nom) Qp(pd) Qp(nom) p(pd) Qp(nom) τp(pd) p(nom) Where p(nom) and Q p(nom) are the nominal values of p and Q p 3. Recalculate the resistors and capacitors using p(pd) and Q p(pd) : RRCC 4 5 3 p(pd) RC 5 RC 5 3 RC 4 3 ( K ) p(pd) Qp(pd) + The Design Example accomplishes this by recalculating R and r, then R 4 and R 5 : R p(pd) C + + 4Q c K p(pd) + r Qp(pd) ( + c ) c R4 R r R5 rr 4. Calculate the resulting parasitic correction factors: τ R 4 C ni τ 4 Kτ oa R 4 C 3 +R 4 R 5 (C +C 3 )C ni 5. Calculate the resulting filter response parameters p and Q p p p(pd) + τ4 p(pd) Qp(pd) Qp p + Qp(pd) τp p(pd) 6. Repeat steps -5 until: p p(nom) Q p Q p(nom) OA-9 3 www.national.com

OA-9 KRC Highpass Biquad Parasitic Compensation (Continued) 7. Estimate the high frequency gain: H K + τ4p(pd) If this reduces the gain too much, then repartition the gain Design Example The circuit shown in Figure is a 3rd-order Butterworth highpass filter. Section A is a buffered single pole section, and Section B is a highpass biquad. Use a voltage source with low output impedance, such as the CLC buffer, for V in : The nominal filter specifications are: f c 50MHz (passband edge frequency) f s 0MHz (stopband edge frequency) f H 00MHz (highest signal frequency) A p 3.0dB (maximum passband ripple) A s 40dB (minimum stopband attenuation) H 0dB (passband voltage gain) FIGURE. Highpass Filter 07968 The 3rd-order Butterworth filter [-4] meets our specifications. The pole frequencies and quality factors are: Section A B p /π [MHz] 50.00 50.00 Q p [ ].000 Overall Design. Restrict the resistor and capacitor ratios to:. 0. c,r 0 3. Use % resistors (chip metal film, 06 SMD) 4. Use 5% capacitors (ceramic chip, 06 SMD) 5. Use standard resistor and capacitor values Section A Design and Pre-distortion:. Use the CLC. This is a close-loop buffer. f 3dB 800MHz > f H 00MHz f 3dB 800MHz > 0f c 500MHz SR 3500V/µs, while a 00MHz, V pp sinusoid requires more than 00V/µs τ oa 0.8ns at 0MHz C ni().3pf (input capacitance). Select R A for noise, distortion and to properly isolate the CLC s output and C A. The pre-distorted value of R A, that also compensates for C ni(), is [5]: RA p τ oa CA + Cni() The results are in the table below: The Initial Value column shows ideal values that ignore any parasitic effect The Adjusted Value column shows the component values that compensate for C ni() and CLC is group delay (τ oa ) The Standard Value column shows the nearest standard % resistors and 5% capacitors Component Initial Value Standard Adjusted C A 30pF 30pF 30pF R A 06Ω 9.8Ω 93.Ω C ni().3pf.3pf Section B Design:. Since Q p.000, set K B to.00. Use the CLC446. This is a current-feedback op amp f 3dB 400MHz > f H 00MHz f 3dB < 0f c 500MHz; the design will be sensitive to the op amp group delay SR 000V/µs > 000V/µs (see Item # in Section A Design ) τ oa 0.56ns at 0MHz C ni(446).0pf (input capacitance) 3. Use the CLC446 s recommended R f at A v.0: R fb 453Ω Then leave R gb open so that K B.00 4. Initialize the resistor level: R 00Ω 5. Initialize the capacitor level, and the component ratios: C 3.83pF π( 50.00MHz) ( 00Ω) c 0.000 r max 0.0,0.086 0.000 { } 6. Recalculate C and initialize the capacitors: C 0.7 C B 89.3pF C 3B.3pF 7. Set the capacitors to the nearest standard values: C B 9pF C 3B pf 8. Recalculate the capacitor level and ratio, and the resistor level and ratio: www.national.com 4

Design Example (Continued) 9. Calculate the resistors: R 4B 34Ω R 3B 3.Ω 0. The sensitivities for this design are: αi C ( 9pF) ( pf) 3.64pF pf c 0.09 ( 9pF) R π ( 50.00MHz) ( 3.64pF) 00.6Ω r 0.056 C B 0.00 0.50 0.39 C 3B 0.00 0.50 0.39 R 4B 0.00 0.50 0.50 R 5B 0.00 0.50 0.50 R fb 0.00 0.00 0.00 R gb 0.00 0.00 0.00 K.00 0.00. Section B Pre-distortion:. The design gives these values: p(nom) π(50.00mhz) Q p(nom).000 K B.00 C B 9pF C 3B pf. Iteration shows the initial design results. Iterations -4 pre-distort R 4B and R 5B to compensate for the CLC446 s group delay, and for C ni(446) : Iteration # 3 4 [MHz] p(pd) 50.00 59.73 56.8 57.54 π Q p(pd) [ ].000 0.930 0.956 0.9505 R [Ω ] 0.6 84. 88.54 87.4 r [Ω ] 0.096 0.08 0.053 0.065 R 4B [Ω ] 34.3 53.0 7.9 67.9 R 5B [Ω ] 3. 8.03 8.73 8.53 τ [ns] 0.34 0.53 0.73 0.68 τ 4 [ns].74.5.575.559 Iteration # 3 4 [MHz] p 43.87 5.96 49.5 50.3 π Q p [ ].034 0.984.003 0.999 The midband gain estimate is: H 0.770[/V/V]. Iteration 0.759 [V/V]. Iteration 4 The simulations gave a lower value for H. Increasing K could help overcome this loss, but would also increase the sensitivities. 3. The resulting components are: Component Initial Value Standard Adjusted C B 9pF 9pF 9pF C 3B pf pf pf C ni(446).0pf.0pf R 4B 34Ω 68Ω 67Ω R 5B 3.Ω 8.5Ω 8.7Ω R fb 453Ω 453Ω 453Ω R gb Figure 3 and Figure 4 show simulated gains. The curve numbers are:. Ideal (Initial Design Values, τ oa 0,C ni 0). Without pre-distortion (Initial Design Values, τ oa 0, C ni 0) 3. With pre-distortion (Pre-distorted Values, τ oa 0, C ni 0) 07964 FIGURE 3. Simulated Filter Magnitude Response OA-9 5 www.national.com

OA-9 Design Example (Continued) SPICE Models SPICE Models are available for most of Comlinear s amplifiers. These models support nominal DC, AC, AC noise and transient simulations at room temperature. We recommend simulating with Comlinear s SPICE model to: Predict the op amp s influence on filter response Support quicker design cycles Include board and component parasitic models to obtain a more accurate prediction of the filter s response. To verify your simulations, we recommend bread-boarding your circuit. Summary 07965 FIGURE 4. Simulated Filter Magnitude Response This application Note contains an easy to use design algorithm for a low sensitivities Sallen-Key highpass biquad. Designing for low p and Q p sensitivities gives: Reduced filter variation over process, temperature and time High manufacturing yield Lower component cost A low sensitivity design is not enough to produce high manufacturing yields. This Application Note shows how to compensate for the op amp bandwidth, and for the [parasitic] input capacitance of the op amp. This method also applies to any other component or board parasitics. The components must also have low enough tolerance and temperature coefficients. Appendix A Derivation of Pre-distortion and Parasitic Capacitance Compensation Formulas To pre-distort this filter, and compensate for the [parasitic] input capacitance of the op amp C ni ):. Use the method in [5] to include the op amp s effect on the filter response. The result is: H s Vo p τ e Vin s s + + pq p p where the op amp group delay (τ oa ) is evaluated at the passband edge frequency (f c ), and: oa s RC 5 RC 5 3 RC 4 3 K ( pqp) + ( ) RRCC K RC p 4 5 3 + τoa 4 3 K + R f Rg H K www.national.com 6

Appendix A Derivation of Pre-distortion and Parasitic Capacitance Compensation Formulas (Continued). Since C ni is in parallel with R 4, replace R 4 with the parallel equivalent of R 4 and C ni : R4 R4 + R4Cnis H R 4 C 3 R 5 C + K τoa τ oas s e V + R C s o 4 ni Vin R4C3( K) + + R5( C+ C3) s + R4Cnis R4C3( R5C+ Ktoa ) + + R4Cnis s 3. After simplifying, we obtain: H s V p o τ oas e Vin s s + + ( pqp) p where : t t ( pqp) + τ RC 5 + RC 5 3 RC 4 3( K ) τ R4Cni p τ3 + τ 4 τ3 R4RCC 5 3 τ4 KτoaR4C3 + R4R5( C+ C3) Cni K + R f Rg H K ( τ3) ( τ3 + τ4) Appendix B Bibliography. R. Schaumann, M Ghausi and K. Laker, Design of Analog Filters: Passive, Active RD, and Switched Capacitor. New Jersey: Prentice Hall, 990.. A. Zverev, Handbook of FILTER SYNTHESIS. John Wiley & Sons, 967. 3. A. Williams and F. Taylor, Electronic Filter Design Handbook. McGraw Hill, 995. 4. S. Natarajan, Theory and Design of Linear Active Networks. Macmillan, 987. 5. K Blake, Component Pre-distortion for Sallen-Key Filters, Comlinear Application Note, OA-, Rev. B, July 996. 6. K. Blake, Low-Sensitivity, Lowpass Filter Design, Comlinear Application Note, OA-7, July 996. 7. K. Blake, Low-Sensitivity, Bandpass Filter Design With Tuning Method, Comlinear Application Note, OA-8, Oct. 996 Note: The circuits included in this application note have been tested with parts that may have been obsoleted and/or replaced with newer products. Please refer to the CLC to LMH conversion table to find the appropriate replacement part for the obsolete device. OA-9 7 www.national.com

OA-9 Low-Sensitivity, Highpass Filter Design with Parasitic Compensation LIFE SUPPORT POLICY Notes NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Corporation Americas Email: support@nsc.com www.national.com Europe Fax: +49 (0) 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 608 English Tel: +44 (0) 870 4 0 7 Français Tel: +33 (0) 4 9 8790. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Asia Pacific Customer Response Group Tel: 65-544466 Fax: 65-504466 Email: ap.support@nsc.com Japan Ltd. Tel: 8-3-5639-7560 Fax: 8-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.