Model : LII0 P P/N:L00- P P/N:L00- Intel Merom PU + M + IH-M hipset LII0 M/ and aughter P/N LIT: LII0 M/ ffiliated FF/able P/N LIT: P0 INEX P0 YTEM LOK IRM P0 POWER IRM & EQUENE P0 PIO & POWER ONUMPTION P0 PU Merom-/ P0 PU Merom-/ P0 LOK EN I LPR P0 N HOT -/ P0 N V_PIEXPR-/ P0 N R_MEM YTEM-/ P N POWER-/ P N _NTF-/ P R OIMM P Terminatation / MP-II P L&-VIO&RT&WEM&LUET P IH-PU/TT/IE -/ P IH-IO/PIO/U/Y -/ P IH-POWER -/ P Mini card/o/t on/fn P0 L ard Reader P /EU/NEW ard /U on P UIO/LE/W /TP ON/IO P 0_00M LN RTL0E P E-ITE P YTEM POWER (MX) P.V/.0V/0.V_R P FX ORE ( OZ) P PU ORE(IL) P +.V(OZ) P0 TT IN / harger P V W / W P ppendix. Ver. History L00- L00-0L00-0 L00-0 0L000-0 L000-0 0L000-0 L000-0 0L000-0 L000-0 0PL000-0 PL000-0 0JL00-0 JL00-0 0YL0-0 YL0-0 P TK UP LYER:TOP LYER:N LYER:IN LYER:IN LYER:N LYER:IN LYER:V LYER:OT MIN OR Y LII0 REV. P MIN FOR LII0 REV: UIO Y FOR L0II REV: P UIO FOR L0II0 REV: TOUHP FOR LI0 REV: P TOUHP FOR LI0 REV: MOEM FOR LI0 REV: P MOEM FOR LI0 REV: WITH FOR LI0 REV: P WITH FOR LI0 REV: O FOR LI0 REV: P O FOR LIO REV: FOR L0I0 REV:0 P FOR L0IO REV:0 IR FOR L0IIX REV: P IR FOR LIIX VER: 0L00-0 0L000-0 0L000-0 st nd rd st nd 0PL000-0 0JL00-0 0YL0-0 WEM st nd rd st nd rd st nd rd st nd rd st nd rd st st LUETOOTH st UIO Y FOR L0II REV: L00-00 L00-0 L00-0 L000-00 L00-00 TOUHP FOR LI0 R: L000-00 L000-0 L000-0 L00-00 L00-0 L00-0 MOEM FOR LI0 R: L00-00 L00-0 L00-0 L00-00 L00-0 L00-0 FF UIO L0 H FF UIO L0 JH FF UIO L0 HF LE PK OHM N0E L0 F LE PK H O.W M.. FF T M L0 H FF T M L0 JH FF T M L0 HF FF TP T L0 H FF TP T L0 JH FF TP T L0 HF LE M L0 HL LE M L0 MI LE M L0 FV WITH Y LI0 VER. FOR L0I0 REV:0 L0-0 IR Y LII0 VER. L0-0 FF WITH L0 H FF WITH L0 JH FF WITH L0 HF LE FOR HL LI/RI To Mother board To udio board To Mother board To Mouse board To Mother board To Mother board To Mother board To Mother board To Mother board To Mother board E OMPUTER ORP. INEX ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
LIIX YTEM LOK IRM RYTL.MHz PU Merom ocket, THERML M0 E MPLIFIER MP0 INTERL PK.W x RYTL MHz lock en I LPR UIO OE L HP JK(PIF)* L Extended ZLI 0 R REER MM//M/M-PRO 0 M RJ OIMM R RM U /MHZ +.V +.V." T H FLH ROM OIMM0 MLL OR UIO/LE OR U x U ONN x T x W/ PI U INT K/ INTEL IH-M E K/ ONTROLLER T/P F U /00 MHZ North ridge INTEL restline MI outh ridge RT RYTL.K ITE,,0,,,, LP U FN U x 0 PIE x IE PIE x PIE x PIE x U ONN x ebug ONN RYTL.K HRER None use -ROM RTL0E NEW R U x IR TTERY TVout LV TM&RT UX uletooth 0 0 Mini ard -Video L RT RJ RYTL M HZ Mini ard U x module WE M U x U x Mus iagram _M_T _M_LK outh R IMM ridge,, Mini ard TTERY 0 Thermal ensor for PU E_T_THM E_LK_THM E M_T_E_EN lock en M_LK_E_EN E OMPUTER ORP. YTEM LOK IRM ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
POWER LOK IRM VI0 VI VI VI VI VI VI IL RQW00N0 & RQW0N0 +PU_ORE/ +.V +.V PL EU +.V/ +0.V/ VI0 VI VI VI OZ O FX_ORE/ ignal tate 0(FULL ON)/M0 (uspend to RM)/M (uspend to IK)/M (oft OFF)/M +*V ON ON ON ON +*V +*V LOKs ON ON ON ON OFF ON ON OFF ON ON OFF ON VI +V//PK 0 O PL O +V/ O +V/. MX IL O O +.V//PK O O +.V/ +.V/ +.V/ -JK HRER TL Power PWM I Power W Mosfet Power Regulator Power Input 0 0 VP VP +PU_ORE PWM IL +PU_ORE / P_IN FX_ORE PWM IL FX_ORE/ FX_VR_EN ll_ux PWM MX +.V/ +V //PK0 +V/0. follow up +.V +.V +V +V +V +.V/ MOFET W +.V_ON +.V/ MOFET W +.V_ON +V/. MOFET W +V_ON +V MOFET W +V_ON +V MOFET W +.V +.V/0. LO +.V /0. follow +.V up O +.0V/ TTERY 0 VT +.V/+.0V PWM IL +.V /,+.0V/ +.V_ON/+.0V_ON +.V +.V_ON.V//PK 0 +.V_R PWM OZ +.V//PK0 R_V_W# +.V LO PL +.V / +.V_ON O +0.V LO EUP +0.V/ follow +.V up OZ E OMPUTER ORP. POWER IRM ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO( ~ ) IH-M PIO PM_M_UY# E_EXTMI# INT_PIRQE# INT_PIRQF# INT_PIRQ# INT_PIRQH# IO_RE N T_ON WOL_EN Pull low 00k Pull high.k M_LERT# LN_PHYP N Pull high.k PM_TPPI# PM_PRLPVR N PIO TP PIO0 T0P N N. R_V_ET PM_TPPU# PM_LP TTE# N.(QRT_TTE0) N.(QRT_TTE) U_O# U_O# U_O# PM_LKRUN# H_OK_EN# N. LK_T_OE# TP TP O_ET IH_PIO U_O# U_O# U_O# U_O# MF_MOE H_PWR PI_REQ# PI_NT# PI_REQ# PI_NT# PI_REQ# PI_NT# N ITEE PIO Pin efinition list P0 TL_EEP P RF_OFF# P E_VI P E_VI P E_VI P E_VI P MP_00MV_EN# P MP_0MV_EN# P0 LE_PWR P +.V_ON P LE_RF P M_LK_T P M_T_T P H_0TE P H_RIN# P MUTE_MP# P0 IR_RX P M_LK_E_EN P M_T_E_EN P MP_EN# P PWR_KEEP P E_KIP P -PWRTN# P R_V_W# P0 _IN P H_PROHOT_E# P PLT_RT# P EI# P _ON P E_PF P FN_PEE# P RF_W_ON# PE0 PM_RMRT# PE PM_PWROK_ PE P_IN PE INTERNET# PE PWR_W PE HR_R PE HR_ PE NEWR_PWRON PF0 ILENT_ON# PF LE_P PF LE_NUM PF ILENT_LE PF P_LK_TP PF P_T_TP PF NEWR_PERT# PF NEWR_PPE# PH0 +PU_ORE_ON PH +.0V_ON PH +.V_ON PH +.V_ON PH +V_ON PH +.V_ON PH +.V_ON P +V_ON 0/PI0 TT_TEMP /PI PTOR_I /PI T_I /PI T_V /PI PM_LP_# /PI PM_LP_# /PI E_PU_00MHz /PI WEM_W ITEE PIO Pin efinition list 0/PJ0 RIHTNE 0/PJ H_I 0/PJ FN_TRL0 0/PJ H_ON 0/PJ ENT_V 0/PJ H_V K Matrlk interface KI0/T# K_IN0 KI/F# K_IN KI0/T# K_IN KILIN# K_IN KI K_IN KI K_IN KI K_IN KI K_IN KO0/P0 K_OUT0 KO/P K_OUT KO/P K_OUT KO/P K_OUT KO/P K_OUT KO/P K_OUT KO/P K_OUT KO/P K_OUT KO/K# K_OUT KO/UY K_OUT KO0/PE K_OUT0 KO/ERR# K_OUT KO/LT K_OUT KO K_OUT KO K_OUT KO K_OUT ITEE PI Flash ROM interface FLFRME#/P FLFRME# FL0/E# PI_E# FL/ FL/ PI_IN PI_OUT FL/P N. FLLK/K PI_LK FLRT#/WU /P0/TM N. ystem & LP us L0 LP_0 L LP_ L LP_ L LP_ ERIRQ INT_ERIRQ LFRME# LPLK LP_FRME# LK_PI_LP WRT# LRT# ITEE lock KK EKI KKE EKO VTY0 VTY VTY VTY VTY VTY VT V V ITEE ITEE ITEE Power +.V +.V +.V +.V +.V +.V +.V +.V +.V ITEE N E-- 0 N N N N N N N -M PIO PIO0 MH_EL0 PIO MH_EL PIO MH_EL PIO N. PIO N. PIO F(MIx selction) PIO N. PIO N. PIO N. PIO F(PIe Lane) PIO0 N. PIO N. PIO F(XOR / LLZ / lock Un-gating) PIO F(XOR / LLZ / lock Un-gating) PIO N. PIO N. PIO F(F ynamic OT) PIO N. PIO F(NP design) PIO F(MI lane Reversal) PIO0 F0 (VO/PIE oncurrent Operation). F_0 ~ F_ Host clock frequency initial F0 F F Host lock Frequency 0 0 00 0. F MIx selection MIx selction Low = MI* F High = MI* (default). F_ PIe Lane PIe Lane F INT-PIRQ# :N INT-PIRQ# :N INT-PIRQ# :N INT-PIRQ# :N PI_REQ#0 : N PI_REQ# N PI_REQ# N PI_REQ# : N PI_NT#0 N PI_NT# N PI_NT# : N PI_NT# N Low = Reverse Lane (default) High = Normal F[:] have internal pullup ressistors.. F_ ~ F_ XOR / LLZ / lock Un-gating F F onfiguration 0 0 lock ating isabled 0 XOR Mode Enabled 0 ll-z Mode Enabled. F_ F ynamic OT F ynamic OT Normal Operation (efault) Low = ynamic OT isabled F High = ynamic OT Enabled(default). F_ NP design F (V elect) NP design Low =.0V High =.V. F_ MI lane Reversal MI lane Reversal F 0 = normal (default) = Reversed. F_0 VO/PIE oncurrent operation F0 (VO/PIE oncurrent Operation) 0 = Only VO or PIE x is operational (default) = VO and PIE x are operating simultaneously via the PE port V +.V +.V +.V +.V +.0V +0.V FX_ORE V +V +V +.V +.V +.V +.V +.0V V +.V V +.V V +.V V +V V +.V +.V +.V restline I(m) W 0. 00. 0 0. 0.0 0. 0 0. 00.0 I(m) mw 0 0 0 0 00 00.. I(m) 00 I(m) 0 I 0u I(m) 0 I(m) Merom PU PU ORE(V) I() W TEMP( ) IMVP-+..0. IH-M ITEE W LOK ENERTOR mw M0 L mw 0. mw RTL0E mw... TEMP( ) 0 TEMP( ) 0 TEMP( ) 0 TEMP( ) 0 TEMP( ) 0 TEMP( ) 0 TEMP( ) 0 E OMPUTER ORP. PIO & POWER ONU ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
H_#[:] H_T#0 H_REQ#[:0] H_#[:] H_T# H_0M# H_FERR# H_INNE# H_TPLK# H_INTR H_NMI H_MI# R H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# Z00 J L L K M N J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V M N T V F U []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# T[0]# R ROUP 0 REQ[0]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# T[]# R ROUP 0M# FERR# INNE# TPLK# LINT0 LINT MI# RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] IH REERVE XP/ITP INL ONTROL THERML H LK # NR# PRI# EFER# RY# Y# R0# IERR# INIT# LOK# REET# R[0]# R[]# R[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TM TRT# R# PROHOT# THERM THERM THERMTRIP# LK[0] LK[] H E H F E F 0 H F F E 0 H_IERR# H_PURT# H_R#0 H_R# H_R# PREQ# TK TI TO TM TRT# R# H_PROHOT# H_THERM H_THERM PM_THRMTRIP# H_# H_NR# H_PRI# H_EFER# H_RY# H_Y# H_REQ#0 H_INIT# H_LOK# H_PURT# H_TRY# H_HIT# H_HITM# *K R *._ R H_R#[:0] +.0V +.V PM_THRMTRIP#,, LK_PU_LK LK_PU_LK# H_R#[:0] +.0V R 0K T M-OTE +.V R 0K H_PROHOT_E# H_TLREF place within 0.'' +.0V R K_ R K_ H_#[:0] H_TN#0 H_TP#0 H_INV#0 H_#[:0] PU_EL0 H_TN# H_TP# H_INV# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TLREF R *K TET R *K TET *0.u/0V/XR TET PU_EL0 PU_EL PU_EL E F E F E E K J J H F K H J H H N K P R L M L M P P P T R L T N L M N F F U [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# TN[0]# TP[0]# INV[0]# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# TN[]# TP[]# INV[]# TLREF TET TET TET TET TET TET EL[0] EL[] EL[] T RP T RP 0 MI T RP T RP Merom all-out Rev a []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# TN[]# TP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# TN[]# TP[]# INV[]# OMP[0] OMP[] OMP[] OMP[] PRTP# PLP# PWR# PWROO LP# PI# Y H_# H_# V H_# V H_# V H_# T H_# U H_# U H_# Y H_#0 W H_# Y H_# W H_# W H_# H_# H_# H_# Y U E H_# H_# H_#0 H_# H_# H_# 0 H_# E H_# F H_# H_# E H_# H_# H_#0 H_# F H_# H_# E F 0 R OMP0 U OMP OMP Y OMP E E R0 R0 R R H_#[:0] H_TN# H_TP# H_INV# H_#[:0] H_TN# H_TP# H_INV#._._._._ H_PRTP#,, H_PLP# H_PWR# H_PWR H_PULP# H_PI# OMP0/ TRE. OHM +-% OMP/ TRE OHM +-% within 0.'' Merom all-out Rev a +.0V lose to N PU_EL0 R R *K_ R K_ MH_EL0 LK_EL0 EL EL EL0 MHZ P00 0 0 00 P 0 P If used, pull-up change from R to R(Intel recommend) lose PU H_IERR# R H_TPLK# R *0_ TO R * +.0V R TM R _ K_ TI H_PURT# R _ 0-0-00 modify R._ H_FERR# R +.0V PU Thermal ensor R K_ +.0V TRT# TK R _ R0 _ +.V R 00_ Z00 0.u/.V/XR_00 +.V R 0K M-00 U H_THERM + V Z00 THERM# 000p H_THERM - N T LK LERT Z00 E_T_THM E_LK_THM R * PM_THRM#, PU_ELR R R *K_ K_ MH_EL LK_EL PM_THRMTRIP# R K modify R 00K Z00 E Z00 Q N0 0.u/0V/XR_00 M-00 00 u/0v_00 M-00 E Q N0 UX_OFF#, 0-0-00 modify M0 +.0V R K_ PU_ELR0 R K_ MH_EL LK_EL R *K_ E OMPUTER ORP. PU Merom-/ ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
lose to Pin QT0RL00 = 00m QT0RL0 = 00m QT0RL00 = 00 m QT0RL00 = 00m QT0RL00 = 00m I=000m I=00m I=0m Modify / LIIX PU Merom-/ E OMPUTER ORP. ustom Tuesday, February, 00 ize ocument Number Rev ate: heet of PU_V Z00 VORE_VENE VORE_ENE Z00 +PU_ORE +.0V +PU_ORE +PU_ORE +.V +.0V +PU_ORE.u/0V/XR_00 M-00.u/0V/XR_00 M-00 0 0.0u/V/XR.u/0V/XR_00 M-00.u/0V/XR_00 M-00.u/0V/XR_00 M-00 0.u/V/XR XR u/0v_00 M-00 0.u/V/XR 0.u/0V/XR_00 M-00.u/0V/XR_00 M-00 0 0.u/V/XR XR 0.u/V/XR XR R *00_ u/0v_00 M-00 0 u/0v_00 M-00 u/0v_00 M-00 0.u/V/XR XR u/0v_00 M-00 0 000p R0 000p 000p 0.u/V/XR u/0v_00 M-00 0.u/V/XR u/0v_00 M-00 0 000p 0 000p 000p 0 000p 000p U Merom all-out Rev a. 0 0 0 0 0 0 E E E0 E E E E E E0 F F F0 F F F F F F0 0 0 0 0 0 0 E E0 E E E E E E0 F F0 F F F F F F0 J K M J K M N N R R T T V W F F E F E F E E V V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[] VP[] VP[] VP[] VP[] VP[] VENE VI[0] VI[] VI[] VI[] VI[] VI[] VI[] ENE V[0] VP[0] VP[0] 0.u/0V/XR u/0v_00 M-00 u/0v_00 M-00 0.u/V/XR.u/0V/XR_00 M-00.u/0V/XR_00 M-00 u/0v_00 M-00 0 u/0v_00 M-00 0.u/V/XR 0.u/0V/XR u/0v_00 M-00 L _00 u/0v_00 M-00 U Merom all-out Rev a. P E F E E E E E E E E E F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P F F F F F F F E E E P P R R R R T T T T U U U U V V V V W W W W Y Y Y E E Y E E E F [0] [] [00] [00] [00] [00] [00] [00] [00] [00] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [] [] [0] [] [] [] [] [] [] [] [] [] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] [0] [00] [] [0] [] [] u/0v_00 M-00.u/0V/XR_00 M-00 u/0v_00 M-00 u/0v_00 M-00.u/0V/XR_00 M-00 u/0v_00 M-00.u/0V/XR_00 M-00 u/0v_00 M-00 0.u/0V/XR u/0v_00 M-00 000p 000p.u/0V/XR_00 M-00.u/0V/XR_00 M-00 R.u/0V/XR_00 M-00 0.u/0V/XR 0.u/V/XR.u/0V/XR_00 M-00 u/0v_00 M-00.u/0V/XR_00 M-00 R *00_ H_VI H_VI H_VI0 H_VI H_VI H_VI H_VI VORE_ENE VORE_VENE
+.V +.0V +.V LK_V_IO 0 0.u/V/XR 0 0.u/V/XR 0 *0.u/V/XR L QT0RL00_00 LK_V_IO L *QT0RL00_00 +.V R R 0K R0 *0K R 0K 0K PI0/LKREQ# PI/LKREQ# R/LKREQ_H R#/LKREQ_ Reserved FOR EMI I=0m *.u/0v/xr_00 M-00 L QT0RL00_00 *0.u/V/XR LK_V.u/0V/XR_00 0.u/V/XR M-00 LK_ebug 0 0.u/V/XR 0 0.u/V/XR LK_T_OE# MH_LK_REQ# PI_LK LK_PI_LP 0 R -PI_LK LK_R_M LK_M_ebug LK_U LK_IH 0.u/V/XR 0 0.u/0V/XR LK_V R * R R R R R0 * R * R R 0.u/0V/XR XTL_OUT XTL_IN PI0/LKREQ# PI/LKREQ# PI PI PI/LK_EL PIF/ITP_EN LKEL0 LKEL LKEL 0 0 U V_PI V_ V_PLL V_R V_PU V_REF K0 V_I/O V_PLL_I/O V_R_I/O_ V_R_I/O_ V_R_I/O_ V_PU_I/O PU_TOP# PI_TOP# KPWR/P# XTL_OUT PU_0 XTL_IN PU_0# PI_0/LKREQ_# PU MH PI_/LKREQ_# PU MH# PI_/TME R_/PU_ITP PI_ R_#/PU_ITP# ^PI_/LLK_EL PIF_/ITP_EN N U_MHz/F_ F_/TET_MOE LLK/M LLK#/M_ REF/F_/TET_EL 0 0 I=0m TPPU# TPPI# Z00 PU0 PU0# PU PU# Z00 Z00 LK LK# 0.u/V/XR R0 R0 R R R00 R0 R R R R 0.u/V/XR 0 *.u/0v/xr_00 M-00 0.u/V/XR PM_TPPU# PM_TPPI# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PIE_LN LK_PIE_LN# L_K L_K#.u/0V/XR_00 M-00 +.V R0 *0K R *0.u/V/XR *0.u/V/XR LK_PWR *0p LK_MH_LK R R0 R R OT_ R0 R0# R_0/OT_ R_/TT R# R OT_# *0p LK_MH_LK# R_0#/OT_# R_#/T LKEN_LK R_/LKREQ_# *0p LK LKEN_T L R_#/LKREQ_# R R R_ R# R *0p LK# R_# R R0 R_ 0 R# R0 *0p LK_MI_IH R_# R/LKREQ_F R0 R_/LKREQ_F# *0p LK_MI_IH# _PI R_#/LKREQ_E# 0 R R _ R_ R# R *0p LK_U *0p *0p _I/O R_# R R0 EL EL EL0 PU PI PI-E _PLL R_0 R# R0 *0p LK_IH NPO NPO _R_ R_0# R/LKREQ_H R FL FL FL MHZ MHZ MHZ _R_ R_/LKREQ_H# R#/LKREQ_ R *0p LK_PI_LP _R_ R_#/LKREQ_# _PU P00 0 0 00 0 *0p LK_ebug _REF 00 P 0 0 *0p -PI_LK LPR IH_T_LK IH_T_LK# LK LK# LK_MI_IH LK_MI_IH# LN_LKREQ# LK_PIE_NEW_R LK_PIE_NEW_R# LK_PIE_MINI_R LK_PIE_MINI_R# MINI ard_lk_req# New ard_lk_req# Note : liego LPT is Pin to Pin with I LPR O/P From LK REQ R0 OT R MH_LK Y.MHz_IP XTL_OUT XTL_IN e = *L - ( s + i ) L = rystal Load ap = 0P R R R R IH_T ontrol. NO UE MH_LK MI_IH E Mus M_T_E_EN M_LK_E_EN R R R0 i = I internal ap = P s = P R ontrol E.F,, _M_T R0 * LKEN_T *0M p p e = rystal external ap = P R R R0 LN NEWR MINIR F H,, _M_LK R * LKEN_LK 0-0-00 modify R ontrol.h 0-0-00 modify LK_EL R 0K LKEL LK_EL R LKEL +.V R *0K pin pull down=pin/ 為 R 輸出. pin pull up= pin/ 為 ITP 輸出. +.V R *0K 0 = LLK & OT_ for internal graphic controller support = M & M_ & R_0 for external graphic controller support +.V *R0 0K 0 = Overclocking of PU and R llowed = Overclocking of PU and R NOT allowed R.K LKEL0 LK_EL0 sel [0,] Vil = 0. Vih = 0. PIF/ITP_EN PI/LK_EL PI R 0K R 0K R 0K E OMPUTER ORP. Reserved for ILPR LOK EN I LPR ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
F I/O slew rate compensation Reference Voltage for ROMP 0mil/0mil losed to N within 00mil LIIX N_M-/ E OMPUTER ORP. ustom Tuesday, February, 00 ize ocument Number Rev ate: heet of H_WIN H_OMP H_OMP# H_ROMP H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_TP#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_ROMP H_# H_# H_TP# H_# H_# H_# H_# H_# H_# H_# H_#0 H_#0 H_# H_# H_#0 H_# H_# H_# H_#0 H_#0 H_WIN H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TP# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_TP# H_# H_# H_# H_OMP H_OMP# H_VREF H_PULP#_MH H_R#0 H_R# H_R# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_INV# H_INV# H_INV# H_INV#0 H_TN# H_TN#0 H_TN# H_TN# H_VREF +.0V +.0V +.0V +.0V R _ R._ 0.u/V/XR R UI restline 0 0 0 E0 E E F0 F F F 0 H H0 H H H J J J J J J J J J K0 K K K K K L M M M M M M N N N N N N P P P0 R R R R R R T0 T T T U U U U U U U V V W W W W W Y0 Y Y Y Y Y Y Y0 0 0 0 0 0 E E E E0 E E E F F F H H0 H H H J J J J J J K K K K W W W K K0 K K K L L L L L L 0 0 0 0 0 0 0 0 0 _00 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 0 0 0 0 0 0 _0 0 R0 K_ R K_ 0 0.u/V/XR R._ R 00_ R._ R HOT U restline J M F L K L J K P R H0 L M N J E E E M H H F N H M0 N N H P K M W0 Y V M J N N W W N Y Y P W N E Y E J H J E E H J H J E J J E J H H W E H 0 E F M 0 H K L E M K H L K J0 E 0 M E H E W N M K H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_WIN H_ROMP H_OMP H_PURT# H_PULP# H_VREF H_VREF H_# H_T#_0 H_T#_ H_NR# H_PRI# H_REQ#0 HPLL_LK H_Y# H_EFER# H_PWR# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#0 H_TN# H_TN# H_TN# H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_HIT# H_HITM# H_LOK# H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_R#_0 H_R#_ H_R#_ H_TRY# H_OMP# H_#_ H_#_ H_#_ H_#_ HPLL_LK# H_RY# H_LOK# H_#[:] H_HIT# H_#[:0] H_NR# H_T#0 H_TRY# H_HITM# LK_MH_LK H_PRI# H_T# H_EFER# LK_MH_LK# H_# H_REQ#0 H_Y# H_RY# H_PWR# H_TP#[:0] H_PULP# H_PURT# H_R#[:0] H_REQ#[:0] H_INV#[:0] H_TN#[:0]
U LK => PI-E & MI (00MHZ) REFLK => ispaly PLL ( nun- ss MHZ) REFLK => isplay LV PLL ( ss 00MHZ) Mount for UM +.V F0 0 F F 0 0 PM_M_UY#,, H_PRTP# PM_EXTT#0 R0 PM_EXTT#, ELY_VR_PWROO,,, PLT_RT#, PM_PRLPVR olse to N Host lock Frequency 00 ELY_VR_PWROO 0.u/V/XR MH_EL0 MH_EL MH_EL F F F F F F F F0 R0 PM_PRTP# PM_EXTT#0 PM_EXTT#-R ELY_VR_PWROO R00 00 RTIN# IH_THRMTRIP# P P R N R R M N J R M L M 0 H0 J0 K F H0 K J F H W0 K0 P N N F N J0 0 R L J E E0 K M0 M L N L L L J W V0 N0 J K K0 L0 L L L K J E 0 0 K RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_0 RV_ RV_ RV_ RV_ RV_0 RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_0 RV_ RV_ RV_ RV_ RV_ RV_0 RV_ RV_ RV_ RV_ RV_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 PM_M_UY# PM_PRTP# PM_EXT_T#_0 PM_EXT_T#_ PWROK RTIN# THRMTRIP# PRLPVR N N N N N N N N N N0 N N N N N N restline RV F PM N MI LK R MUXIN RPHI VI ME MI M_K_0 M_K_ M_K_ M_K_ M_K#_0 M_K#_ M_K#_ M_K#_ M_KE_0 M_KE_ M_KE_ M_KE_ M_#_0 M_#_ M_#_ M_#_ M_OT_0 M_OT_ M_OT_ M_OT_ M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VREF_0 M_VREF_ PLL_REF_LK PLL_REF_LK# PLL_REF_LK PLL_REF_LK# PE_LK PE_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ FX_VI_0 FX_VI_ FX_VI_ FX_VI_ FX_VR_EN L_LK L_T L_PWROK L_RT# L_VREF VO_TRL_LK VO_TRL_T LK_REQ# IH_YN# TET_ TET_ VOT has internal pull down 0= no VO device = VO device present V V W0 W W E Y 0 K E H J J E L K K L R W H H K K N J N N M J N N J J M0 M J J M M E E M K0 T N M0 H K 0 R M_ROMPP M_ROMPN M_ROMP_VOH M_ROMP_VOL M_VREF_MH L_VREF LK_REQ#_R Z00 R Z00 R0 OT_ OT_# L_K L_K# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP R0 0_ R0 0_ R OT_ OT_# L_K L_K# R * R * R * R * +.V LK LK# HH integrated graphics busy MI_TXN[:0] 0K M_K0 M_K M_K M_K M_K#0 M_K# M_K# M_K# M_KE0, M_KE, M_KE, M_KE, M_#0, M_#, M_#, M_#, M_OT0, M_OT, M_OT, M_OT, MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] +.V R 0K L_LK0 L_T0 L_PWROK L_RT# modify OT_ OT_# L_K L_K# modify 0- LK_REQ:sserted to control the raw PI-E clock MH_LK_REQ# MH_YN# VOLK has internal pull down. FX_V_VI0 FX_V_VI FX_V_VI FX_V_VI FX_VR_EN N_LEI_LK N_LEI_T R.K N_TV_ N_TV_ N_RT_HYN N_RT_VYN R R R.K R R Mount for UM N_LV_EN Mount 0 ohm % for UM 0 00 0 00 L_VREF 0 R 0.u/V/XR R Mount for UM R R N_LV_LKN N_LV_LKP N_LV_LKN N_LV_LKP N_L_EN N_LV_N0 N_LV_N N_LV_N N_LV_P0 N_LV_P N_LV_P N_LV_N0 N_LV_N N_LV_N N_LV_P0 N_LV_P N_LV_P R 0 N_RT_LK N_RT_T 0--00 modify Mount ohm % for UM Mount for UM +.V.K_ R K 00 Modify / R _ TP TP TP.K_ N_RT_ N_RT_ N_RT_R MH_RT_H Z0 MH_RT_V Z00 J0 H Z00 E Z00 E0 Z00 K0 LV_I L TP Z00 L N N0 E TP TP R TP TP E F Z00 0 E0 F Z00 E Z00 E Z0 Z0 K F J L Z0M Z0 P H K J F E K F E N_RT_LK N_RT_T U restline F0 ( IP ) => = Only VO or PI-E 0 = VO and PI-E F ( IPU ) => = Mobility PU 0 = Reverse +.V L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_LK# LV_LK LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ LV_T#_0 LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONEL0 TV_ONEL RT_LUE RT_LUE# RT_REEN RT_REEN# RT_RE RT_RE# RT LK RT T RT_HYN RT_TVO_IREF RT_VYN R *.K +.V R0 *.K LV TV V PI-EXPRE RPHI N_RT_ N_RT_ N_RT_R PE_OMPI PE_OMPO PE_RX#_0 PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_0 PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX_0 PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_0 PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_RX_ PE_TX#_0 PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_0 PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX#_ PE_TX_0 PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_0 PE_TX_ PE_TX_ PE_TX_ PE_TX_ PE_TX_ N M J L N T T0 U0 Y Y0 W 0 H J0 L0 M U T T W W 0 Y H H N U U N R0 T Y W W H E H M T T N0 R U W Y Y 0 E0 H PE_OMP R should be tied to N._ V_PE N_RT_ N_RT_ N_RT_R 0.0 M_VREF_MH - MOIFY M_VREF_MH TP MH_VERF-TP TP +.V R0 K_0. M_ROMP_VOH R0 0.0u/V/XR.u/.V/XR_00.0K_0. M-00 XR MH_RT_H MH_RT_V *p *p should be tied to N R R R *0_ *0_ *0_ Mount for UM 0-0-MOIFY *0p *0p *0p Modify /0 M_ROMP_VOL For MEN bus throttling Reserve for N THRMTRIP# ( O/ Vccp ) modify R * IH_THRMTRIP# PM_THRMTRIP#,, *T hecking 0.0u/V/XR.u/.V/XR_00 M-00 XR R K_0. +.V heck with /W R 0K PM_EXTT#-R R 0K PM_EXTT#0 R 0K LK_REQ#_R R N_L_EN *00K R N_LV_EN *00K E OMPUTER ORP. N N RLK_V_PIEXPR-/ ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
LIIX N R_MEM YTEM-/ E OMPUTER ORP. ustom 0 Tuesday, February, 00 ize ocument Number Rev ate: heet of M_Q M_Q M_Q M_Q M_0 M_Q M_0 M_Q0 M_Q M_Q0 M_Q M_Q M_Q M_ M_Q M_Q M_Q M_Q M_Q M_Q0 M_ M_Q M_Q M_ M_Q M_Q M_Q M_ M_Q M_Q#0 M_Q# M_Q# M_Q# M_Q# M_Q# M_Q# M_Q# M_ M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_M M_Q# M_0 M_M M_Q M_Q#0 M_ M_ M_ M_Q M_ M_Q# M_ M_Q0 M_Q M_0 M_Q# M_M0 M_ M_0 M_ M_Q M_M M_M M_Q# M_M M_Q M_ M_Q M_ M_Q# M_ M_M M_Q# M_ M_Q# M_Q M_M M_ M_ M_M M_M M_M M_M0 M_M M_M M_M M_M M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q0 M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_ Z00 Z00 M_ Z00 Z00 Z00 Z00 R TP0 R YTEM MEMORY UH restline P R W0 W N N0 V0 V 0 0 E0 Y F0 F J0 J J L K K K K J L J J K J0 L K K E K E J0 L K L K K0 J J F H K E J R T Y Y U T Y V Y W F E Y E T0 0 K K J L E V U0 0 L K K K F V E R0 K L H J F W E _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q 0 _R# _RVEN# _WE# _M_0 _M M M M M M M M M M_0 _M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# # _M_0 _M M M M M M M M_ UJ restline 0 E0 E E E E E F F F F0 F0 H H H H J J J J J J J J K K K L L L0 L L L L L M M M M M M0 M N N N N N N N N N N V W W W W W W Y Y Y Y Y Y Y0 Y P T T T R F F T V H0 P P P P P0 R T T T U U U0 V 00 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 0 0 0 _0 0 0 _0 00 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _ R TP R R YTEM MEMORY U restline R W Y R R T W F J 0 H E W E E0 F H 0 F0 R0 W0 T W W Y V T V T W V U T E0 0 Y 0 W Y T T Y R R R N M N0 T N M N K F E Y0 J 0 K H L K J J L E 0 J T E H P T H P L T W W Y N J _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q 0 _R# _RVENIN# _WE# _M_0 _M M M M M M M M M M_0 _M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# # _M_0 _M M M M M M M M_ R M_Q[:0] M_Q[:0] M_[:0], M_#, M_Q#[:0] M_[:0], M_Q[:0] M_Q#[:0] M_M[:0] M_[:0], M_[:0], M_M[:0] M_Q[:0] M_#, M_R#, M_WE#, M_R#, M_WE#,
Mount for UM hange 0.u/YV_00 For UM Mount for UM Mount for UM I=m I=00m Mount for UM I=0m I=0m Mount for UM I=00m I=00m Mount for UM I=m hange 0.u/YV_00 For UM losed to I I=00m hange 0.u/YV_00 For UM I=00m I=0m Mount for UM I=0m I=0m I=0m hange 0.u/YV_00 For UM losed to I I=0m I=0m I=m I=0m I=00m I=0m I=00m I=0m I=m I=0m I=0m I=0m I=0m I=00m I=0m I=00m I=00m I=00m 0/ modify hange 0.u/YV_00 For UM 0/0 modify - modify delete L 0-0-00 modify modify 0- modify 0- modify 0- LIIX N POWER-/ E OMPUTER ORP. ustom Tuesday, February, 00 ize ocument Number Rev ate: heet of V_HV V_Q V_TV MH_RT Z0 Z0 MH_V_HPLL V_TV MH_V_MPLL V_RXR_MI V_M_K V_MI MH_V_HPLL VTTLF VTTLF MH_VYN V_M_K V_X MH_V_MPLL MH_V_PLL V_HV V_LV VTTLF Z0 V_FX V_Q MH_V_PLL MH_V_PLL MH_V_PLL V_LV V_PE_ V_PE_PLL V_PE_PLL V_TV V_TV V_TV V_TV V_TV V_TV V_M_K V_VTT MH_RT_ +.V +.0V +.V +.V +.V +.V +.0V +.0V +.V +PU_ORE +.V +.V +.V +.0V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V V_PE 0.u/V/XR R *.u/0v/xr_00 M-00 *.u/0v/xr_00 M-00 0 *0.u/V/XR XR 0 0.u/V/XR 0 0.u/V/XR 0 0.u/V/XR.u/0V/XR_00 M-00 R _00 0 u/0v_00 M-00 00 n/v 0.u/V/XR R *0.u/0V/XR *T.u/0V/XR_00 M-00 L _00.u/0V/XR_00 M-00 n/v L _00 *0.u/V/XR R u/0v_00 M-00 L QT0RL00_00 L _00 0.u/V/XR 0.u/V/XR R L _00.u/0V/XR_00 M-00.u/0V/XR_00 M-00 R *0 *.u/0v/xr_00 M-00 0.u/V/XR R _00.u/0V/XR_00 M-00 0.u/0V/XR 0 0.u/V/XR 000p 0.u/V/XR R0 * *0.u/V/XR 0.u/V/XR 0.u/V/XR.u/0V/XR_00 M-00.u/0V/XR_00 M-00 0.u/V/XR 0.u/V/XR *n/v 0 0.u/V/XR 0.u/0V/XR L *_00 0.u/V/XR.u/0V/XR_00 M-00 u/0v_00 M-00 0u/0V_00 M-00 0.u/V/XR u/0v_00 M-00 u/0v_00 M-00 0.u/V/XR *n/v n/v L QT0RL00_00 *.u/0v/xr_00 M-00 0.u/V/XR 0 0.u/V/XR 0.u/0V/XR VTT X XF M K HV PE MI VTTLF RT PLL LV_ PE_ M_ TV TV/RT LV_ U restline J U U U U U U U U U U T T T0 T T T T T T R R R T U U T T T0 R J0 K K J J 0 0 W0 W V V0 H0 H F H 0 H L M K0 K U W V U U U T T T T T R R M L N N U J H VYN VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_NTF V_XF_ V_XF_ V_XF_ V_MI V_M_K_ V_M_K_ V_M_K_ V_M_K_ V_TX_LV V_HV_ V_HV_ V_PE_ V_PE_ V_PE_ V_PE_ V_PE_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF V_RT V_RT V V_PLL V_PLL V_HPLL V_MPLL V_LV _LV V_PE PE_ V_PE_PLL V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_NTF_ V_M_NTF_ V_M_K_ V_M_K_ V_TV V_TV V_TV V_TV V_TV V_TV V_RT V_TV V_Q V_HPLL V_PE_PLL V_LV_ V_LV_ *.u/0v/xr_00 M-00 0.u/V/XR 0.u/V/XR 0.u/V/XR *.u/0v/xr_00 M-00 L *_00 0 0u/0V_00 M-00 0.u/V/XR L _00 L _00.u/0V/XR_00 M-00 R _00.u/0V/XR_00 M-00 0 *.u/0v/xr_00 M-00 R 0 L QT0RL00_00 L _00 L0 _00 0.u/0V/XR *0.u/V/XR *.u/0v/xr_00 M-00 0.u/V/XR u/0v_00 M-00.u/0V/XR_00 M-00 *.u/0v/xr_00 M-00 0 u/0v_00 M-00 L QT0RL00_00 u/0v_00 M-00 0.u/V/XR L _00 0.u/0V/XR 0.u/V/XR 0.u/V/XR L _00.u/0V/XR_00 M-00 T 0 0.u/V/XR L _00 0.u/V/XR u/0v_00 M-00 *.u/0v/xr_00 M-00.u/0V/XR_00 M-00 n/v n/v 0.u/V/XR 0.u/V/XR
I=m T +.0V T H - modify K J J H H H R F Z0 R0 +.V I=00m U U U V W W Y E E E F F H H H J J J K K K K L U0 FX_ORE R0 T W W - modify Y 0 0 0 F F H0 H H H H J0 N UE V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_0 V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_0 V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_0 V_X_ V_X_ V_X_ V_X_ V ORE V M V FX V M LF V FX NTF V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF FX_ORE UF T I=???m T T I=000m V_NTF T V_NTF T V_NTF T V_NTF T - modify V_NTF U V_NTF U V_NTF U V_NTF U F V_NTF U0 F V_NTF0 U H V_NTF U H V_NTF U H V_NTF V H +.0V V_NTF V J V_NTF V J V_NTF V0 K - modify V_NTF V K V_NTF V K V_NTF V K V_NTF0 Y V_NTF Y J V_NTF Y M V_NTF Y L V_NTF Y0 L V_NTF Y V_NTF Y V_NTF Y V_NTF Y P V_NTF Y P V_NTF0 Y R V_NTF R V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF T0 V_NTF T V_NTF T V_NTF0 U V_NTF F U V_NTF F U V_NTF H U V_NTF H U V_NTF H U V_NTF H V V_NTF J V V_NTF J V - modify V_NTF J V V_NTF0 K K +.0V L L I=0m L L V_XM_NTF_ L0 L V_XM_NTF_ L L V_XM_NTF_ L M V_XM_NTF_ M M 0.u/V/XR V_XM_NTF_ M M V_XM_NTF_ M M V_XM_NTF_ M0 M V_XM_NTF_ M M V_XM_NTF_ M P V_XM_NTF_0 P P V_XM_NTF_ P P V_XM_NTF_ P P V_XM_NTF_ P L V_XM_NTF_ P0 L V_XM_NTF_ P L V_XM_NTF_ P R V_XM_NTF_ P R V_XM_NTF_ R0 R V_XM_NTF_ R R R R V V V restline Y +.V V NTF V XM NTF V XM NTF XOR / LLZ / lock Un-gating F F F onfiguration R 0 0 lock ating isabled *.0K _NTF_ T 0 XOR Mode Enabled _NTF_ T _NTF_ U 0 ll-z Mode Enabled F ynamic OT _NTF_ U _NTF_ V Normal Operation (efault) _NTF_ V Low = ynamic OT isabled _NTF_ F _NTF_ High = ynamic OT _NTF_ F F _NTF_0 Enabled(default) _NTF NTF_ F R R _NTF_ F *.0K *.0K _NTF_ K _NTF_ M F _NTF_ M _NTF_ P R _NTF_ P *.0K _NTF_ R _NTF_0 R _NTF_ R PIe Lane Low = Reverse Lane (default) F High = Normal _ F[:] have internal pullup ressistors. _ L _ L F _ R *.0K MIx selction Low = MI* F High = MI* (default) - modify +.0V I=0m +.V V_XM_ T F Low =.0V V_XM_ T V_XM_ K (V elect) High =.V V_XM_ K K 0.u/V/XR.u/0V/XR_00.u/0V/XR_00 V_XM_ J M-00 M-00 V_XM_ V_XM_ J NP design R *.0K F F[0:] have internal pulldown resistors. F0 +.V (VO/PIE oncurrent Operation) 0 = Only VO or PIE x is operational (default) R = VO and PIE x are operating simultaneously via the PE port *.0K F0 W Z0 Z0 +.V E Z0 0 Z0 Z0 0.u/V/XR_00 *.u/0v/xr_00 *.u/0v/xr_00 *0.u/V/XR *0.u/V/XR 0.u/V/XR 0.u/V/XR *0.u/V/XR *0.u/V/XR MI lane Reversal W Z0 M-00 M-00 T Z0 M-00 0 = normal 0.u/V/XR 0.u/V/XR_00 0 R (default) F M-00 u/0v_00 u/0v_00 *.0K = Reversed M-00 M-00 0.u/V/XR_00 M-00 I=00m F 0.u/V/XR 0 restline 0.u/V/XR.u/0V/XR_00 M-00.u/0V/XR_00 M-00 0.u/V/XR u/0v_00 M-00 0.u/0V/XR FX_ORE I=000m +.0V - X_ORE 0 0.u/V/XR 0.u/V/XR 0.u/0V/XR_00.u/0V/XR_00.u/0V/XR_00 0.u/V/XR 0.u/0V/XR M-00 M-00 M-00 - modify 0.u/0V/XR_00 M-00 0.u/0V/XR_00 M-00 0.u/V/XR I=m 0.u/V/XR Z0 *T R 0 +.V 0.u/0V/XR_00 M-00 0.u/V/XR 0.u/V/XR 0.u/V/XR 0 0.u/0V/XR 0.u/0V/XR.u/0V/XR_00 M-00 0.u/V/XR 0 0.u/0V/XR E OMPUTER ORP. N _NTF-/ ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
R Thermal ensor I=00m I=0m Thermistor - modify - MOIFY MVERF-TP +.V TP 0.V TP LIIX R HNNEL, E OMPUTER ORP. ustom Tuesday, February, 00 ize ocument Number Rev ate: heet of Z0 M_Q M_M0 M_Q M_Q M_Q# M_Q M_ M_ M_KE M_OT M_K M_#0 M_# M_VREF_MH Z0 PM_EXTT#0 M_ M_Q M_ M_ M_M M_0 M_# M_Q#0 M_M0 M_M M_Q# M_K M_OT0 M_WE# R_THERM M_Q M_M M_M M_Q# M_Q# Z0 Z0 M_ M_Q# M_0 M_Q# M_ M_Q M_M M_ M_K#0 M_K Z0 R_THERM M_ M_OT M_K# M_Q M_ M_Q0 M_ M_KE M_M M_Q M_ M_ M_ M_ M_Q# M_ M_R# M_KE Z0 M_Q# M_ M_ M_M M_ M_VREF_MH M_ M_Q M_M M_Q M_ M_ M_K# M_# M_WE# PM_EXTT# M_ M_Q M_Q# M_ M_0 M_Q M_Q# M_M M_M M_K0 Z0 M_ M_0 M_Q M_Q0 M_Q# M_M M_KE0 M_# M_R# M_# M_ M_ M_Q# M_Q#0 M_M M_ M_0 M_OT Z0 M_Q# M_ M_0 M_ Z0 M_Q# M_M M_M M_K# M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_VREF_MH +0.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V *0.u/V/XR 0.u/V/XR 00p R 0K R00 * *0p NPO 0.u/V/XR 0 0.u/0V/XR 000p TP 0 0.u/V/XR ON R_ON_REV 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 N N VP K0 K K#0 K# N N N 0 Q Q Q# Q Q Q Q Q Q# Q# Q N Q#0 Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q0 Q Q WE# L OT0 N/OT 0 # R# N/TET Q V V V V V V V 0 M0 Q Q Q 0# N/# M M M M M M M KE0 N/KE Q Q Q# Q# Q# Q# Q Q Q Q Q Q Q Q VREF V V V V V Q Q0 Q0 N/ N/ N/ 0/P N N R0 *0K.u/.V/XR_00 M-00 0 000p 00p 0.u/V/XR.u/.V/XR_00 M-00 0.u/V/XR 000p *0.u/V/XR 0.u/0V/XR *0p NPO R 0K R * *0p NPO 0.u/V/XR 0 0.u/0V/XR 0 0.u/V/XR 0.u/V/XR 0.u/0V/XR 0.u/V/XR 0.u/V/XR 0.u/0V/XR *0.u/V/XR 0.u/V/XR R 0K RT *0K_RT_00 0.u/0V/XR 0.u/V/XR TP R 0_ 0.u/0V/XR *0.u/V/XR 0.u/V/XR 0 *0p NPO 0 0.u/V/XR 0.u/0V/XR 0.u/V/XR 0 0.u/V/XR *0.u/V/XR 0.u/V/XR 0 0.u/V/XR U *M0 V + - THERM# N LERT T LK R 0_ R * 0.u/V/XR 0.u/0V/XR 0 0.u/0V/XR 0 0.u/0V/XR 0 0.u/V/XR 0 0.u/0V/XR 0.u/0V/XR 00 0.u/V/XR 0.u/V/XR.u/.V/XR_00 M-00 0 0.u/V/XR TP R0 * Q *N0 E 0.u/V/XR R0 *.K_ R *00 ON R_ON_NORML 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 N N VP K0 K K#0 K# N N N 0 Q Q Q# Q Q Q Q Q Q# Q# Q N Q#0 Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q0 Q Q WE# L OT0 N/OT 0 # R# N/TET Q V V V V V V V 0 M0 Q Q Q 0# N/# M M M M M M M KE0 N/KE Q Q Q# Q# Q# Q# Q Q Q Q Q Q Q Q VREF V V V V V Q Q0 Q0 N/ N/ N/ 0/P N N R 0K 0.u/V/XR 0.u/0V/XR.u/0V/XR_00 M-00.u/.V/XR_00 M-00 M_WE# 0, M_R# 0, M_KE0, M_K M_Q[:0] 0 M_M[:0] 0 M_#, E_R_TEMP M_WE# 0, M_#0, M_K#0 PM_EXTT# M_KE, M_K0 M_R# 0, M_#, M_Q#[:0] 0 M_KE, M_M[:0] 0 M_K _M_LK,, M_[:0] 0, _M_T,, M_# 0, M_Q[:0] 0 _M_LK,, M_K M_OT0, M_KE, M_OT, M_OT, _M_T,, M_[:0] 0, _M_T,, M_[:0] 0, _M_LK,, M_Q[:0] 0 M_K# M_# 0, M_K# M_OT, M_Q#[:0] 0 M_Q[:0] 0 M_K# M_[:0] 0, M_#, PM_EXTT#0 M_VREF_MH
0, M_[:0] 0, M_[:0] 0, M_[:0] 0, M_[:0] RP PRXR_00 M_ M_ M_, M_KE R, M_KE 0, M_ R, M_OT, M_OT0 R, M_#, M_#0 R, M_KE0 0, M_R# RP PRXR_00 M_ M_ M_ M_ RP PRXR_00 M_0 0, M_WE# 0, M_#, M_# RP PRXR_00 M_0 M_0 0, M_WE# 0, M_# RP PRXR_00 M_, M_#, M_OT 0, M_ R, M_OT R, M_KE 0, M_R# M_ R +0.V RP0 PRXR_00 M_ M_ M_ M_0 RP PRXR_00 RP PRXR_00 M_ M_ M_ M_ RP PRXR_00 M_ M_0 M_ M_ RP PRXR_00 M_ M_ M_ RP PRXR_00 M_ M_ M_ M_ RP PRXR_00 M_ M_ M_0 MRT POWER VI VI VI VI VI VI VI0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.000-00mV 0 0 0 0 0 0 0 0 0 0 VORE +_mv.000. -0mV -.mv.0 -mv.00-0mv.000-00mv.000-00mv 0 0 0 0 0 0 0.000-00mV 0 0. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H_VI0 H_VI MP_0MV_EN# H_VI0 H_VI LV_LOK MP_0MV_EN# LV_LOK MP_0MV_EN# H_VI R R LV_LOK Q N00 M-OT * M-R00-UW Q N00 M-OT Q N00 M-OT * M-R00-UW Q N00 M-OT Q N00 M-OT HH_VI PU_VI0 PU_VI R * M-R00-UW MP_00MV_EN# MP_00MV_EN# Q N00 M-OT +.0V +.0V +.V +.V R H_VI H_VI R *.K M-R00-UW R M-R00-UW PU_VI H_VI H_VI T M-OTE R R 0K K M-R00-UW M-R00-UW Z0 Z0 Q N0 M-OT E 0K M-R00-UW LV_LOK Q N00 M-OT +.0V +.0V R R *.K *.K M-R00-UW M-R00-UW H_VI H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI H_VI H_VI RP *PRX0_00 M-RPM0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI0 T M-OTE RP *PRX0_00 M-RPM0 +.0V +.0V +V RP PRX.K_00 M-RPM0 PU_VI PU_VI PU_VI PU_VI RP PRX.K_00 M-RPM0 0.u/0V/XR H_VI H_VI H_VI HH_VI FROM E ONTROLLER RP 0 Z0 E_VI Z0 E_VI Z0 E_VI Z0 E_VI 0 PRX00_00 M-RPM0 R.K MP_EN +V M-R00-UW MP_EN# OE# OE# U V TO PWM ONTROLLER ( PU V_ORE PWM) PU_VI PU_VI PU_VI PU_VI MP_EN# Q N00 M-OT N NT M-TOP E OMPUTER ORP. Termination / mart Power/ IN ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
N_RT_LK N_RT_T +.V +V R0 00 Z R.K +.V +V R0 00 Z R.K Q N00 +.V Q R0 N00.K R.K LYOUT: Place L, L,L 0 degree from each other. L Panel ELET L_EL# L_EL# L_EL0# L L L L L L H H L L H H H L L H L H H H L H H H reserved 0X 00X00 0X00 reserved 0X00 0X00 0X00 +.V R0 R R R R K K K 0K 0K L_EL0# L_EL# L_EL# N_LEI_LK N_LEI_T N_LV_N0 N_LV_P0 N_LV_LKN N_LV_LKP N_LV_N N_LV_P N_LV_LKN N_LV_LKP L_EL# N_LEI_LK +.V_L L I= 0.u/0V/XR ON N_LV_N0 N_LV_P0 V_EI N_LV_LKN 0 N_LV_LKP N_LV_N N_LV_P 0 N_LV_LKN N_LV_LKP 0 N N N N N N N N L QT0RL00H-_00 +.V 0 0.u/0V/XR N_LV_N N_LV_N N_LV_P N_LV_P N_LV_N0 N_LV_N0 N_LV_P0 N_LV_P0 N_LV_N N_LV_N N_LV_P N_LV_P N_LV_N N_LV_N N_LV_P N_LV_P L_EL# L_EL0# N_LEI_T N_RT_VYN R0 * +.V 0-0-MOIFY U H0KR LYOUT: Resistor / aps / ead close to RT_ON. Z0 Z0 R0 R0 0 00p RT ON N_LV_LKN N_LV_LKP N_LV_N0 N_LV_P0 N_LV_LKN N_LV_LKP N_LV_N N_LV_P L_ON -0 N_LV_N0 N_LV_P0 N_LV_N N_LV_P N_LV_N N_LV_P N_LV_N N_LV_P N_RT_HYN N_RT_ N_RT_ N_RT_R H0KR U R * RT resistor trace impedance between N and 0 ohm resistor should be. ohm +/- %, etween two 0 ohm resistors should be 0 ohm, etween 0 ohm resistor and connector should be ohm +/- %. Z0 Z0 0-0-MOIFY R R0 R0 _ 00p 0p.p RT_LK R0 RT_VYN# R0 RT_HYN# 0p 0.p RT_T L F0K-00T0 RT_LUE L F0K-00T0 RT_REEN L0 F0K-00T0 RT_RE Z0 p *0p *0p *0p p p NPO NPO NPO NPO NPO 0-0-MOIFY 0.u/0V/XR N 0 N RT_ON K-0 IO_N L +V QT0RL00H-_00 *0p *0p *0p *0p *0p *0p *0p *0p L V +.V I= R K Z0 Q O L QT0RL00H-_00 Z0 R *K 0u/0V_00 M-00 *0p *0p *0p *0p 0 *0p *0p *0p *0p I= +.V_L u/0v_00 M-00 WEM +V/+V/. +V +V LUETOOTH +V/+V/. 0-0-MOIFY PM_PRLPVR LOW N_LV_EN R0 00K_ 0.u/0V/XR - modify Z L_EN Q N00 0.u/0V/XR R 0 R *_00 PM_PRLPVR Z LOW R / HIH K M-R00-UW // LOW modify 0-0 modify R PIO-N PIO R *0K L U_PN RI RO U_PP RI RO *TM-00T IR R R - modify *.u/0v/xr_00 M-00 WEM_W IR_RX R _00 Z Q N00 *OPEN-MLL OPEN-MLL PJP +V I=0. ON N N N N *WEM_W_ON -0XX-XXR Q O 0.u/0V/XR I=. Z WEM_U- WEM_U+ PIO-N R0 0-0 modify ON Z0 N N N N *WEM_ON 0- L QT0RL00H-_00 PIO0 T_T T_LK U_PP U_PN U_PP U_PN R * Z T_T T_LK U_PP U_PN U_PP U_PN +V +V R *0K L Z R0.K R.K RP R _00 R0 *K M-R00-UW RI RI LI LI RO RO LO LO R *_00 *OPEN-MLL OPEN-MLL PJP Z Q *N00 +.V 0u/0V_00 PRX0_00 M-RPM0 *0T-00 Z Q0 *O I=. R T_ON 0.u/0V/XR _00 0 0.u/V/XR / T_T R T_LK R R // u/0v_00 0 = Enable = isable _UP _UN HIH LOW I=. Z Z Z T_T_T T_T_LK Z 0/ modify ON N N *U dongle -0L N N INVERTER -VIEO *0.u/0V/XR_00 +.V M-00 *0.u/0V/XR_00 L 0.u/0V/XR M-00 QTL00H-_00 ON _L L0 QT0RL00H-_00 Z0 RIHTNE N N_L_EN KL_ON QT0RL00H-_00 L Z0 N KL_E U H0KR INVERTER_ON M-0-0.u/0V/XR 0-X0XR 0.u/0V/XR L FI0F-RK_00 Z N_TV_ R 00 p p 0 0/ Modify NPO NPO IO_N L ON FI0F-RK_00 Z N_TV_ R p p 0 NPO NPO *-VIEO 00-X0XX-X LYOUT: Resistor and caps close to -VIEO_ON. IO_N TV resistor trace impedance between N and ohm resistor should be. ohm +/- %, The trace impedance between ohm resistor and connector should be ohm +/- %. E OMPUTER ORP. L&-VIO&RT&WEOM&LUETOOTH ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of N N N N
RT ircuitry +.V +.V_RT T_ T 0 +.V_RT_R R R 0K u/0v_00 M-00 H_FERR# H_PRTP# H_PLP# Modify R * R * R * +.0V +.V R0 K U_T+ T T R M JP OPEN_ u/0v_00 M-00 *0.u/V/XR p NPO Y.KHz_M PIN,= N_POWER R 0M U H_RIN# H_0TE H_OUT R 0K R 0K R *K R0-KT p NPO M_INTRUER# 0 = isable Internal.Vs LO = Enable Internal.Vs LO IH-M Internal VR Enable trap (Internal VR for Vccus_0, Vccus_ and VccL_) Low = Internal VR isabled High = Internal VR Enabled (efault) IH-M LN00_LP trap (Internal VR for VccLN_0 and VccL_0) Low = Internal VR isabled High = Internal VR Enabled (efault) Z_ITLK R0 K +.V_RT R * R0 K +.V_RT R * I=0m IF Not use : N R p R Z_YN Z_RT# R Z_TIN0 R Z_TIN R Z_TOUT RT_X RT_X F RT_RT# F M_INTRUER# INTVRMEN F LN00_LP +.V modify R E0.R_ 0 H Z0 H_IT_K J H_YN J E H_IN0 J H_IN H H H_OUT E R.K H_OK_EN# +.V E0 HLE# F0 IH_RXN0 IH_RXN0 F IH_RXP0 IH_RXP0 F 0 00p IH_T_TXN0 IH_TXN0 H 0 00p IH_T_TXP0 IH_TXP0 H TP T_RXN_ T_RXP_ TP T_TXN_ TP J T_TXP_ TP J TP T_RXN_ F TP T_RXP_ F T_TXN_ TP E T_TXP_ TP0 E IH_T_LK# IH_T_LK Z0 R. within 00 mils RTX RTX RTRT# INTRUER# INTVRMEN LN00_LP LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_OK#/PIO LN_OMPI LN_OMPO H_IT_LK H_YN H_RT# H_IN0 H_IN H_IN H_IN H_OUT RT LN IH H_OK_EN#/PIO H_OK_RT#/PIO TLE# TXN TXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI T PU LP IE FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO 0TE 0M# PRTP# PLP# FERR# PIO/PUPWR INNE# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# TP 0 0 0 # # IOR# IOW# K# IEIRQ IORY REQ E F F E F F E F E 0 H E V U V T V T T T R T V V U V U Y Y W W Y Y Y W Z0 H_0TE _PRTP# R _PLP# R _FERR R H_RIN# H_THERMTRIP_R Z0 IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P LP_0, LP_, LP_, LP_, LP_FRME#, LRQ0# TP H_0TE H_0M# H_PRTP# H_PLP# H_PRTP#,, H_PLP# H_FERR# H_FERR# H_PWR H_INNE# +.0V H_INIT# H_INTR H_RIN# R H_NMI H_MI# R H_TPLK# R._ lose to in ". TP IE_P[0..] IE_P0 IE_P IE_P IE_P# IE_P# IE_PIOR# IE_PIOW# IE_PK# Intel IRQ INT_IRQ IE_PIORY IE_PREQ PM_THRMTRIP#,, IH E OMPUTER ORP. IHM PU/T/IE / ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
(.V,.V, PI LK m) s Test Point ample on PWROK rise edge PI_NT#0 0 0 PI_# PI_FRME# PI_IRY# PI_TRY# PI_TOP# PI_ERR# PI_EVEL# PI_PERR# PI_LOK# PI_REQ#0 PI_REQ# PI_REQ# PI_REQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQE# INT_PIRQF# INT_PIRQ# INT_PIRQH# PM_LKRUN# INT_ERIRQ PI_PR PI_RT# OOT IO LOTION PI PI LP trap PKR :Normal 0:No Reboot Mode PI_NT#0 R0 *K PI_# R *K R0.K R.K R.K R0.K R.K R.K R.K R.K R.K R.K R0.K R.K R.K R.K R.K R.K R.K R0.K R.K R.K R.K R.K R R (EFULT), PI_[:0] *.K *.K +.V TP TP INT_PIRQ# INT_PIRQ#,,, PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PLT_RT# 0 E 0 E 0 F E E E E F 0 U PI 0 REQ0# NT0# REQ#/PIO0 NT#/PIO REQ#/PIO NT#/PIO REQ#/PIO NT#/PIO 0 /E0# /E# /E# /E# IRY# PR PIRT# EVEL# 0 PERR# PLOK# ERR# TOP# TRY# FRME# PLTRT# PILK PME# 0 INTERRUPT I/F PIRQ# PIO/PIRQE# PIRQ# PIO/PIRQF# PIRQ# PIO/PIRQ# PIRQ# PIO/PIRQH# IH 0.u/V/XR E F 0 E F E F0 0 F F +.V PI_REQ#0 PI_NT#0 PI_REQ# PI_NT# PI_REQ# PI_NT# PI_REQ# PI_NT# PI_E#0 PI_E# PI_E# PI_E# PI_IRY# PI_PR PI_RT# PI_EVEL# PI_PERR# PI_LOK# PI_ERR# PI_TOP# PI_TRY# PI_FRME# IH_PLT_RT# PI_PME# INT_PIRQE# INT_PIRQF# INT_PIRQ# INT_PIRQH# U H0KR TP TP TP TP TP TP PI_REQ# PI_NT# PI_E#[0..] IH_PLT_RT# PI_E#[0..], *0K R +.V Modify / TP R *0K PM_M_UY# MLK MT LINK_LERT# MLINK0 MLINK PM_RI# PM_U_TT# PM_Y_RT# PM_M_UY# M_LERT# PI_IRY# PM_TPPI# R0 PM_TPPU_IH# PI_PR PM_TPPU# PI_RT#,,, PM_LKRUN# PI_EVEL# PM_LKRUN# TP PIE_WKE# TP0 INT_ERIRQ TP,, INT_ERIRQ PM_THRM# PI_TOP#, PM_THRM# PI_TRY# _VR_PWR PI_FRME#, Z0 TP -PI_LK PI_PME# E_EXTMI# IO_RE TP0 T_ON LN_PHYP TP TP TP PIO TP PIO0 TP TP R * QRT_TTE0 QRT_TTE R0 * QRT_TTE LK_T_OE# LK_T_OE# O_ET IH_PIO MF_MOE Z_PKR MH_YN# Z_PKR MH_YN# IH_TP J E F F E0 H E F J0 J J J H E H E 0 H F J 0 U MLK MT LINKLERT# MLINK0 MLINK RI# U_TT#/LPP# Y_REET# MUY#/PIO0 MLERT#PIO TP_PI#/PIO TP_PU#/PIO LKRUN#/PIO WKE# ERIRQ THRM# VRMPWR TP TH/PIO TH/PIO TH/PIO PIO PIO TH0/PIO PIO PIO0 LOK/PIO QRT_TTE0/PIO QRT_TTE/PIO TLKREQ#/PIO LO/PIO TOUT0/PIO TOUT/PIO M T PIO LOK Y-PIO PIO Power MT ontroller Link L_RT# J L_RT# R_V_ET PKR MEM_LE/PIO J Z0 R.K LERT#/PIO0 J +.V J Z0 R.K MH_YN# NETETET/PIO F WOL_EN WOL_EN/PIO J TP IH R Resume Power PIO [:0] [:] [:] 00K MI +.V RP PRX0K_00 T0P T0P PIO/T0P J TP TP PIO/TP J0 TP TP PIO/TP F TP TP PIO/TP LK LK_IH LK LK_U U_LK ULK IH_LP_# R 00 PM_LP_# LP_# IH_LP_# PM_LP_# PM_LP_#,,, R 00 LP_# F IH_LP_# R 00 PM_LP_# PM_LP_# LP_# TP PM_LP TTE# TP _TTE#/PIO H E IH-PWROK PWROK - modify J IH_PRLPVR R 00 PM_PRLPVR PIO/PRLPVR PM_PRLPVR, E PM_TLOW# TLOW# PWRTN# -PWRTN# H0 Z0 R PLT_RT# LN_RT# RMRT#_IH R 00 PM_RMRT# RMRT# PM_RMRT# K_PWR E LK_PWR E L_PWROK LPWROK J Z0 TP LP_M# L_LK0 F L_LK0 L_LK E L_T0 F L_T0 L_T F L_VREF0_IH L_VREF0 H L_VREF_IH L_VREF R +.V +.V * 0-0-MOIFY PI_NT# 0 = wap override enabled = default MLK MT IO_RE R 0K E_EXTMI# R *0K PM_LP TTE# R *0K PM_THRM# R.K Z_PKR R *.K MH_YN# R *0K PM_PRLPVR R *00K LK_T_OE# R0 0K MF_MOE R 0K PM_M_UY# R *0K MF_MOE IO_RE PM_RI# M_LERT# PM_Y_RT# MLINK0 MLINK PIE_WKE# R_V_ET MLK MT LINK_LERT# PM_TLOW# U_LK PLT_RT# IH_LP_# IH_LP_# LN_PHYP WOL_EN PM_RMRT# IH-PWROK IH_PIO IH_TP R *K R 0K R 0K R 0K R 0K R 0K R K R0 *0K R 0K R 0K R 0K R.K R *0K R *.K R *.K R *.K R 0K R 00K R 0K R 0K R 0K R *0K +.V R * R * R.K Z0 Q N00 Q N00 Z0 R.K +.V +.V +.V +.V R 0K R 0K modify _M_LK,, modify Modify / _M_T,, IH-PWROK VORE_LK_EN# L_PWROK +.V L_PWROK INT-PIRQ# N INT-PIRQ# : N INT-PIRQ# : N INT-PIRQ# N PI_REQ#0 N PI_REQ# : N PI_REQ# N PI_REQ# : N PI_NT#0 N PI_NT# N PI_NT# N PI_NT# : N R * uffer to reduce loading on PLT_RT# R 00K U +.V *H0KR R R * R *00K R *0.u/V/XR R 0K _VR_PWR Q N00 R 00K PM_PWROK_ close 0.u/V/XR ELY_VR_PWROO, +.0V_ON, PM_PWROK_ R 00K PIE 0 PIE PIE PIE PIE PIE PIE LII NEW R minir LRI NEW R minir PI-E WKE UP For New ard For Mini ard For Lan0E U0 U U U U No No U No No U No No U No No U No No U PIE_TXN0 PIE_TXP0 PIE_TXN PIE_TXP PIE_TXN PIE_TXP LII on board ON0 NEW R MINI R MOULE ext board ON LUETOOTH ext board ON WEM_ON L ardread PIE_WKE# 0/ Modify 0 LRI 0.u/V/XR 0.u/V/XR 0.u/V/XR T R * T R * T R * 0.u/V/XR PIE_RXN PIE_RXP 0.u/V/XR PIE_RXN PIE_RXP 0.u/V/XR +.V PIE_RXN0 PIE_RXP0 R R0 R R R R R R R R 0K 0K 0K 0K 0K 0K 0K 0K 0K 0K INTEL REOMMN 0K PIE_RXN0 PIE_RXP0 PIE_TXN0_ PIE_TXP0_ PIE_RXN PIE_RXP PIE_TXN_ PIE_TXP_ PIE_RXN PIE_RXP PIE_TXN_ PIE_TXP_ PI_# MINIR_WKE# NEWR_WKE# LN_WKE# U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# P P N N M M L L K K J J H H F F E E E F J E F J H U PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn/LN_RXN PERp/LN_RXP PETn/LN_TXN PETp/LN_TXP PI_LK PI_0# PI_# PI_MOI PI_MIO O0# O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO O# O# IH PI-Express PI U irect Media Interface L_VREF_IH 0 0.u/V/XR MIXN V MIXP V MI0TXN U MI0TXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN T MI_LKP T MI_ZOMP Y MI_IROMP Y UP0N UP0P UPN H UPP H UPN H UPP H UPN J UPP J UPN K UPP K UPN K UPP K UPN L UPP L UPN M UPP M UPN M UPP M UPN N UPP N URI# F URI F +.V R0.K_ R MI_ZOMP U_RI_PN modify MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_MI_IH# LK_MI_IH R lose to (<00mil) L_VREF0_IH U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN 0 U_PP 0 0.u/V/XR +.V R._ R *.K_ E OMPUTER ORP. IHM IO/PIO/U/Y-/ R0.K_ R ize ocument Number Rev ustom LIIX ate: Tuesday, February, 00 heet of
PI-E IH ore Power Integrated VRM enable(ln00lp) Integrated VRM enable(intvmen) V I=m V_0 I=0m V I=0m V_ I=m I=m I=m I=m I=0m I=m I=m I=m I=m I=m I=m I=m I=m I=0m I=0m modify 0-0-MOIFY 0-0-MOIFY LIIX IHM Power -/ E OMPUTER ORP. ustom Tuesday, February, 00 ize ocument Number Rev ate: heet of VP VLN.0 V_MIPLL VU_0 VREF_U IH_V_MI VPU V_H VREF VL_ VL_0 _TPLL VUPLL VUORE VUPLL _TPLL VUORE VLNPLL VLNPLL VP VLN_ VU_ VU_H VU_H V_H VPU +.V +.V +V +.V +.V +.0V +.V +.V +V +.V +.V +.V +.0V +.V_RT +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.0V +V +.V +.V *0.u/V/XR R *_00 L0 _00 0.u/V/XR 0.u/V/XR 0.u/0V/XR_00 M-00 0 *0.0u/V/XR *0.u/V/XR 0.u/V/XR R *_00 *0.u/V/XR TP R0 0.u/V/XR R0 *_00 R0.u/0V/XR_00 M-00 R *_00 0.u/V/XR 0.u/0V/XR 0.u/V/XR 0.u/V/XR 0 0.u/V/XR 0.u/V/XR 0.u/0V/XR *0.0u/V/XR T 0.u/V/XR 0.u/V/XR *0.u/V/XR L _00 R0 00 0.u/V/XR R00 _00 0.u/V/XR 0.u/V/XR R 0.u/0V/XR.u/0V/XR_00 M-00 u/0v_00 M-00 0.u/V/XR.u/0V/XR_00 M-00 0.u/V/XR u/0v_00 M-00 0.u/V/XR.u/0V/XR_00 M-00 TP0 T 0 0.u/V/XR.u/0V/XR_00 M-00.u/0V/XR_00 M-00 *0.u/V/XR L _00 IE RX TX VP U ORE PI ORE LN POWER VPU VPU V ORE UF IH T E E E F F H H J J K K L L L M M N N N P P R R R R T T T T T U U V V V W Y E F H J 0 H E F L L L L L L M M P P T T E F U V W W W Y 0 H P P N P P P P P R R R F L L M M W J F F 0 V V V U V V V U R E E F E0 E F F0 R J F0 J VREF[] VREF[] VREF_U Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] VUPLL Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[0] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[0] V_PU_IO[] V_PU_IO[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[0] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[0] Vcc_[] VH Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[0] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vccus_[] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] VRT VTPLL VLN_0[] VLN_0[] VLN_[] VLN_[] VLNPLL VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_ Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] Vcc_0[] VMIPLL V_MI[] V_MI[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] VL_[] VL_[] VL_0 VL_ Vccus_[] VU_[] VU_[] VU_0[] VU_0[] VUH 0.u/V/XR 0.u/V/XR 0.u/V/XR 0 0.u/0V/XR R _00 R * 0.u/V/XR 0.u/V/XR.u/0V/XR_00 M-00 0.u/V/XR R0 R 0.u/0V/XR.u/0V/XR_00 M-00 0 *0.u/V/XR 0.u/V/XR R _00 0.u/V/XR UE IH 0 E E E E E E E E F F F F F H0 H H H H F H H H H H H J 0 E E E E F E F F F E 0 H H H H H J J J J J J K K K K K K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y U W H H J J J J 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF0 _NTF _NTF *.u/0v/xr_00 M-00 0.u/V/XR u/0v_00 M-00 0.u/V/XR 0.u/V/XR 0.u/V/XR *.u/0v/xr_00 M-00 0 0.u/V/XR R *_00 R0 R 0.u/V/XR.u/0V/XR_00 M-00 0 0.u/V/XR 0 *0.u/V/XR 0.u/V/XR 0.u/V/XR 0.u/0V/XR 0.u/V/XR u/0v_00 M-00 0.0u/V/XR R _00.u/0V/XR_00 M-00 *.u/0v/xr_00 M-00 0.u/V/XR.u/0V/XR_00 M-00 R _00