STATIC TIMING ANALYSIS

STATIC TIMING ANALYSIS

Standard Cell Library NanGate 45 nm Open Cell Library Open-source standard cell library Over 62 different functions ranging from buffers, to scan-able FFs with set and reset, to AOI and OAI gates Multiple drive strengths Over 170 total different standard cells Corners available: Slow, Typical, Fast Low temperature and worst low temperature Views available: Libraries in Verilog and Spice (pre and post parasitic extracted netlists) Cell layouts in GDSII Geometric library in Library Exchange Format (LEF) Liberty (.lib) formatted libraries with various timing data others... http://www.nangate.com/?page_id=2325 EEC 180B, B. Baas 67

Example INV_X1 Smallest and weakest inverter. It should be the smallest gate in the entire library! 0.532 um^2 Input capacitance of 1.7002 ff EEC 180B, B. Baas 68

Estimating propagation delay is generally done in one of two ways: Dynamically: delays are measured during an actual simulation Statically: worst-case delays are calculated by interpolating data in propagation delay tables This method is very fast (compare with how long it would take to simulate all possible input patterns into a 64-bit adder) This method will find the absolute slowest path in a system which may be unnecessarily pessimistic if the worst-case path is never used EEC 180B, B. Baas 69

Estimating propagation delay statically often yields a good estimate because the delay is a strong function of only a few factors: 1) input transition time the rise and fall time of the gate s input 2) load capacitance a) input capacitance of gate loads b) wire interconnect 3) Process, Supply voltage, Temperature ( PVT ) these are typically handled by separate libraries EEC 180B, B. Baas 70

Estimate the propagation delay of the leftmost inverter among the three INV_X1 inverters if the wire s capacitance is 12 ff and the input transition time is 1.2 ps = 0.0012 ns First, calculate the total capacitive load of the gate under consideration Total load = 12 ff + 2 * 1.7002 ff = 15.4 ff Next interpolate C_load to get an estimate of the propagation delay t p-fall = (15.4 0.3656)/(60.73 0.3656) * (0.08 0.00) + 0.00 = 0.0199 ns = 19.9 ps t p-rise = (15.4 0.3656)/(60.73 0.3656) * (0.15 0.01) + 0.01 = 0.0449 ns = 44.9 ps transition time = 1.2 ps = 0.0012 ns 12 ff EEC 180B, B. Baas 71

Static Timing Analysis In the more general case, calculations begin with the FF and move forward in the pipe stage Find capac. load of Q output 1.7002 ff + C_wire here Calc FF output transition time Calc FF Clk-to-Q delay clk Notice output transition time is the same for any input transition time EEC 180B, B. Baas 72

Things get a little more complex when the input transition time is not one of the values given in the table (e.g., 0.0012 or 0.1985 ns in this table) In this case we need to use a bilinear interpolation and conceptually think of interpolating in two steps For example, if an INV_X1 had an input transition fall time of 0.025 ns, and an input transition rise time of 0.035 ns, we could solve the problem by first generating these tables:...and then interpolating as in the previous example Or we could interpolate C_load first and then input transition time second same result EEC 180B, B. Baas rise x x 73 fall x 0.025 0.035 x

Output transition times are calculated in a similar manner Which are then used to calculate delays for subsequent gates driven by this particular gate EEC 180B, B. Baas 74

The situation gets increasingly complex with gates with more than one input In these gates, a separate delay calculation is performed from each rising/falling transition of each input to the output NAND2_X1 The delay assigned to an output node is the longest total rise and fall delays considering all possible paths. This is the slowestpossible case Gates with multiple outputs can be viewed and calculated as separate gates Note that in general, delays from inputs to outputs varies for different inputs even for gates like NANDs! Notice these are in general not equal EEC 180B, B. Baas 75