Keysight Technologies 2018.03.29 Heidi Barnes 1
S I G N A L I N T E G R I T Y A N D P O W E R I N T E G R I T Y Hewlett-Packard Agilent Technologies Keysight Technologies Bill and Dave s Company and the HP Way High Frequency Simulation Tools Test and Measurement 2
T H E T R A N S M I S S I O N O F I N F O R M AT I O N ~2 bits per second ~25,000,000,000 bits per second 01010101011101110110 http://www.sleewee.com/sos-distress-signal.php https://www.cloudyn.com/blog/10-facts-didnt-know-server-farms/ 3
F O L L O W T H E R E T U R N PAT H The Channel ADS Channel Simulator Poor Ground Return - Fail Engineered Design - Pass Eye Diagram (Overlay of rising and falling data transitions) 4
E N G I N E E R E D D E S I G N V S. C O S T LY D E B U G / R E D E S I G N What is so hard about stringing a wire between the transmitter and the receiver? Where was the SI Engineer in 1858? Transatlantic telegraph cable In 1858 signal quality declined rapidly, slowing transmission to an almost unusable speed. The cable was destroyed the following month when Wildman Whitehouse applied excessive voltage to it while trying to achieve faster operation. 5
N E T L I S T O F C O N N E C T I O N S Modern High Density Electronics 1000 s of nets 1 ground net Barely noticeable on a schematic Typically the largest copper net in layout 6
W H AT D E S I G N M A R G I N D I D I G I V E U P? Marisa Alia-Novobiliski, AFRL, NextFlex leverage open-source community to create flexible circuit system AFRL Feb. 2, 2018 7
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W AT C H O U T F O R H I G H C U R R E N T D E N S I T I E S I N T H E G R O U N D R E T U R N PAT H Electronic devices produce HEAT Joule losses in metallization produce HEAT Heat is transferred to the ambient (conduction, convection, radiation) Heat causes a Temperature rise in the electronic circuits Thermal validation is needed to avoid Component overheating Thermal stress Electronic malfunctioning 9
W AT C H O U T F O R C U R R E N T C O N S T R I C T I O N P O I N T S Coupled Electro-Thermal Equations Electric resistance R s [V/A] Thermal resistance R k [K/W] V 2 V 1 R s I T T R Q 2 1 k s k Where electric resistance R s changes with temperature T Where the injected heat flux Q changes with voltage V 10
H I G H C U R R E N T D E N S I T Y I N A S I N G L E P O I N T G R O U N D R E T U R N C O N N E C T I O N 27 mil trace Via Cross Section 200 mil trace >> Via Cross Section ADS PIPro Simulation Equivalent cross section via has more conductive cooling than the trace. Wide trace provides conductive cooling for the via. 11
M O D E R N C I R C U I T S A R E N E V E R J U S T D C Current equals voltage divided by the resistance R I V R Resistor Steady state Current flow equals capacitance times the rate of voltage change. I C C dv dt Capacitor + + + + - - - - Electric field between two plates Voltage equals inductance times the rate of current change + V L L di dt Inductor _ Magnetic fields surrounding the current in a wire. 12
T H E B E G I N N I N G S O F M A X W E L L S E Q U AT I O N S F O R E L E C T R O M A G N E T I C T H E O R Y ( E M ) Voltages and Currents are changing with Time and Distance (Magnitude and Phase) Create a simple model of a transmission line. Oliver Heaviside 1850-1925 For small R and G Sinusoidal Input Utilize calculus to analyze the model when summing a series of incremental length sections. Resulting Relationships 13
E R I C B O G AT I N S I G N A L I N T E G R I T Y E VA N G E L I S T Derivation from Telegrapher Equations: Z 0 L C Derivation from transmission line charging: Z 0 1 vc L Independent of Length Q x C CL x, I, Q CV t t v CL xv V 1 then I vclv and Z x I vcl v The Math. 14
F A S T E R R I S I N G E D G E H A S H I G H E R F R E Q U E N C I E S What is high speed? V=IR The Channel has finite length: Speed of Tx : Signal Rise-time Type of Data : Data Rate Gb/s Speed of Channel: Time Delay Rise Time 20 80% Unit Interval velocity 12 0.22 Frequency 3dB Dk 1 DataRate NRZ mils ps ps 15
db(single_c_21mil..s(2,1)) db(single_clc_21mil..s(2,1)) db(perfect_match_21mil..s(2,1)) INSERTION LOSS S21 (db) G R O U N D R E T U R N D I S C O N T I N U I T Y I N A C O N N E C T O R T R A N S I T I O N 0-1 -2-3 -4 MICROSTRIP TRANSMISSION LINE DISCONTINUITY EXAMPLE L-C-L C MICROSTRIP NO DISCONTINUITY (50 OHM MATCHED IMPEDANCE) CAPACITIVE DISCONTINUITY (50 OHM MATCHED IMPEDANCE) L-C-L FILTER DISCONTINUITY (50 OHM MATCHED IMPEDANCE) -5 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY freq, GHz (GHz) AGILENT ADS SIMULATION 16
E N E R G Y L O S T D U E T O I M P E D A N C E R E F L E C T I O N S C A N R A D I AT E Ground Fill Chip and Wire on PCB Shielded cavities Controlled Impedance Transmission Lines Edge plating Ground Signal Ground Interconnects 17
I T D E P E N D S. I N E E D A S I M U L AT O R! Too much loss and no signal gets through 18
D E S I G N C O N 2 0 1 8 : 3 2 T O 5 6 G B / S S E R I A L L I N K A N A LY S I S A N D O P T I M I Z AT I O N M E T H O D S F O R PAT H O L O G I C A L C H A N N E L S T U T O R I A L 32 Gb/s NRZ Signaling 19
I M P E D A N C E I S S T I L L A C H A L L E N G E Supply It takes time for the supply to respond to the demand. Consumer If the flow at the supply is different than at the consumer what happens? 20
T I M E D O M A I N P O W E R R A I L R I P P L E D U E T O A L O A D T R A N S I E N T Power Rail Natural Response Forced Response Volts Amps Load Current Step Load AC Load Keysight Infiniium S-Series Oscilloscope 21
P O W E R I N T E G R I T Y I S D E L I V E R I N G T H E R I G H T P O W E R T O T H E L O A D Voltage Regulator Module VRM PCB Power Distribution Network PDN Package + Die Circuit LOAD Target Impedance Calculation Z Target V I Max Ripple Max Transient Load 22
F L AT I M P E D A N C E V S F R E Q U E N C Y F O R B E S T P E R F O R M A N C E Decoupling Capacitors Target Z 40% Fewer Components Original Decaps Optimized Decap Design DesignCon Paper 2017: H. Barnes, J. Carrel, S. Sandler, Power Integrity for 32 Gb/s SERDES Transceivers 23
E N E R G Y S W I N G S B E T W E E N T H E L A N D T H E C Energy stored in the Magnetic Field V t = L di dt Z = jωl Energy stored in the Electric Field I = න C dv dt Z = 1 jωc B L E Phase V Leads I Phase V Lags I 24
PA R A L L E L I N D U C TA N C E C A N R E S O N AT E W I T H T H E D E C O U P L I N G C A PA C I TA N C E Parallel L-C in the PDN V R L supply C bulk Flat VRM ESL Cbulk ESR Cbulk C decap ESL Cdecap ESR Cdecap f 0 = 1 2π LC V = I Z peak Z peak = Z 0 Q Impedance vs. Frequency 20 mohms +6dB/Octave 1.5 Ohms 6 nh 100 nf ωl 1 ωc - 6dB/Octave 1 Amp AC Sweep Z 0 = L C Q = Z 0 R total Zpeak=1.5 Ohms Zo=250 mohms 25
E M S I M U L AT O R S C A N O P T I M I Z E L AY O U T F O R L O W L Loop Inductance + - L L increases with loop area CAP 26
D E C O U P L I N G I S R E Q U I R E D T O E X T E N D T H E P O W E R S U P P LY B A N D W I D T H PROBLEM The Load can make the Power Supply Control Loop go unstable 1 st Order SOLUTION Design for Flat Impedance at the output to keep V and I in phase and the feedback stable. Frequency Domain Power Supply Output Impedance Controlled f supply No Control High Z ωl Power Supply Simple R-L Model Time Domain Voltage and Current vs. Time R V R L Step Load Forced LOG SCALE LOG SCALE for time 27
D E S I G N I N G F O R F L AT I M P E D A N C E PROBLEM Find the decoupling capacitor that will maintain a Flat Z Load for the Power Supply 1 st Order SOLUTION Add Bulk Capacitor to maintain flat impedance V R L supply C bulk Z target C bulk = L supply 2 Z Target Frequency Domain Power Supply Output Impedance Time Domain Voltage and Current vs. Time f supply 1 ωl supply Flat Z Design ωc bulk Target Z Flat Z Load R-L Supply Power Supply Decoupling Ideal Bulk C Step Load Forced LOG SCALE LOG SCALE for time 28
PA R A L L E L R E S O N A N C E C A U S E S I M P E D A N C E P E A K VRM Control Frequency Domain Impedance at the Package Pin No PDN Decoupling Package/Die Decoupling Time Domain Voltage and Current vs. Time No PDN Decoupling Step Forced 29
I N C R E A S E S PA R T C O U N T T O R E A C H TA R G E T Z Frequency Domain Impedance at the Package Pin Low ESR 100 uf Capacitor Target Z Time Domain Voltage and Current vs. Time VRM Control Package/Die Decoupling Step Forced 30
F L AT Z = M A X I M U M S TA B I L I T Y A N D M I N I M U M R I P P L E Frequency Domain Impedance at the Package Pin Time Domain Voltage and Current vs. Time Flat PDN Decoupling Target Z VRM Control Package/Die Decoupling Step Forced 31
F O L L O W T H E R E T U R N PAT H T O S U C C E S S Ground is for potatoes and carrots, electrical circuits use a return path Bruce Archambeault EMC Consultant and IBM Distinguished Engineer Check for high current density constriction points. Control the impedance by engineering the return path. Minimize the inductance in the power delivery and return path. 32
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