5 SS Series Circuits 5.1 NTODUCTON Two types of current re redily ville to the consumer tody. One is direct current (dc), in which idelly the flow of chrge (current) does not chnge in mgnitude (or direction) with time. The other is sinusoidl lternting current (c), in which the flow of chrge is continully chnging in mgnitude (nd direction) with time. The next few chpters re n introduction to circuit nlysis purely from dc pproch. The methods nd concepts will e discussed in detil for direct current; when possile, short discussion will suffice to cover ny vritions we might encounter when we consider c in the lter chpters. The ttery of Fig. 5.1, y virtue of the potentil difference etween its terminls, hs the ility to cuse (or pressure ) chrge to flow through the simple circuit. The positive terminl ttrcts the electrons through the wire t the sme rte t which electrons re supplied y the negtive terminl. As long s the ttery is connected in the circuit nd mintins its terminl chrcteristics, the current (dc) through the circuit will not chnge in mgnitude or direction. Bttery (volts) conventionl electron = V = V FG. 5.1 ntroducing the sic components of n electric circuit. f we consider the wire to e n idel conductor (tht is, hving no opposition to flow), the potentil difference V cross the resistor will equl the pplied voltge of the ttery: V (volts) (volts).
130 SS CCUTS S For ll one-voltgesource dc circuits FG. 5.2 Defining the direction of conventionl flow for single-source dc circuits. V For ny comintion of voltge sources in the sme dc circuit FG. 5.3 Defining the polrity resulting from conventionl current through resistive element. The current is limited only y the resistor. The higher the resistnce, the less the current, nd conversely, s determined y Ohm s lw. By convention (s discussed in Chpter 2), the direction of conventionl current flow conventionl s shown in Fig. 5.1 is opposite to tht of electron flow ( electron ). Also, the uniform flow of chrge dicttes tht the direct current e the sme everywhere in the circuit. By following the direction of conventionl flow, we notice tht there is rise in potentil cross the ttery ( to ), nd drop in potentil cross the resistor ( to ). For single-voltge-source dc circuits, conventionl flow lwys psses from low potentil to high potentil when pssing through voltge source, s shown in Fig. 5.2. However, conventionl flow lwys psses from high to low potentil when pssing through resistor for ny numer of voltge sources in the sme circuit, s shown in Fig. 5.3. The circuit of Fig. 5.1 is the simplest possile configurtion. This chpter nd the chpters to follow will dd elements to the system in very specific mnner to introduce rnge of concepts tht will form mjor prt of the foundtion required to nlyze the most complex system. Be wre tht the lws, rules, nd so on, introduced in Chpters 5 nd 6 will e used throughout your studies of electricl, electronic, or computer systems. They will not e dropped for more dvnced set s you progress to more sophisticted mteril. t is therefore criticl tht the concepts e understood thoroughly nd tht the vrious procedures nd methods e pplied with confidence. Series circuit nd re not in series 3 FG. 5.4 Series circuit; sitution in which nd re not in series. c 5.2 SS CCUTS A circuit consists of ny numer of elements joined t terminl points, providing t lest one closed pth through which chrge cn flow. The circuit of Fig. 5.4 hs three elements joined t three terminl points (,, nd c) to provide closed pth for the current. Two elements re in series if 1. They hve only one terminl in common (i.e., one led of one is connected to only one led of the other). 2. The common point etween the two elements is not connected to nother current-crrying element. n Fig. 5.4, the resistors nd re in series ecuse they hve only point in common. The other ends of the resistors re connected elsewhere in the circuit. For the sme reson, the ttery nd resistor re in series (terminl in common), nd the resistor nd the ttery re in series (terminl c in common). Since ll the elements re in series, the network is clled series circuit. Two common exmples of series connections include the tying of smll pieces of rope together to form longer rope nd the connecting of pipes to get wter from one point to nother. f the circuit of Fig. 5.4 is modified such tht current-crrying resistor 3 is introduced, s shown in Fig. 5.4, the resistors nd re no longer in series due to violtion of numer 2 of the ove definition of series elements. The current is the sme through series elements. For the circuit of Fig. 5.4, therefore, the current through ech resistor is the sme s tht through the ttery. The fct tht the current is
S SS CCUTS 131 the sme through series elements is often used s pth to determine whether two elements re in series or to confirm conclusion. A rnch of circuit is ny portion of the circuit tht hs one or more elements in series. n Fig. 5.4, the resistor forms one rnch of the circuit, the resistor nother, nd the ttery third. The totl resistnce of series circuit is the sum of the resistnce levels. n Fig. 5.4, for exmple, the totl resistnce ( T ) is equl to. Note tht the totl resistnce is ctully the resistnce seen y the ttery s it looks into the series comintion of elements s shown in Fig. 5.5. n generl, to find the totl resistnce of N resistors in series, the following eqution is pplied: T 3... N (ohms, ) (5.1) Once the totl resistnce is known, the circuit of Fig. 5.4 cn e redrwn s shown in Fig. 5.6, clerly reveling tht the only resistnce the source sees is the totl resistnce. t is totlly unwre of how the elements re connected to estlish T. Once T is known, the current drwn from the source cn e determined using Ohm s lw, s follows: s T (mperes, A) (5.2) FG. 5.5 esistnce seen y source. s T T = Since is fixed, the mgnitude of the source current will e totlly dependent on the mgnitude of T. A lrger T will result in reltively smll vlue of s, while lesser vlues of T will result in incresed current levels. The fct tht the current is the sme through ech element of Fig. 5.4 permits direct clcultion of the voltge cross ech resistor using Ohm s lw; tht is, s Circuit equivlent FG. 5.6 eplcing the series resistors nd of Fig. 5.5 with the totl resistnce. V 1, V 2, V 3 3,..., V N N (volts, V) (5.3) The power delivered to ech resistor cn then e determined using ny one of three equtions s listed elow for : P 1 V 1 1 2 1 V 2 1 (wtts, W) (5.4) The power delivered y the source is P del (wtts, W) (5.5) The totl power delivered to resistive circuit is equl to the totl power dissipted y the resistive elements. Tht is, P del P 1 P 2 P 3... P N (5.6)
132 SS CCUTS S 20 V 1 T V 1 = 2 3 = 5 V 3 FG. 5.7 xmple 5.1. V 2 XAMPL 5.1. Find the totl resistnce for the series circuit of Fig. 5.7.. Clculte the source current s. c. Determine the voltges V 1, V 2, nd V 3. d. Clculte the power dissipted y,, nd 3. e. Determine the power delivered y the source, nd compre it to the sum of the power levels of prt (d). Solutions:. T 3 2 1 5 8 20 V. s 2.5 A T 8 c. V 1 (2.5 A)(2 ) 5 V V 2 (2.5 A)(1 ) 2.5 V V 3 3 (2.5 A)(5 ) 12.5 V d. P 1 V 1 1 (5 V)(2.5 A) 12.5 W P 2 2 2 (2.5 A) 2 (1 ) 6.25 W P 3 V 2 3/ 3 (12.5 V) 2 /5 31.25 W e. P del (20 V)(2.5 A) 50 W P del P 1 P 2 P 3 50 W 12.5 W 6.25 W 31.25 W 50 W 50 W (checks) To find the totl resistnce of N resistors of the sme vlue in series, simply multiply the vlue of one of the resistors y the numer in series; tht is, V 2 T N (5.7) = 7 = 4 50 V T 4 7 FG. 5.8 xmple 5.2. 3 7 XAMPL 5.2 Determine T,, nd V 2 for the circuit of Fig. 5.8. Solution: Note the current direction s estlished y the ttery nd the polrity of the voltge drops cross s determined y the current direction. Since 3 4, T N (3)(7 ) 4 21 4 25 50 V 2 A T 25 V 2 (2 A)(4 ) 8 V 4 k T = 12 k 3 = 6 ma 6 k xmples 5.1 nd 5.2 re strightforwrd sustitution-type prolems tht re reltively esy to solve with some prctice. xmple 5.3, however, is evidence of nother type of prolem tht requires firm grsp of the fundmentl equtions nd n ility to identify which eqution to use first. The est preprtion for this type of exercise is simply to work through s mny prolems of this kind s possile. FG. 5.9 xmple 5.3. XAMPL 5.3 Given T nd, clculte nd for the circuit of Fig. 5.9.
S KCHHOFF S VOLTAG LAW 133 Solution: T 3 12 k 4 k 6 k 12 k 10 k 2 k T (6 10 3 A)(12 10 3 ) 72 V 5.3 VOLTAG SOUCS N SS Voltge sources cn e connected in series, s shown in Fig. 5.10, to increse or decrese the totl voltge pplied to system. The net voltge is determined simply y summing the sources with the sme polrity nd sutrcting the totl of the sources with the opposite pressure. The net polrity is the polrity of the lrger sum. n Fig. 5.10, for exmple, the sources re ll pressuring current to the right, so the net voltge is T 1 2 3 10 V 6 V 2 V 18 V s shown in the figure. n Fig. 5.10, however, the greter pressure is to the left, with net voltge of T 2 3 1 9 V 3 V 4 V 8 V nd the polrity shown in the figure. 1 10 V 1 2 6 V 3 2 V 4 V 2 9 V 3 3 V T 18 V T 8 V FG. 5.10 educing series dc voltge sources to single source. Germn (Königserg, Berlin) (182487) Physicist Professor of Physics, University of Heidelerg 5.4 KCHHOFF S VOLTAG LAW Note Fig. 5.11. Kirchhoff s voltge lw (KVL) sttes tht the lgeric sum of the potentil rises nd drops round closed loop (or pth) is zero. A closed loop is ny continuous pth tht leves point in one direction nd returns to tht sme point from nother direction without leving the circuit. n Fig. 5.12, y following the current, we cn trce continuous pth tht leves point through nd returns through without leving the circuit. Therefore, cd is closed loop. For us to e le to pply Kirchhoff s voltge lw, the summtion of potentil rises nd drops must e mde in one direction round the closed loop. For uniformity, the clockwise (CW) direction will e used throughout the text for ll pplictions of Kirchhoff s voltge lw. Be wre, however, tht the sme result will e otined if the counterclockwise (CCW) direction is chosen nd the lw pplied correctly. A plus sign is ssigned to potentil rise ( to ), nd minus sign to potentil drop ( to ). f we follow the current in Fig. 5.12 from point, we first encounter potentil drop V 1 ( to ) cross nd then nother potentil drop V 2 cross. Continuing through the voltge source, we hve potentil rise ( to ) efore returning to point. n symolic form, where Σ represents summtion, the closed loop, nd V the potentil drops nd rises, we hve V 0 (Kirchhoff s voltge lw in symolic form) (5.8) d V 1 KVL Courtesy of the Smithsonin nstitution Photo No. 58,283 Although contriutor to numer of res in the physics domin, he is est known for his work in the electricl re with his definition of the reltionships etween the currents nd voltges of network in 1847. Did extensive reserch with Germn chemist oert Bunsen (developed the Bunsen urner), resulting in the discovery of the importnt elements of cesium nd ruidium. FG. 5.11 Gustv oert Kirchhoff. FG. 5.12 Applying Kirchhoff s voltge lw to series dc circuit. V 2 c
134 SS CCUTS S which for the circuit of Fig. 5.12 yields (clockwise direction, following the current nd strting t point d): V 1 V 2 0 or V 1 V 2 reveling tht the pplied voltge of series circuit equls the sum of the voltge drops cross the series elements. Kirchhoff s voltge lw cn lso e stted in the following form: V rises V drops (5.9) which in words sttes tht the sum of the rises round closed loop must equl the sum of the drops in potentil. The text will emphsize the use of q. (5.8), however. f the loop were tken in the counterclockwise direction strting t point, the following would result: V 0 V 2 V 1 0 V x 12 V 8 V FG. 5.13 Demonstrtion tht voltge cn exist etween two points not connected y currentcrrying conductor. or, s efore, V 1 V 2 The ppliction of Kirchhoff s voltge lw need not follow pth tht includes current-crrying elements. For exmple, in Fig. 5.13 there is difference in potentil etween points nd, even though the two points re not connected y current-crrying element. Appliction of Kirchhoff s voltge lw round the closed loop will result in difference in potentil of 4 V etween the two points. Tht is, using the clockwise direction: 12 V V x 8 V 0 nd V x 4 V XAMPL 5.4 Determine the unknown voltges for the networks of Fig. 5.14. V 1 4.2 V 12 V 6 V 1 16 V 2 9 V 32 V V x 3 14 V FG. 5.14 xmple 5.4. Solution: When pplying Kirchhoff s voltge lw, e sure to concentrte on the polrities of the voltge rise or drop rther thn on the
S KCHHOFF S VOLTAG LAW 135 type of element. n other words, do not tret voltge drop cross resistive element differently from voltge drop cross source. f the polrity dicttes tht drop hs occurred, tht is the importnt fct when pplying the lw. n Fig. 5.14, for instnce, if we choose the clockwise direction, we will find tht there is drop cross the resistors nd nd drop cross the source 2. All will therefore hve minus sign when Kirchhoff s voltge lw is pplied. Appliction of Kirchhoff s voltge lw to the circuit of Fig. 5.14 in the clockwise direction will result in nd 1 V 1 V 2 2 0 V 1 1 V 2 2 16 V 4.2 V 9 V 2.8 V The result clerly indictes tht there ws no need to know the vlues of the resistors or the current to determine the unknown voltge. Sufficient informtion ws crried y the other voltge levels to permit determintion of the unknown. n Fig. 5.14 the unknown voltge is not cross current-crrying element. However, s indicted in the prgrphs ove, Kirchhoff s voltge lw is not limited to current-crrying elements. n this cse there re two possile pths for finding the unknown. Using the clockwise pth, including the voltge source, will result in nd V 1 V x 0 V x V 1 32 V 12 V 20 V Using the clockwise direction for the other loop involving nd 3 will result in nd mtching the result ove. V x V 2 V 3 0 V x V 2 V 3 6 V 14 V 20 V XAMPL 5.5 Find V 1 nd V 2 for the network of Fig. 5.15. Solution: For pth 1, strting t point in clockwise direction: 25 V V 1 15 V 0 nd V 1 40 V For pth 2, strting t point in clockwise direction: V 2 20 V 0 nd V 2 20 V The minus sign simply indictes tht the ctul polrities of the potentil difference re opposite the ssumed polrity indicted in Fig. 5.15. The next exmple will emphsize the fct tht when we re pplying Kirchhoff s voltge lw, it is the polrities of the voltge rise or drop tht re the importnt prmeters, nd not the type of element involved. 25 V 1 15 V V 1 2 20 V FG. 5.15 xmple 5.5. V 2
136 SS CCUTS S XAMPL 5.6 Using Kirchhoff s voltge lw, determine the unknown voltges for the network of Fig. 5.16. 40 V 60 V V x 6 V 14 V V x 30 V 2 V FG. 5.16 xmple 5.6. Solution: Note in ech circuit tht there re vrious polrities cross the unknown elements since they cn contin ny mixture of components. Applying Kirchhoff s voltge lw to the network of Fig. 5.16 in the clockwise direction will result in 60 V 40 V V x 30 V 0 nd V x 60 V 30 V 40 V 90 V 40 V 50 V n Fig. 5.16 the polrity of the unknown voltge is not provided. n such cses, mke n ssumption out the polrity, nd pply Kirchhoff s voltge lw s efore. f the result hs plus sign, the ssumed polrity ws correct. f it hs minus sign, the mgnitude is correct, ut the ssumed polrity hs to e reversed. n this cse if we ssume to e positive nd to e negtive, n ppliction of Kirchhoff s voltge lw in the clockwise direction will result in 6 V 14 V V x 2 V 0 nd V x 20 V 2 V 18 V Since the result is negtive, we know tht should e negtive nd should e positive, ut the mgnitude of 18 V is correct. 20 V T V 1 V 2 4 6 XAMPL 5.7 For the circuit of Fig. 5.17:. Find T.. Find. c. Find V 1 nd V 2. d. Find the power to the 4- nd 6- resistors. e. Find the power delivered y the ttery, nd compre it to tht dissipted y the 4- nd 6- resistors comined. f. Verify Kirchhoff s voltge lw (clockwise direction). FG. 5.17 xmple 5.7. Solutions:. T 4 6 10 20 V. 2 A T 10
S NTCHANGNG SS LMNTS 137 c. V 1 (2 A)(4 ) 8 V V 2 (2 A)(6 ) 12 V V 2 1 (8 V) 2 64 d. P 4 16 W 1 4 4 P 6 2 (2 A) 2 (6 ) (4)(6) 24 W e. P (20 V)(2 A) 40 W P P 4 P 6 40 W 16 W 24 W 40 W 40 W (checks) f. V V 1 V 2 0 V 1 V 2 20 V 8 V 12 V 20 V 20 V (checks) V 3 = 15 V 3 54 V 7 V 2 V 1 = 18 V FG. 5.18 xmple 5.8. XAMPL 5.8 For the circuit of Fig. 5.18:. Determine V 2 using Kirchhoff s voltge lw.. Determine. c. Find nd 3. Solutions:. Kirchhoff s voltge lw (clockwise direction): 10 75 V V 2 5 3 20 V 3 V 2 V 1 0 or V 1 V 2 V 3 nd V 2 V 1 V 3 54 V 18 V 15 V 21 V V 2 21 V. 3 A 2 7 V 1 18 V c. 6 3 A V 3 15 V 3 5 3 A FG. 5.19 Series dc circuit with elements to e interchnged. 10 20 3 75 V 5 V 2 5.5 NTCHANGNG SS LMNTS The elements of series circuit cn e interchnged without ffecting the totl resistnce, current, or power to ech element. For instnce, the network of Fig. 5.19 cn e redrwn s shown in Fig. 5.20 without ffecting or V 2. The totl resistnce T is 35 in oth cses, nd 70 V/35 2 A. The voltge V 2 (2 A)(5 ) 10 V for oth configurtions. XAMPL 5.9 Determine nd the voltge cross the 7- resistor for the network of Fig. 5.21. Solution: The network is redrwn in Fig. 5.22. T (2)(4 ) 7 15 37.5 V 2.5 A T 15 V 7 (2.5 A)(7 ) 17.5 V 50 V FG. 5.20 Circuit of Fig. 5.19 with nd 3 interchnged. 4 12.5 V 4 FG. 5.21 xmple 5.9. V 7
138 SS CCUTS S 4 4 4 4 12.5 V 50 V 7 V 37.5 V 7 V 20 V 3 6 3 1 12 V 6 V 2 V FG. 5.23 eveling how the voltge will divide cross series resistive elements. 6 M 12 V 20 V 3 M 6 V 3 1 M 2 V FG. 5.24 The rtio of the resistive vlues determines the voltge division of series dc circuit. 1 M V 1 >> V 2 or V 3 100 V 1 k V 2 = 10V 3 3 100 V 3 >> or 3 FG. 5.25 The lrgest of the series resistive elements will cpture the mjor shre of the pplied voltge. FG. 5.22 edrwing the circuit of Fig. 5.21. 5.6 VOLTAG DVD UL n series circuit, the voltge cross the resistive elements will divide s the mgnitude of the resistnce levels. For exmple, the voltges cross the resistive elements of Fig. 5.23 re provided. The lrgest resistor of 6 cptures the ulk of the pplied voltge, while the smllest resistor 3 hs the lest. Note in ddition tht, since the resistnce level of is 6 times tht of 3, the voltge cross is 6 times tht of 3. The fct tht the resistnce level of is 3 times tht of results in three times the voltge cross. Finlly, since is twice, the voltge cross is twice tht of. n generl, therefore, the voltge cross series resistors will hve the sme rtio s their resistnce levels. t is prticulrly interesting to note tht, if the resistnce levels of ll the resistors of Fig. 5.23 re incresed y the sme mount, s shown in Fig. 5.24, the voltge levels will ll remin the sme. n other words, even though the resistnce levels were incresed y fctor of 1 million, the voltge rtios remin the sme. Clerly, therefore, it is the rtio of resistor vlues tht counts when it comes to voltge division nd not the reltive mgnitude of ll the resistors. The current level of the network will e severely ffected y the chnge in resistnce level from Fig. 5.23 to Fig. 5.24, ut the voltge levels will remin the sme. Bsed on the ove, first glnce t the series network of Fig. 5.25 should suggest tht the mjor prt of the pplied voltge will pper cross the 1-M resistor nd very little cross the 100- resistor. n fct, 1 M (1000)1 k (10,000)100, reveling tht V 1 1000V 2 10,000V 3. Solving for the current nd then the three voltge levels will result in 100 V 99.89 ma T 1,001,100 nd V 1 (99.89 ma)(1 M ) 99.89 V V 2 (99.89 ma)(1 k ) 99.89 mv 0.09989 V V 3 3 (99.89 ma)(100 ) 9.989 mv 0.009989 V clerly sustntiting the ove conclusions. For the future, therefore, use this pproch to estimte the shre of the input voltge cross series elements to ct s check ginst the ctul clcultions or to simply otin n estimte with minimum of effort.
S VOLTAG DVD UL 139 n the ove discussion the current ws determined efore the voltges of the network were determined. There is, however, method referred to s the voltge divider rule (VD) tht permits determining the voltge levels without first finding the current. The rule cn e derived y nlyzing the network of Fig. 5.26. T nd Applying Ohm s lw: V 1 T T with V 2 Note tht the formt for V 1 nd V 2 is T T T T FG. 5.26 Developing the voltge divider rule. V 1 V 2 V x x T (voltge divider rule) (5.10) where V x is the voltge cross x, is the impressed voltge cross the series elements, nd T is the totl resistnce of the series circuit. n words, the voltge divider rule sttes tht the voltge cross resistor in series circuit is equl to the vlue of tht resistor times the totl impressed voltge cross the series elements divided y the totl resistnce of the series elements. V 1 XAMPL 5.10 Determine the voltge V 1 for the network of Fig. 5.27. Solution: q. (5.10): V 1 1 (20 )(64 V) 1280 V 16 V 20 60 80 T 64 V 20 60 XAMPL 5.11 Using the voltge divider rule, determine the voltges V 1 nd V 3 for the series circuit of Fig. 5.28. Solution: V 1 (2 k )(45 V) T 2 k 5 k 8 k (2 10 3 )(45 V) 90 V 6 V 15 10 3 15 V 3 3 (8 k )(45 V) 5 k T 360 V 15 24 V (2 k )(45 V) 15 k (8 10 3 )(45 V) 15 10 3 FG. 5.27 xmple 5.10. 2 k V 1 45 V 5 k 3 8 k V 3 V' The rule cn e extended to the voltge cross two or more series elements if the resistnce in the numertor of q. (5.10) is expnded to FG. 5.28 xmple 5.11.
140 SS CCUTS S include the totl resistnce of the series elements tht the voltge is to e found cross ( ); tht is, V T (volts) (5.11) XAMPL 5.12 Determine the voltge V in Fig. 5.28 cross resistors nd. Solution: (2 k 5 k )(45 V) (7 k )(45 V) V 21 V T 15 k 15 k There is lso no need for the voltge in the eqution to e the source voltge of the network. For exmple, if V is the totl voltge cross numer of series elements such s those shown in Fig. 5.29, then (2 )(27 V) 54 V V 2 6 V 4 2 3 9 V = 27 V 4 2 3 V 2 FG. 5.29 The totl voltge cross series elements need not e n independent voltge source. 4 ma 20 V V 1 V 2 XAMPL 5.13 Design the voltge divider of Fig. 5.30 such tht V 1 4V 2. Solution: The totl resistnce is defined y T 20 V 4 ma 5 k FG. 5.30 xmple 5.13. Since V 1 4V 2, 4 Thus T 4 5 nd nd 5 5 k 1 k 4 4 k 5.7 NOTATON Nottion will ply n incresingly importnt role in the nlysis to follow. t is importnt, therefore, tht we egin to exmine the nottion used throughout the industry.
S NOTATON 141 Voltge Sources nd Ground xcept for few specil cses, electricl nd electronic systems re grounded for reference nd sfety purposes. The symol for the ground connection ppers in Fig. 5.31 with its defined potentil level zero volts. None of the circuits discussed thus fr hve contined the ground connection. f Fig. 5.4 were redrwn with grounded supply, it might pper s shown in Fig. 5.32,, or (c). n ny cse, it is understood tht the negtive terminl of the ttery nd the ottom of the resistor re t ground potentil. Although Figure 5.32(c) shows 0 V FG. 5.31 Ground potentil. FG. 5.32 Three wys to sketch the sme series dc circuit. (c) no connection etween the two grounds, it is recognized tht such connection exists for the continuous flow of chrge. f 12 V, then point is 12 V positive with respect to ground potentil, nd 12 V exist cross the series comintion of resistors nd. f voltmeter plced from point to ground reds 4 V, then the voltge cross is 4 V, with the higher potentil t point. On lrge schemtics where spce is t premium nd clrity is importnt, voltge sources my e indicted s shown in Figs. 5.33 nd 5.34 rther thn s illustrted in Figs. 5.33 nd 5.34. n ddition, potentil levels my e indicted s in Fig. 5.35, to permit rpid check of the potentil levels t vrious points in network with respect to ground to ensure tht the system is operting properly. 12 V 12 V 5 V 5 V FG. 5.33 eplcing the specil nottion for dc voltge source with the stndrd symol. 25 V FG. 5.34 eplcing the nottion for negtive dc supply with the stndrd nottion. 3 Doule-Suscript Nottion The fct tht voltge is n cross vrile nd exists etween two points hs resulted in doule-suscript nottion tht defines the first FG. 5.35 The expected voltge level t prticulr point in network of the system is functioning properly.
142 SS CCUTS S suscript s the higher potentil. n Fig. 5.36, the two points tht define the voltge cross the resistor re denoted y nd. Since is the first suscript for V, point must hve higher potentil thn point if V is to hve positive vlue. f, in fct, point is t higher potentil thn point, V will hve negtive vlue, s indicted in Fig. 5.36. V (V = ) V (V = ) FG. 5.36 Defining the sign for doule-suscript nottion. n summry: The doule-suscript nottion V specifies point s the higher potentil. f this is not the cse, negtive sign must e ssocited with the mgnitude of V. n other words, the voltge V is the voltge t point with respect to (w.r.t.) point. = 10 V V 6 10 V 4 V V 4 FG. 5.37 Defining the use of single-suscript nottion for voltge levels. Single-Suscript Nottion f point of the nottion V is specified s ground potentil (zero volts), then single-suscript nottion cn e employed tht provides the voltge t point with respect to ground. n Fig. 5.37, V is the voltge from point to ground. n this cse it is oviously 10 V since it is right cross the source voltge. The voltge V is the voltge from point to ground. Becuse it is directly cross the 4- resistor, V 4 V. n summry: The single-suscript nottion V specifies the voltge t point with respect to ground (zero volts). f the voltge is less thn zero volts, negtive sign must e ssocited with the mgnitude of V. Generl Comments A prticulrly useful reltionship cn now e estlished tht will hve extensive pplictions in the nlysis of electronic circuits. For the ove nottionl stndrds, the following reltionship exists: V V V (5.12) n other words, if the voltge t points nd is known with respect to ground, then the voltge V cn e determined using q. (5.12). n Fig. 5.37, for exmple, V V V 10 V 4 V 6 V
S NOTATON 143 XAMPL 5.14 Find the voltge V for the conditions of Fig. 5.38. Solution: Applying q. (5.12): V V V 16 V 20 V 4 V V = 16 V V = 20 V FG. 5.38 xmple 5.14. Note the negtive sign to reflect the fct tht point is t higher potentil thn point. XAMPL 5.15 Find the voltge V for the configurtion of Fig. 5.39. Solution: Applying q. (5.12): V V = 5 V V = 4 V FG. 5.39 xmple 5.15. nd V V V V V V 5 V 4 V 9 V XAMPL 5.16 Find the voltge V for the configurtion of Fig. 5.40. Solution: Applying q. (5.12): V V V 20 V ( 15 V) 20 V 15 V 35 V V = 20 V 10 k V = 15 V V FG. 5.40 xmple 5.16. Note in xmple 5.16 the cre tht must e tken with the signs when pplying the eqution. The voltge is dropping from high level of 20 V to negtive voltge of 15 V. As shown in Fig. 5.41, this represents drop in voltge of 35 V. n some wys it s like going from positive checking lnce of $20 to owing $15; the totl expenditure is $35. V = 20 V V Gnd (0 V) V = 35 V XAMPL 5.17 Find the voltges V, V c, nd V c for the network of Fig. 5.42. V = 15 V 1 = 10 V 4 V V 2 20 V c FG. 5.41 The impct of positive nd negtive voltges on the totl voltge drop. V FG. 5.42 xmple 5.17. 10 V 4 V 6 V Solution: Strting t ground potentil (zero volts), we proceed through rise of 10 V to rech point nd then pss through drop in potentil of 4 V to point. The result is tht the meter will red V 10 V 4 V 6 V s clerly demonstrted y Fig. 5.43. Gnd (0 V) FG. 5.43 Determining V using the defined voltge levels.
144 SS CCUTS S f we then proceed to point c, there is n dditionl drop of 20 V, resulting in V c V 20 V 6 V 20 V 14 V s shown in Fig. 5.44. V 2 = 35 V 25 V 10 V 4 V V c 1 = 19 V V c 20 FG. 5.45 xmple 5.18. Gnd (0 V) 20 V c V c = 14 V V c = 24 V FG. 5.44 eview of the potentil levels for the circuit of Fig. 5.42. 35 V 54 V Gnd (0 V) The voltge V c cn e otined using q. (5.12) or y simply referring to Fig. 5.44: V c V V c 10 V ( 14 V) 24 V 19 V FG. 5.46 Determining the totl voltge drop cross the resistive elements of Fig. 5.45. 25 2 20 c 1 19 V 35 V FG. 5.47 edrwing the circuit of Fig. 5.45 using stndrd dc voltge supply symols. XAMPL 5.18 Determine V, V c, nd V c for the network of Fig. 5.45. Solution: There re two wys to pproch this prolem. The first is to sketch the digrm of Fig. 5.46 nd note tht there is 54-V drop cross the series resistors nd. The current cn then e determined using Ohm s lw nd the voltge levels s follows: 54 V 1.2 A 45 V (1.2 A)(25 ) 30 V V c (1.2 A)(20 ) 24 V V c 1 19 V The other pproch is to redrw the network s shown in Fig. 5.47 to clerly estlish the iding effect of 1 nd 2 nd then solve the resulting series circuit. 1 2 19 V 35 V 54 V 1.2 A 45 45 T nd V 30 V V c 24 V V c 19 V
S NTNAL SSTANC OF VOLTAG SOUCS 145 XAMPL 5.19 Using the voltge divider rule, determine the voltges V 1 nd V 2 of Fig. 5.48. Solution: edrwing the network with the stndrd ttery symol will result in the network of Fig. 5.49. Applying the voltge divider rule, (4 )(24 V) V 1 16 V 1 4 2 (2 )(24 V) V 2 8 V 1 4 2 XAMPL 5.20 For the network of Fig. 5.50: = 24 V V 1 V 2 4 2 FG. 5.48 xmple 5.19. V 2 V 2 3 10 V V 3 c 5 24 V 4 V1 2 V2. Clculte V.. Determine V. c. Clculte V c. Solutions:. Voltge divider rule: V T. Voltge divider rule: FG. 5.50 xmple 5.20. (2 )(10 V) 2 3 5 2 V V V 2 V 3 ( 3 ) (3 5 )(10 V) 8 V T 10 or V V V V 10 V 2 V 8 V c. V c ground potentil 0 V FG. 5.49 Circuit of Fig. 5.48 redrwn. 5.8 NTNAL SSTANC OF VOLTAG SOUCS very source of voltge, whether genertor, ttery, or lortory supply s shown in Fig. 5.51, will hve some internl resistnce. The equivlent circuit of ny source of voltge will therefore pper s shown in Fig. 5.51. n this section, we will exmine the effect of the internl resistnce on the output voltge so tht ny unexpected chnges in terminl chrcteristics cn e explined. n ll the circuit nlyses to this point, the idel voltge source (no internl resistnce) ws used [see Fig. 5.52]. The idel voltge source hs no internl resistnce nd n output voltge of volts with no lod or full lod. n the prcticl cse [Fig. 5.52], where we con-
146 SS CCUTS S POW SUPPLY int FG. 5.51 Sources of dc voltge; equivlent circuit. L int L = 0 V NL = int L L V L L (c) FG. 5.52 Voltge source: idel, int 0 ; determining V NL ; (c) determining int. sider the effects of the internl resistnce, the output voltge will e volts only when no-lod ( L 0) conditions exist. When lod is connected [Fig. 5.52(c)], the output voltge of the voltge source will decrese due to the voltge drop cross the internl resistnce. By pplying Kirchhoff s voltge lw round the indicted loop of Fig. 5.52(c), we otin L int V L 0 or, since V NL we hve V NL L int V L 0 nd V L V NL L int (5.13) f the vlue of int is not ville, it cn e found y first solving for int in the eqution just derived for V L ; tht is, int V NL V L V NL LL L L L NL nd int V L (5.14) A plot of the output voltge versus current ppers in Fig. 5.53 for the dc genertor hving the circuit representtion of Fig. 5.51. Note tht ny increse in lod demnd, strting t ny level, cuses n dditionl drop in terminl voltge due to the incresing loss in potentil cross the internl resistnce. At mximum current, denoted y FL, the L
S NTNAL SSTANC OF VOLTAG SOUCS 147 V L V L 120 V 100 V L 0 1 2 3 4 5 6 7 8 9 10 FL (A) FG. 5.53 V L versus L for dc genertor with int 2. voltge cross the internl resistnce is V int FL int (10 A)(2 ) 20 V, nd the terminl voltge hs dropped to 100 V significnt difference when you cn idelly expect 120-V genertor to provide the full 120 V if you sty elow the listed full-lod current. ventully, if the lod current were permitted to increse without limit, the voltge cross the internl resistnce would equl the supply voltge, nd the terminl voltge would e zero. The lrger the internl resistnce, the steeper is the slope of the chrcteristics of Fig. 5.53. n fct, for ny chosen intervl of voltge or current, the mgnitude of the internl resistnce is given y int D VL D L (5.15) For the chosen intervl of 57 A (D L 2A)onFig. 5.53, DV L is 4V,nd int DV L D L 4V 2A 2. A direct consequence of the loss in output voltge is loss in power delivered to the lod. Multiplying oth sides of q. (5.13) y the current L in the circuit, we otin L V L L V NL 2 L int Power Power output Power loss in to lod y ttery the form of het (5.16) XAMPL 5.21 Before lod is pplied, the terminl voltge of the power supply of Fig. 5.54 is set to 40 V. When lod of 500 is ttched, s shown in Fig. 5.54, the terminl voltge drops to 38.5 V. Wht hppened to the reminder of the no-lod voltge, nd wht is the internl resistnce of the source? Solution: The difference of 40 V 38.5 V 1.5 V now ppers cross the internl resistnce of the source. The lod current is 38.5 V/0.5 k 77 ma. Applying q. (5.14), int V NL 40 V L 77 ma L 0.5 k 519.48 500 19.48 POW SUPPLY 40 V (no lod) POW SUPPLY L FG. 5.54 xmple 5.21. L 500 36 V
148 SS CCUTS S = 30 V (V NL ) int = 2 Ω FG. 5.55 xmple 5.22. V L 13 Ω XAMPL 5.22 The ttery of Fig. 5.55 hs n internl resistnce of 2. Find the voltge V L nd the power lost to the internl resistnce if the pplied lod is 13- resistor. Solution: 30V 30 V L 2 A 2 13 15 V L V NL L int 30 V (2 A)(2 ) 26 V P lost 2 L int (2 A) 2 (2 ) (4)(2) 8 W Procedures for mesuring int will e descried in Section 5.10. 5.9 VOLTAG GULATON V L For ny supply, idel conditions dictte tht for the rnge of lod demnd ( L ), the terminl voltge remin fixed in mgnitude. n other words, if supply is set for 12 V, it is desirle tht it mintin this terminl voltge, even though the current demnd on the supply my vry. A mesure of how close supply will come to idel conditions is given y the voltge regultion chrcteristic. By definition, the voltge regultion (V) of supply etween the limits of full-lod nd no-lod conditions (Fig. 5.56) is given y the following: V NL V FL del chrcteristic Voltge regultion (V)% V NL V FL 100% V FL (5.17) 0 FL L FG. 5.56 Defining voltge regultion. For idel conditions, V FL V NL nd V% 0. Therefore, the smller the voltge regultion, the less the vrition in terminl voltge with chnge in lod. t cn e shown with short derivtion tht the voltge regultion is lso given y int V% 100% L (5.18) n other words, the smller the internl resistnce for the sme lod, the smller the regultion nd the more idel the output. XAMPL 5.23 Clculte the voltge regultion of supply hving the chrcteristics of Fig. 5.53. Solution: V% V NL V FL 120 V 100 V 100% 100% V 100 V FL 20 100% 20% 100
S MASUMNT TCHNQUS 149 XAMPL 5.24 Determine the voltge regultion of the supply of Fig. 5.54. Solution: V% int 19.48 100% 100% 3.9% 500 L 5.10 MASUMNT TCHNQUS n Chpter 2, it ws noted tht mmeters re inserted in the rnch in which the current is to e mesured. We now relize tht such condition specifies tht mmeters re plced in series with the rnch in which the current is to e mesured s shown in Fig. 5.57. f the mmeter is to hve miniml impct on the ehvior of the network, its resistnce should e very smll (idelly zero ohms) compred to the other series elements of the rnch such s the resistor of Fig. 5.57. f the meter resistnce pproches or exceeds 10% of, it will nturlly hve significnt impct on the current level it is mesuring. t is lso noteworthy tht the resistnces of the seprte current scles of the sme meter re usully not the sme. n fct, the meter resistnce normlly increses with decresing current levels. However, for the mjority of situtions one cn simply ssume tht the internl mmeter resistnce is smll enough compred to the other circuit elements tht it cn e ignored. For n up-scle (nlog meter) or positive (digitl meter) reding, n mmeter must e connected with current entering the positive terminl of the meter nd leving the negtive terminl, s shown in Fig. 5.58. Since most meters employ red led for the positive terminl nd lck led for the negtive, simply ensure tht current enters the red led nd leves the lck one. Voltmeters re lwys hooked up cross the element for which the voltge is to e determined. An up-scle or positive reding on voltmeter is otined y eing sure tht the positive terminl (red led) is connected to the point of higher potentil nd the negtive terminl (lck led) is connected to the lower potentil, s shown in Fig. 5.59. m FG. 5.57 Series connection of n mmeter. ed led Blck led FG. 5.58 Connecting n mmeter for n up-scle (positive) reding. ed led V V Blck led ed led V Blck led FG. 5.59 Hooking up voltmeter to otin n up-scle (positive) reding. For the doule-suscript nottion, lwys hook up the red led to the first suscript nd the lck led to the second; tht is, to mesure the voltge V in Fig. 5.60, connect the red led to point nd the lck
150 SS CCUTS S led to point. For single-suscript nottion, hook up the red led to the point of interest nd the lck led to ground, s shown in Fig. 5.60 for V nd V. V ed led Blck led ed led V 3 ed led V Blck led Blck led FG. 5.60 Mesuring voltges with doule- nd single-suscript nottion. The internl resistnce of supply cnnot e mesured with n ohmmeter due to the voltge present. However, the no-lod voltge cn e mesured y simply hooking up the voltmeter s shown in Fig. 5.61. Do not e concerned out the pprent pth for current tht the meter seems to provide y completing the circuit. The internl resistnce of the meter is usully sufficiently high to ensure tht the resulting current is so smll tht it cn e ignored. (Voltmeter loding effects will e discussed in detil in Section 6.9.) An mmeter could then e plced directly cross the supply, s shown in Fig. 5.61, to mesure the short-circuit current SC nd int s determined y Ohm s lw: int NL / SC. However, since the internl resistnce of the supply my e very low, performing the mesurement could result in high current levels tht could dmge the meter nd supply nd possily cuse dngerous side effects. The setup of Fig. 5.61 is therefore not suggested. A etter pproch would e to pply resistive lod tht will result in supply current of out hlf the mximum rted vlue nd mesure the terminl voltge. Then use q. (5.14). 0 V int V NL = V int sc Not recommended!! FG. 5.61 Mesuring the no-lod voltge ; mesuring the short-circuit current.
S APPLCATONS 151 5.11 APPLCATONS Holidy Lights n recent yers the smll linking holidy lights with s mny s 50 to 100 uls on string hve ecome very populr [see Fig. 5.62]. Although holidy lights cn e connected in series or prllel (to e descried in the next chpter), the smller linking light sets re normlly connected in series. t is reltively esy to determine if the lights re connected in series. f one wire enters nd leves the ul csing, they re in series. f two wires enter nd leve, they re proly in prllel. Normlly, when uls re connected in series, if one should urn out (the filment reks nd the circuit opens), ll the uls will go out since the current pth hs een interrupted. However, the uls of Fig. 5.62 re specilly designed, s shown in Fig. 5.62, to permit current to continue to flow to the other uls when the filment urns out. At the se of ech ul there is fuse link wrpped round the two posts holding the filment. The fuse link of soft conducting metl ppers to e touching the two verticl posts, ut in fct coting on the posts or fuse link prevents conduction from one to the other under norml operting conditions. f filment should urn out nd crete n open circuit etween the posts, the current through the ul nd other uls would e interrupted if it were not for the fuse link. At the instnt ul opens up, current through the circuit is zero, nd the full 120 V from the outlet will pper cross the d ul. This high voltge from post to post of single ul is of sufficient potentil difference to estlish current through the insulting cotings nd spot-weld the fuse link to the two posts. The circuit is gin complete, nd ll the uls will light except the one with the ctivted fuse link. Keep in mind, however, tht ech time ul urns out, there will e more voltge cross the other uls of the circuit, mking them urn righter. ventully, if too mny uls urn out, the voltge will rech point where the other uls will urn out in rpid succession. The result is tht one must replce urned-out uls t the erliest opportunity. The uls of Fig. 5.62 re rted 2.5 V t 0.2 A or 200 ma. Since there re 50 uls in series, the totl voltge cross the uls will e 50 2.5 V or 125 V which mtches the voltge ville t the typicl Bul filment Bul filment Contct point Motion when heted Current pth Bul se Fuselink (few wrps of thin coted conductive wire) Bul se Flsher Unit Bi-metl structure Stndrd ul FG. 5.62 Holidy lights: 50-unit set; ul construction.
152 SS CCUTS S home outlet. Since the uls re in series, the current through ech ul will e 200 ma. The power rting of ech ul is therefore P V (2.5 V)(0.2 A) 0.5 W with totl wttge demnd of 50 0.5 W 25 W. A schemtic representtion for the set of Fig. 5.62 is provided in Fig. 5.63. Note tht only one flsher unit is required. Since the uls re in series, when the flsher unit interrupts the current flow, it will turn off ll the uls. As shown in Fig. 5.62, the flsher unit incorportes imetl therml switch tht will open when heted to preset level y the current. As soon s it opens, it will egin to cool down nd close gin so tht current cn return to the uls. t will then het up gin, open up, nd repet the entire process. The result is n on-ndoff ction tht cretes the flshing pttern we re so fmilir with. Nturlly, in colder climte (for exmple, outside in the snow nd ice), it will initilly tke longer to het up, so the flshing pttern will e reduced t first; ut in time s the uls wrm up, the frequency will increse. The mnufcturer specifies tht no more thn six sets should e connected together. The first question tht then rises is, How cn sets e connected together, end to end, without reducing the voltge cross ech ul nd mking ll the lights dimmer? f you look closely t the 125 V c Flsher 50 uls 2.5V2.5V 2.5V 2.5V2.5V 2.5V = 200 ma 200 ma 200 ma 125 V c c Three wires 50 uls stlish prllel connection of 50-ul strings c Plug Buls in series Connector Plug supply = 1.2 A 1 A 0.8 A 3(0.2 A) = 0.6 A 125 V c 0.2 A 0.2 A 0.2 A 6 sets supply c c c c (c) FG. 5.63 Single-set wiring digrm; specil wiring rrngement; (c) redrwn schemtic; (d) specil plug nd flsher unit. (d)
S APPLCATONS 153 wiring, you will find tht since the uls re connected in series, there is one wire to ech ul with dditionl wires from plug to plug. Why would they need two dditionl wires if the uls re connected in series? The nswer lies in the fct tht when ech set is connected together, they will ctully e in prllel (to e discussed in the next chpter) y unique wiring rrngement shown in Fig. 5.63 nd redrwn in Fig. 5.63(c) to clerly show the prllel rrngement. Note tht the top line is the hot line to ll the connected sets, nd the ottom line is the return, neutrl, or ground line for ll the sets. nside the plug of Fig. 5.63(d) the hot line nd return re connected to ech set, with the connections to the metl spdes of the plug s shown in Fig. 5.63. We will find in the next chpter tht the current drwn from the wll outlet for prllel lods is the sum of the current to ech rnch. The result, s shown in Fig. 5.63(c), is tht the current drwn from the supply is 6 200 ma 1.2 A, nd the totl wttge for ll six sets is the product of the pplied voltge nd the source current or (120 V)(1.2 A) 144 W with 144 W/6 24 W per set. Microwve Oven Series circuits cn e very effective in the design of sfety equipment. Although we ll recognize the usefulness of the microwve oven, it cn e quite dngerous if the door is not closed or seled properly. t is not enough to test the closure t only one point round the door ecuse the door my e ent or distorted from continul use, nd lekge could result t some point distnt from the test point. One common sfety rrngement ppers in Fig. 5.64. Note tht mgnetic switches re locted ll round the door, with the mgnet in the door itself nd the mgnetic door switch in the min frme. Mgnetic switches re simply switches where the mgnet drws mgnetic conducting r etween two contcts to complete the circuit somewht reveled y the symol Series sfety switches Mgnetic door switches Microwve power unit Mgnets Mgnets FG. 5.64 Series sfety switches in microwve oven.
154 SS CCUTS S for the device in the circuit digrm of Fig. 5.64. Since the mgnetic switches re ll in series, they must ll e closed to complete the circuit nd turn on the power unit. f the door is sufficiently out of shpe to prevent single mgnet from getting close enough to the switching mechnism, the circuit will not e complete, nd the power cnnot e turned on. Within the control unit of the power supply, either the series circuit completes circuit for opertion or sensing current is estlished nd monitored tht controls the system opertion. Series Alrm Circuit Door switch Window foil Mgnetic switch Sensors 5 ma Sensing rely FG. 5.65 Series lrm circuit. To ell circuit 5 V @ 5mA 1 kω 5 V Power supply The circuit of Fig. 5.65 is simple lrm circuit. Note tht every element of the design is in series configurtion. The power supply is 5-V dc supply tht cn e provided through design similr to tht of Fig. 2.31, dc ttery, or comintion of n c nd dc supply tht ensures tht the ttery will lwys e t full chrge. f ll the sensors re closed, current of 5 ma will result ecuse of the terminl lod of the rely of out 1 k. Tht current energizes the rely nd mintins n off position for the lrm. However, if ny of the sensors re opened, the current will e interrupted, the rely will let go, nd the lrm circuit will e energized. With reltively short wires nd few sensors, the system should work well since the voltge drop cross ech will e miniml. However, since the lrm wire is usully reltively thin, resulting in mesurle resistnce level, if the wire to the sensors is too long, sufficient voltge drop could occur cross the line, reducing the voltge cross the rely to point where the lrm fils to operte properly. Thus, wire length is fctor tht must e considered if series configurtion is used. Proper sensitivity to the length of the line should remove ny concerns out its opertion. An improved design will e descried in Chpter 8. s V 1 6 Ω 54 V V 1 V 2 7 Ω FG. 5.66 Series dc network to e nlyzed using PSpice. V 2 V 3 3 5 Ω 5.12 COMPUT ANALYSS PSpice n Section 4.9, the sic procedure for setting up the PSpice folder nd running the progrm were presented. Becuse of the detil provided in tht section, you should review it efore proceeding with this exmple. Becuse this is only the second exmple using PSpice, some detil will e provided, ut not t the level of Section 4.9. The circuit to e investigted ppers in Fig. 5.66. Since the PSpice folder ws estlished in Section 4.9, there is no need to repet the process here it is immeditely ville. Doule-clicking on the Orcd Lite dition icon will generte the Orcd Cpture-Lite dition window. A new project is then initited y selecting the Crete document key t the top left of the screen (it looks like pge with str in the upper left corner). The result is the New Project dilog ox in which SeriesDC is inserted s the Nme. The Anlog or Mixed A/D is lredy selected, nd C:\PSpice ppers s the Loction only the Nme hd to e entered! Click OK, nd the Crete PSpice Project dilog ox will pper. Select Crete lnk project, click OK, nd the working windows will pper. Gring the left edge of the SCHMATC1:PAG1 window will llow you to move it to the right so tht you cn see oth screens. Clicking the sign in the Project Mnger window will llow you to set the sequence down to PAG1. f you prefer to chnge the nme of the SCHMATC1, just select it
S COMPUT ANALYSS 155 nd right-click on the mouse. A listing will pper in which enme is n option; selecting it will result in enme Schemtic dilog ox in which SeriesDC cn e entered. n Fig. 5.67 it ws left s SCHMATC1. Now this next step is importnt! f the toolr on the right edge does not pper, e sure to doule-click on PAG1 in the Project Mnger window, or select the Schemtic Window. When the heding of the Schemtic Window is drk lue, the toolr will pper. To strt uilding the circuit, select Plce prt key (the second one down) to otin the Plce Prt dilog ox. Note tht now the SOUC lirry is lredy in plce in the Lirry list from the efforts of Chpter 4; it does not hve to e reinstlled. Selecting SOUC will result in the list of sources under Prt List, nd VDC cn e selected. Click OK, nd the cursor cn put it in plce with single left click. ight-click nd select nd Mode to end the process since the network hs only one source. One more left click nd the source is in plce. Now the Plce prt key isselected gin, followed y ANALOG lirry to find the resistor. Once the resistor hs een selected, n OK will plce it next to the cursor on the screen. This time, since three resistors need to e plced, there is no need to go to nd Mode etween depositing ech. Simply click one in plce, then the next, nd finlly the third. Then right-click to end the process with nd Mode. Finlly, GND must e dded y selecting the pproprite key nd selecting 0/SOUC in the Plce Ground dilog ox. Click OK, nd plce the ground s shown in Fig. 5.67. The elements must now e connected using the Plce wire key to otin the crosshir on the screen. Strt t the top of the voltge source with left click, nd drw the wire, left-clicking it t every 90 turn. When wire is connected from one element to nother, move on to the next connection to e mde there is no need to go nd Mode etween FG. 5.67 Applying PSpice to series dc circuit.
156 SS CCUTS S connections. Now the lels nd vlues hve to e set y doule-clicking on ech prmeter to otin Disply Properties dilog ox. Since the dilog ox ppers with the quntity of interest in lue ckground, simply type in the desired lel or vlue, followed y OK. The network is now complete nd redy to e nlyzed. Before simultion, select the V,, nd W in the toolr t the top of the window to ensure tht the voltges, currents, nd power re displyed on the screen. To simulte, select the New Simultion Profile key (which ppers s dt sheet on the second toolr down with str in the top left corner) to otin the New Simultion dilog ox. nter Bis Point for dc solution under Nme, nd hit the Crete key. A Simultion Settings-Bis Point dilog ox will pper in which Anlysis is selected nd Bis Point is found under the Anlysis type heding. Click OK, nd then select the un PSpice key (the lue rrow) to initite the simultion. xit the resulting screen, nd the disply of Fig. 5.67 will result. The current is clerly 3 A for the circuit with 15 V cross 3, nd 36 V from point etween nd to ground. The voltge cross is 36 V 15 V 21 V, nd the voltge cross is 54 V 36 V 18 V. The power supplied or dissipted y ech element is lso listed. There is no question tht the results of Fig. 5.67 include very nice disply of voltge, current, nd power levels. lectronics Workench (WB) Since this is only the second circuit to e constructed using WB, detiled list of steps will e included s review. ssentilly, however, the entire circuit of Fig. 5.68 cn e drwn using simply the construction informtion introduced in Chpter 4. After you hve selected the Multisim 2001 icon, Multisim- Circuit 1 window will pper redy to ccept the circuit elements. Select the Sources key t the top of the left toolr, nd Sources prts in will pper with 30 options. Selecting the top option will plce the GOUND on the screen of Fig. 5.68, nd selecting the third option down will result in DC VOLTAG SOUC. The resistors re otined y choosing the second key down on the left toolr clled the Bsic key. The result is 25 options in which SSTO VTUAL is selected. We must return to the SSTO VTUAL key to plce ech resistor on the screen. However, ech new resistor is numered in sequence, lthough they re ll given the defult vlue of 1 k. ememer from the discussion of Chpter 4 tht you should dd the meters efore connecting the elements together ecuse the meters tke spce nd must e properly oriented. The current will e determined y the XMM1 mmeter nd the voltges y XMM2 through XMM5. Of prticulr importnce, note tht in WB the meters re connected in exctly the sme wy they would e plced in n ctive circuit in the lortory. Ammeters re in series with the rnch in which the current is to e determined, nd voltmeters re connected etween the two points of interest (cross resistors). n ddition, for positive redings, mmeters re connected so tht conventionl current enters the positive terminl, nd voltmeters re connected so tht the point of higher potentil is connected to the positive terminl. The meter settings re mde y doule-clicking on the meter symol on the schemtic. n ech cse, V or hd to e chosen, ut the hori-
S COMPUT ANALYSS 157 FG. 5.68 Applying lectronics Workench to series dc circuit. zontl line for dc nlysis is the sme for ech. Agin, the Set key cn e selected to see wht it controls, ut the defult vlues of meter input resistnce levels will e fine for ll the nlyses descried in this text. Leve the meters on the screen so tht the vrious voltges nd the current level will e displyed fter the simultion. ecll from Chpter 4 tht elements cn e moved y simply clicking on ech schemtic symol nd drgging it to the desired loction. The sme is true for lels nd vlues. Lels nd vlues re set y douleclicking on the lel or vlue nd entering your preference. Click OK, nd they will pper chnged on the schemtic. There is no need to first select specil key to connect the elements. Simply ring the cursor to the strting point to generte the smll circle nd crosshir. Click on the strting point, nd follow the desired pth to the next connection pth. When in loction, click gin, nd the line will pper. All connecting lines cn mke 90 turns. However, you cnnot follow digonl pth from one point to nother. To remove ny element, lel, or line, simply click on the quntity to otin the four-squre ctive sttus, nd select the Delete key orthe scissors key on the top menu r. Before simulting, e sure tht the Simulte Switch is visile y selecting View-Show Simulte Switch. Then select the 1 option on the switch, nd the nlysis will egin. The results ppering in Fig. 5.68 verify those otined using PSpice nd the longhnd solution. C We will now turn to the C lnguge nd review progrm designed to perform the sme nlysis just performed using PSpice nd WB. As noted in erlier chpters, do not expect to understnd ll the detils of how the progrm ws written nd why specific pths were tken.