Preamplifier in 0.5µm CMOS

A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University

OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling and Optimization Circuit Layout and Measurement Summary

SYSTEM OVERVIEW Var. gain amp Decision circuit Optical fiber Photo diode Preamp AGC Digital data Clock synthesizer Pre-amp design is critical Challenge: CMOS implementation

CMOS VS. GAAS Factor GaAs CMOS Performance Excellent Sufficient for up to low GHz Integration Photodiode with Pre-amp Analog and Digital Cost High Low Photodiode in GaAs Flip-chip techniques can reduce parasitics at the GaAs to CMOS transition Parasitic coupling from digital to analog is a challenge for integration

TRANSIMPEDANCE AMPLIFIER R f C d C g A + Photo diode Transimpedance amplifier

ω 3dB = 1 R in C in = (A+1) R f (C d +C g ) A MAX = k ω T ω where 3dB (k 1) A R f (C d +C g )

TRANSIMPEDANCE LIMIT R f,max kω T ω 3dB2 (C d +C g ) Desire maximum R f for sensitivity, stability and high gain Need to circumvent this limit

CIRCUMVENTING THE TRANSIMPEDANCE LIMIT R f C d + C g A Photo diode Common-gate stage Shunt-peaked transimpedance stage Decouple photodiode from the transimpedance stage with common-gate stage Increase gain-bandwidth product by shunt-peaking

SHUNT-PEAKED AMPLIFIER Common Source Amplifier Shunt-peaked Amplifier V dd V dd L R R v out v out v in C v in C Bandwidth enhancement using zeros No additional power dissipation

SMALL SIGNAL MODELS Common Source Amplifier Shunt-peaked Amplifier v out v out R g m v in R C g m v in L C One pole v out v in (ω) = g mr 1+jωRC One zero, two poles v out v in (ω) = g m(r+jωl) 1+jωRC ω 2 LC

MAGNITUDE RESPONSE 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0 0.2 No peaking Optimum group delay Maximally flat Maximum bandwidth 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Normalized frequency

PHASE RESPONSE Phase 0 10 20 30 40 50 60 70 80 90 No peaking Optimum group delay Maximally flat Maximum bandwidth 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Normalized frequency

FREQUENCY RESPONSE R v out Two time constants: τ C = RC, τ L = L/R g m v in L C Ratio determines performance: m = τ L τc = L R 2 C Factor (m) Normalized ω 3dB Response 0 1.00 No shunt peaking 0.32 1.60 Optimum group delay 0.41 1.72 Maximally flat 0.71 1.85 Maximum bandwidth

ON-CHIP SHUNT PEAKING :PREVIOUS WORK Bond-wire inductor V dd Maximum Q on-chip V dd L bondwire L C L R s C bondpad R v out R v out v in C d C load v in C d C load C g C g Large C bondpad Limited L bondwire Coupling issues Large C L Large area Limited L

ON-CHIP SHUNT PEAKING: NEW V dd L R s (R R s ) C L v out Work with inductor parasitics R s is not an issue (now part of load resistance) Inductor Q is not relevant Minimize area and C L v in C d C load L determined by R, C load, C L and C d C g

MODELING CHALLENGE Simultaneous optimization of active and passive components 3-D field solvers are inconvenient { Numerically expensive and cumbersome { Good for verification but not for design Scalable, analytical models { Design guidelines and explore trade-offs { Circuit design and optimization

INDUCTOR MODELING port 1 R si Two port (without PGS) C s C ox L C si R s C si C ox R si port 2 C L = C ox + C s One port (with PGS) L R s substrate Simple expressions for R s, C ox and C s Patterned ground shield (PGS) eliminates R si and C si NEED simple, accurate expression for inductance!

CURRENT SHEET APPROACH OD = (1 + ρ)ad w AD ni s ρad = nw +(n 1)s Reduce complexity by 4n 2 Use symmetry Derive simple expression using GMD, AMD and AMSD

GMD, AMD AND AMSD w 2 w 2 w 2 <x 1,x 2 < w 2 l I x 1 x 2 ln (GMD) = ln x 1 + x 2 =lnw 1.5 AMD = x 1 + x 2 = w 3 AMSD 2 = (x 1 + x 2 ) 2 = w2 6 L = µl 2π [ ln ( = µl 2π 2l GMD [ ln ( 2l w ) 1+ AMD l ] AMSD2 4l 2 ) ] +0.5+ w 3l w2 24l 2

INDUCTANCE EXPRESSSION s w ID OD AD = 0.5(OD + ID) ρ = OD ID OD+ID ρad = nw +(n 1)s AD L = 2µn2 AD π [ ( ln ) ] 2.067 +0.176ρ +0.125ρ 2 ρ

INDUCTANCE EXPRESSSION % Inductors exceeding abs. error 100 80 60 40 20 0 0 1 2 3 4 5 6 7 % Absolute error Min Max L(nH) 0.1 70 OD(µm) 100 400 n 1 20 s/w 0.02 3 ρ 0.03 0.95 Verified by measurements (75) and 3-D field solver simulations (19,000)

TRANSIMPEDANCE STAGE V dd L R s C L Input current drive (R R s ) Cascode stage R f C d v out C load On-chip shunt-peaking Feedback i in C in C g

DESIGN METHODOLOGY 1. Design and optimize transimpedance stage without shunt peaking 2. Transistor current determines conductor width, w 3. Lithography sets spacing, s 4. Choose n and AD to realize desired L while minimizing parasitic capacitance and area 5. Increase transimpedance resistance, R f

OPTIMIZATION VIA GEOMETRIC PROGRAMMING Simultaneous optimization of active and passive components Global Optimum or Proof of Infeasibility DAC99, Session 54.3 (June 24, 1999): Optimization of Inductor Circuits via Geometric Programming Maria del Mar Hershenson, Sunderarajan S. Mohan Stephen P. Boyd and Thomas H. Lee

EXPERIMENTAL VERIFICATION OF INDUCTOR 1000 Impedance (Ω) 800 600 400 200 real(zl) measured real(zl) predicted imag(zl) measured imag(zl) predicted 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) OD = 180µm w =3.2µm s =2.1µm n =11.75 L meas =20.5nH L pred =20.3nH

COMMON-GATE STAGE V dd Decouple sensitive feedback node from external capacitances Realize higher transimpedance Extra power Additional noise terms Photo diode Common-gate stage Shunt-peaked transimpedance stage Junction capacitances degrade noise at high frequency

DIFFERENTIAL PREAMPLIFIER

TRANSIMPEDANCE BANDWIDTH 1800 Transmpedance (Ω) 1600 1400 1200 1000 800 C PD = 100fF C PD = 300fF C PD = 500fF C PD = 700fF 0 0.2 0.4 0.6 0.8 1.0 1.2 frequency (GHz)

INPUT REFERRED CURRENT NOISE DENSITY 40 30 γ =2/3 γ=4/3 γ=2 pa/ Hz 20 10 0 0 0.5 1.0 1.5 2.0 frequency (GHz)

EYE DIAGRAM 1.6 Gb/s 120 80 40 mv mv 25 20 15 10 5 0 5 10 15 20 25 6.2 6.4 6.6 ns6.8 7.0 7.2 2.1 Gb/s 0 40 80 120 6.0 6.2 6.4ns 6.6 6.8 7.0 S. S. Mohan, A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS, CICC

PERFORMANCE SUMMARY Transimpedance (small-signal) Bandwidth (3dB) Max. photodiode capacitance Max. input current Simulated input noise current Max. output voltage swing 1600Ω (differential) 800Ω (single-ended) 1.2GHz 0.6pF 1.0mA 0.6µA 1.0V pp (differential) (50Ω load at each output) 0.5V pp (single-ended) Power consumption 115mW (core) 110mW (50Ω driver) Die area 0.6mm 2 Technology 0.5µm CMOS

CONTRIBUTIONS Shunt-peaking with optimized on-chip inductor Simple accurate expression for inductance Common-gate input stage CMOS implementation of differential preamplifier

ACKNOWLEDGMENTS IBM fellowship support Rockwell International Dr. Christopher Hull Dr. Paramjit Singh Prof. L. Kazovsky and Dr. Allen Lu Dr. C. Patrick Yue, Dr. Derek Shaeffer, Dr. Arvin Shahani Maria del Mar Hershenson and Dr. Ali Hajimiri