Chapter 3 Spring 2012 4 th Semester Mechatronics SZABIST, Karachi 2 Course Support humera.rafique@szabist.edu.pk Office: 100 Campus (404) Official: ZABdesk https://sites.google.com/site/zabistmechatronics/home/spring-2012/ecd ebooks: https://sites.google.com/site/zabistmechatronics/home/ebooks 1
Chapter Contents 3 J Small Signal Model Fixed Bias Configuration Self Bias Configuration Voltage Divider Configuration Common Gate Configuration Source Follower Configuration D and E type MOS Configurations Amplifier Network Design Cacade Configuration Applications 4 Small Signal Model 2
Small Signal Model 5 s Advantages: Excellent voltage gain High input impedance Low-power consumption Good frequency range Small Signal Model 6 Transconductance: The relationship of a change in I D to the corresponding change inv GS : g m I = V D GS 3
Small Signal Model 7 Mathematical Definition of g m : Where V GS =0V Where g m D G S D SS g m 1 VP g m 0 I = V 2I V = V 2I D S S = V g m = g m 0 1 g m = g m 0 1 P V V G S P V V G S P G S P Small Signal Model 8 Example 8-1: Determine the magnitude of g m for a J with I DSS = 8 ma and V P = 4 V at the following dc bias points: a. V GS = 0.5 V b. V GS = 1.5 V c. V GS = 2.5 V 4
Small Signal Model 9 Example 8-1: Determine the magnitude of g m for a J with I DSS = 8 ma and V P = 4 V at the following dc bias points: a. V GS = 0.5 V b. V GS = 1.5 V c. V GS = 2.5 V Small Signal Model 10 Example 8-2: For the J of Ex 8-1, find: a. g m (max) b. g m at each point of Ex 8-1 5
Small Signal Model 11 g m vs V GS : When V GS = V P, g m is zero When V GS = 0V, g m is maximum Small Signal Model 12 Example 8-3: Using J of Ex 8-1, plot g m vs V GS. 6
Small Signal Model 13 Example 8-3: Using J of Ex 8-1, plot g m vs V GS. g 2 I DSS m = V 1 P 2 I DSS g m 0 = V P V V GS P Small Signal Model 14 Effect of I D on g m : Shockley s equation: 1 V V GS P = I I D DSS V gm = gm0 1 V GS P g m = g m0 I I D DSS 7
Small Signal Model 15 Plot of of I D vs g m : g m = g m0 I I D DSS g = m 0 2 I V DSS P g m g mo I D I DSS 0.707 g mo I DSS /2 0.5 g mo I DSS /4 0 0 ma Small Signal Model 16 Example 8-4: Plot g m vs I D of Ex 8-1: 8
Example 8-4: Plot g m vs I D of Ex 8-1: Small Signal Model 17 G m I D g mo I DSS 0.707 g mo I DSS /2 0.5 g mo I DSS /4 0 0 ma Small Signal Model 18 J Z i : input impedance, Z i is sufficiently large. Usually in the range of 10 9 Ω (1000MΩ) Zi ( ) = Ω J Z o : output impedance, Zo is similar in magnitude to conventional BJTs. Output impedance appears as y os with units of µs where 1 Z o = rd = yos VDS r d = VGS = constant ID 9
Small Signal Model 19 Defining r d using J characteristics: Small Signal Model 20 Example 8.5: Determine the output impedance for the given J for V GS = 0 V and 2V at V DS = 8V. 10
Small Signal Model 21 J AC Equivalent: Small Signal Model 22 Example 8-6: Given y fs = 3.8 ms and y os = 20 µs. Sketch the ac equivalent model: Ω 11
23 J Configurations J Configurations 24 J Configurations: 1. Fixed bias (Common Source) 2. Self bias 3. Voltage-Divider bias 4. Common Gate 5. Source-Follower (Common Drain) Important Parameters of AC Analysis: 1. Input impedance 2. Output impedance 3. Voltage Gain 12
25 Fixed Bias Configuration J Fixed Bias 26 1. Fixed Bias Configuration (Common Source): 13
J Fixed Bias 27 Determining Z i : Substituting the J ac equivalent circuit unit into the fixed bias network J Fixed Bias 28 Determining Z i : ( ) Z = R i G Redrawn network 14
J Fixed Bias 29 Determining Z o : Set Vi = 0 Z Z o ( ) = r R o d D ( ) if r = R d 10R D D J Fixed Bias 30 Determining A V : A = V ( V ) m ( d D ) ( V ) ( ) v o i = -g r R A = V v o i = -g R when r 10R m D d D V = -g V V ( r R ) o m gs d D gs = V i ( ) V = -g V r R o m i d D Phase reversal 15
J Fixed Bias 31 Example 8-7: AC analysis of the fixed-bias configuration of Ex 7-1: If y os = 40 µs, than, determine: a. g m b. r d c. Z i d. Z o e. A v f. A v (ignoring the effects of r d ) I DQ =5.625mA; V GSQ = 2V y OS =40µS 32 Self Bias Configuration 16
J Self Bias 33 J Self Bias: Bypassed R S J Self Bias 34 J Self Bias: Fixed bias network following the substitution of the J ac equivalent 17
J Self Bias 35 J Self Bias: Redrawn network J Self Bias 36 J Self Bias: Unbypassed R S Z i = R Z G V o o = = I o R D 18
J Self Bias 37 J Self Bias: Unbypassed R S Including the effects of r d in the self bias J configuration J Self Bias 38 J Self Bias: Unbypassed R S R S 1 + g m RS + r d Z O = R RS R D 1 + g m RS + + rd rd D Z O R D A v V O g m R D g m R D = = V RS + R D 1+ g 1 g R m R + S + r i m S d 19
J Self Bias 39 Example 8-8: AC Analysis the self-bias configuration of Ex 7-2: If y os = 20 µs, then, determine: a. g m b. r d c. Z i d. Z o (with and without the effects of r d ). Compare the results. e. A v (with and without the effects of r d ). Compare the results. J Self Bias 40 Computer Analysis: 20
41 Voltage Divider Configuration J Voltage Divider Bias 42 Voltage Divider Bias: 21
J Voltage Divider Bias 43 Voltage Divider Bias: J Voltage Divider Bias 44 Voltage Divider Bias: Z = R R i 1 2 Z o R D A V = g R o v m D V i 22
45 Common-Gate Configuration J Common-Gate 46 Common Gate Configuration: 23
J Common-Gate 47 Common Gate Configuration: J Common-Gate 48 Common Gate Configuration: Z ' i R D 1 + r d 1 g m + rd Z i R Z S o 1 g R m D A R g v D m 24
J Common-Gate 49 Example 8-9: Determine: a. g m b. r d c. Z i d. Z o (with and without the effects of r d ). Compare the results. a. V o (with and without the effects of r d ). Compare the results. 50 Source-Follower (Common-Drain) Configuration 25
J Source-Follower (CD) 51 Source-Follower (CD): J Source-Follower (CD) 52 Source-Follower (CD): 26
J Source-Follower (CD) 53 Common-Follower (CD): J Source-Follower (CD) 54 Common-Follower (CD): Determining Z o 27
J Source-Follower (CD) 55 Common-Follower (CD): Z i = R G Z o R S 1 g m Av g m RS 1 + g R m S J Source-Follower (CD) 56 Example 8-10: AC analysis: V GSQ = 2.86 V and I DQ = 4.56 ma. Determine: a. g m b. R d c. Z i d. Z o with and without r d. Compare results. e. A v with and without r d. Compare results. 28
57 Depletion-Type MOSs MOS Configurations 58 MOS Configurations: D-MOS: 1. Voltage Divider E-MOS: 1. Drain Feedback 2. Voltage Divider 29
59 D-MOS D-MOS Configurations 60 D-MOS Equivalent Model: 30
D-MOS Configurations 61 Example 8-11: AC analysis (Ex 7-8): V GSQ = 0.36 V and I DQ = 7.6 ma. Determine: a. g m and compare to g mo. b. r d c. Z i d. Z o e. A v f. Sketch the ac equivalent D-MOS Configurations 62 Example 8-11: 31
63 E-MOS E-MOS Configurations 64 Equivalent Circuit: 32
65 E-MOS Drain-Feedback E-MOS Configurations 66 Drain Feedback: 33
E-MOS Configurations 67 Drain Feedback: E-MOS Configurations 68 Drain Feedback: Determining Z o 34
E-MOS Configurations 69 Drain Feedback: A v = g m (R F r d R D ) A v = g m R D E-MOS Configurations 70 Example 8-12: The E-MOS of Fig. 8-41 was analyzed in Example 7.11, with the result that k = 0.24 x 10 3 A/V 2, V GSQ = 6.4 V, and I DQ = 2.75 ma. Determine gm. a) Find r d. b) Calculate Z i with and without r d. Compare results. c) Find Z o with and without r d. Compare results. d) Find A v with and without r d. Compare results. 35
71 E-MOS Voltage Divider E-MOS Configurations 72 Voltage Divider: 36
E-MOS Configurations 73 Voltage Divider: E-MOS Configurations 74 Voltage Divider: 37
75 Designing Amplifier Network Amplifier Network Designing 76 Example 8-13: Design the fixed-bias network of Fig. 8-44 to have an ac gain of 10. That is determine the value of R D. 38
Amplifier Network Designing 77 Example 8-14: With a relatively high level of g m, select the values of R D and R S for the given network, that will result in a gain of 8. For the device V GSQ = ¼ V P. Amplifier Network Designing 78 Example 8-15: With a relatively high level of g m, select the values of R D and R S for the given network, that will result in a gain of 8. For the device V GSQ = ¼ V P. Now bypass capacitor has been removed. 39
Summary Table 79 Summary Table 80 40
Summary Table 81 Summary Table 82 41
83 Effect of R L and R sig R L and R sig 84 Effect of R L and R sig :. 42
R L and R sig 85 Effect of R L and R sig : R L and R sig 86 Effect of R L and R sig :. 43
87 Cascade Configuration Cascade Configuration 88 Cascade Configuration: V i1 A v1 V O1 =V i2 A v2 V O2 A = A... 1A 2 v v v 44
Cascade Configuration 89 Cascade Configuration: Cascade Configuration 90 Example 8-16: Calculate the dc bias, voltage gain, input impedance, output impedance and resulting output voltage for the cascade amplifier shown in Fig. 8.49. Calculate the load voltage if a 10-k load is connected across the output. 45
Cascade Configuration 91 Example 8-17: For the cascade amplifier of Fig. 8-50, use the dc bias calculated in Example 8-15 and 8-16 to calculate the input impedance, output impedance, voltage gain, and resulting output voltage. 92 Practical Applications 46
Practical Applications 93 1. Three channel audio mixer Practical Applications 94 2. Phase Shift network 47
Home Task 95 Reading: 1. Summary 2. Equations 3. Computer analysis Problems: 1. Sec 8.2: (odd) 2. Sec 8.3: 17,18 3. Sec 8.4: 19,21 4. Sec 8.5:23,25 5. Sec 8.6: 27,29 6. Sec 8.7: 31 7. Sec 8.8: 33,35,37 8. Sec 8.10: 39,41 9. Sec 8.11: 43 10. Sec 8.12: 45 11. Sec 8.14: 47 12. Sec 8.15: 49 Refernces 96 1. Bolestad 2. Paynter CH 13 48