Lecture 11: MOS Transistor Prof. Niknejad
Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout I-V Curve
MOS Capacitor Gate (n + poly) Body (p-type substrate) ε s = 11.7ε 0 0 x Oxide (SiO 2 ) ε = 3.9ε 0 Very Thin! t ~ 1nm MOS = Metal Oxide Silicon Sandwich of conductors separated by an insulator Metal is more commonly a heavily doped polysilicon layer n + or p + layer NMOS p-type substrate, PMOS n-type substrate
Accumulation: V GB < V FB Q = C ( V V ) G GB FB ρ( x) V GB < V FB + Q B = Q G ++++++++++++++++++ Body (p-type substrate) φ( x) Essentially a parallel plate capacitor Capacitance is determined by ide thickness:
Depletion: V FB <V GB < V T V GB > V + + + + + + + + + + FB + Body (p-type substrate) Q = qn X ( V ) B a d GB Q ( V ) = Q G GB B ρ( x) φ( x) t Positive charge on gate terminates on negative charges in depletion region Potential drop across the ide and depletion region Charge has a square-root dependence on applied bias
Inversion V GB = V T + + + + + + + + + + + Body (p-type substrate) φ s ρ( x) φ( x) t xdep qφs kt s = i = a n n e N The surface potential increases to a point where the electron density at the surface equals the background ion density At this point, the depletion region stops growing and the extra charge is provided by the inversion charge at surface
Threshold Voltage The threshold voltage is defined as the gate-body voltage that causes the surface to change from p-type to n-type For this condition, the surface potential has to equal the negative of the p-type potential Apply KCL around loop: VGS = VFB + V + VBS φs = VBS = 2φp ε s V = E t = t E ε s qnaxdep qn 2 ( 2 ) a 2ε qna φ s p Es = = φ s = εs εs qna εs 1 VTn = VFB 2φ p + 2 qε sna( 2 φp ) C V GB = V T + + V BS Gate (n + poly) + V
Inversion Stops Depletion A simple apprimation is to assume that once inversion happens, the depletion region stops growing This is a good assumption since the inversion charge is an exponential function of the surface potential Under this condition: Q ( V ) Q G Tn B,max Q ( V ) = C ( V V ) Q G GB GB Tn B,max
Q-V Curve for MOS Capacitor Q G depletion inversion Q B,max Q ( V ) N GB accumulation V FB V Tn V ( ) GB V In accumulation, the charge is simply proportional to the applies gate-body bias In inversion, the same is true In depletion, the charge grows slower since the voltage is applied over a depletion region
Numerical Example MOS Capacitor with p-type substrate: t = 20nm Calculate flat-band: N a Calculate threshold voltage: = 5 10 cm 16 3 V = ( φ φ ) = (550 ( 402)) = 0.95V FB n + C p ε t = = 13 3.45 10 F/cm -6 2 10 cm 1 VTn = VFB 2φ p + 2 qε sna ( 2 φp) C V Tn 19 12 16 2 1.6 10 1.04 10 5 10 2 0.4 =.95 2( 0.4) + = 0.52V C
Num Example: Electric Field in Oxide Apply a gate-to-body voltage: V GB = 2.5 < V FB Device is in accumulation The entire voltage drop is across the ide: E V VGB + φ + φ n p 2.5 + 0.55 ( 0.4) V = = = = 8 10 t t 5 6 2 10 cm The charge in the substrate (body) consist of holes: Q = C ( V V ) = 2.67 10 C/cm B GB FB 7 2
Numerical Example: Depletion Region In inversion, what s the depletion region width and charge? VB,max = φs φp = φp φp = 2φp = 0.8V V B,max 1 qn a = 2 ε s X 2 d,max X d,max 2ε V s B,max = = qn a 144nm Q,max = qn X,max = 1.15 10 C/cm B a d 7 2
MOS CV Curve Q G C C C Q ( V ) N GB Q B,max V ( ) GB V V GB V FB V Tn V FB V Tn Small-signal capacitance is slope of Q-V curve Capacitance is linear in accumulation and inversion Capacitance is depletion region is smallest Capacitance is non-linear in depletion
C-V Curve Equivalent Circuits C C C dep C ε s CdepC Cdep = C C Ctot = = = xdep Cdep + C Cdep ε s t 1+ 1+ C ε x dep In accumulation mode the capacitance is just due to the voltage drop across t In inversion the incremental charge comes from the inversion layer (depletion region stops growing). In depletion region, the voltage drop is across the ide and the depletion region
MOSFET Cross Section gate body source drain diffusion regions p+ n+ n+ L p-type substrate Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four terminal device The body is usually grounded (or at a DC potential) For ICs, the body contact is at surface
MOSFET Layout B S G D contact B S G D poly gate p+ n+ n+ L x j W p-type substrate L Planar process: complete structure can be specified by a 2D layout Design engineer can control the transistor width W and L Process engineer controls t, N a, x j, etc.
PMOS & NMOS B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j p-type substrate n-type substrate NMOS PMOS A MOSFET by any other name is still a MOSFET: NMOS, PMOS, nmos, pmos NFET, PFET IGFET Other flavors: JFET, MESFET CMOS technology: The ability to fabricated NMOS and PMOS devices simultaneously
CMOS B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j n-type well NMOS PMOS p-type substrate Complementary MOS: Both P and N type devices Create a n-type body in a p-type substrate through compensation. This new region is called a well. To isolate the PMOS from the NMOS, the well must be reverse biased (pn junction)
Circuit Symbols The symbols with the arrows are typically used in analog applications The body contact is often not shown The source/drain can switch depending on how the device is biased (the device has inherent symmetry)
Observed Behavior: I D -V GS I DS I DS V DS V GS Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearly V T V GS
Observed Behavior: I D -V DS IDS / k VGS = 4V non-linear resistor region constant current I DS V DS resistor region VGS = 3V V GS VGS = 2V For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) V DS
Linear Region Current V GS p+ NMOS > V Tn S n+ n+ p-type G Inversion layer channel 100mV If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drain D VDS x y
MOSFET Linear Region The current in this channel is given by I = Wv Q DS y N The charge proportional to the voltage applied across the ide over threshold Q = C ( V V ) N GS Tn I = Wv C ( V V ) DS y GS Tn If the channel is uniform density, only drift current flows v y = µ ne DS y Ey = V L W I = DS nc ( VGS VTn ) VDS VGS > VTn L µ V 100mV DS
MOSFET: Variable Resistor Notice that in the linear region, the current is proportional to the voltage I = W C ( V V ) V L µ DS n GS Tn DS Can define a voltage-dependent resistor R eq VDS 1 L L = = = R ( VGS ) I µ C ( V V ) W W DS n GS Tn This is a nice variable resistor, electronically tunable!