MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste and Harris & Principles of CMOS LSI Design By Neil E. Weste and Kamran Eshraghian Durga Misra ECE Dept., NJIT, Newark, NJ LSI Design I Lect. 3 1 MOS Symbols and Characteristics MOS majority carrier device Carriers: e in nmos,, holes in pmos t channel threshold voltage (cuts off for voltages < t ) Transistor gate, source, drain all have capacitance I = C (Δ/( /Δt) ) => Δt = (C/I) Δ Capacitance and current determine speed Derive currentvoltage (I) relationships LSI Design I Lect. 3 2 nmos Enhancement Transistor Moderately doped p type Si substrate 2 Heavily doped n + regions LSI Design I Lect. 3 3
I vs. Plots Enhancement and depletion transistors CMOS uses only enhancement transistors nmos uses both LSI Design I Lect. 3 4 Materials and Dopants SiO 2 low loss, high dielectric strength High gate fields are possible n type impurities: P, As, Sb p type impurities: B, Al, Ga,, In LSI Design I Lect. 3 5 Accumulation, Depletion & Inversion Surface of underlying p type Si said to be inverted Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion (a) (b) g < 0 + polysilicon gate silicon dioxide insulator 0 < g < t depletion region + g > t + inversion region depletion region (c) LSI Design I Lect. 3 6
Accumulation, Depletion & Inversion LSI Design I Lect. 3 7 Bipolar vs. MOS Transistors Bipolar pn junction metallurgical MOS Inversion layer / substrate junction fieldinduced induced oltagecontrolled switch, conducts when gs t e swept along channel when ds > 0 by horizontal component of E Pinchoff conduction by e drift mechanism caused by positive drain voltage Pinchedoff channel voltage: gs t (saturated) Reversebiased pn junction insulates from the substrate LSI Design I Lect. 3 8 JFET vs. FET Transistors Junction FET (JFET) channel is deep in semiconductor MOSFET For given ds & gs, I ds controlled by: Distance between source & drain L Channel width W t Gate oxide thickness t ox ε gate oxide Carrier mobility μ LSI Design I Lect. 3 9
JFET Transistor LSI Design I Lect. 3 10 Punchthrough and pmosfet Avalanche breakdown for very high ds gate has no control over I ds LSI Design I Lect. 3 11 Terminal oltages Mode of operation depends on g, d, s + + gs gs = g s gd = g d s + ds ds = d s = gs gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation LSI Design I Lect. 3 12 g gd d
nmos Cutoff No channel I ds = 0 gs < gs = 0 t + s g + gd d n+ n+ b LSI Design I Lect. 3 13 nmos Linear Channel forms Current flows from d to s e from s to d I ds increases with ds Similar to linear resistor gs > t + + gd = g gs s d n+ n+ ds = 0 b gs > t + + gs > gd > g t s d I ds n+ n+ 0 < ds < gs t b LSI Design I Lect. 3 14 nmos Saturation Channel pinches off I ds independent of ds We say current saturates Similar to current source gs > t + s g + gd < t d I ds n+ n+ ds > gs t b LSI Design I Lect. 3 15
t Dependencies Gate material Gate insulation material Gate insulator thickness Channel doping Impurities at Si SiO 2 interface sb voltage from source to substrate t α 1/T 44 m / o C High substrate doping 22 m/ o C Low substrate doping LSI Design I Lect. 3 16 Non DeepSubmicron Threshold Equations t = tmos = 2 φ b + tmos + fb Ideal t of Ideal MOS Capacitor Q b C ox N ( A ) Flatband voltage point at which energy levels go flat kt φ b = ln, bulk potential difference between Fermi q n i level of doped & intrinsic Si C ox = oxide capacitance Q b = bulk charge = 2 ε Si q N A 2 φ b n i = 1.45 x 10 10 cm 3 at 300 o K LSI Design I Lect. 3 17 Threshold Equations (cont d) E i as reference energy level Conditions due to different φ s values φ s =0, Flatband Condition φ s <0, Accumulation φ s >0, Depletion φ s >0 & φ s > φ F, Inversion Condition for strong inversion LSI Design I Lect. 3 18
Threshold Equations (cont d) k = Boltzmann s s constant = 1.380 x 10 23 J/ o K q = 1.602 x 10 19 C (1 e charge) kt/q = 0.02586. at 300 o K (thermal voltage) ε Si = 1.06 x 10 12 F/cm Intrinsic Fermi level midway between conduction & valence bands p Fermi level closer to valence band n Fermi level closer to conduction band Q fb = φ ms fc C ox Q fc = fixed charge due to imperfections in Si SiO 2 interface and due to doping LSI Design I Lect. 3 19 Threshold Equations (cont d) φ ms = φ gate φ Si work function difference between gate material & Si substrate E φ ms = ( g 2 + φ b ) = 0.9 (N( A = 1 x 10 16 cm 3 ) E g = band gap energy of Si = (1.16 0.704 x 10 3 T 2 T ) + 1108 5 φ ms 0.2 (N( A = 1 x 10 16 cm 3 ) LSI Design I Lect. 3 20 Adjustments to t Change t by: Changing substrate doping N A Changing C ox (use a different insulator) (usual method) Changing surface state charge Q fc (usual method) Changing T (temperature) Often use a layer of Silicon nitride Si 3 N 4 ε Si3N4 = 7.5 on top of SiO 2 Dual dielectric process gives combined ε relative = 6 Electrically equivalent to thinner layer of SiO 2, leads to higher C ox MOS transistors selfisolating if regions between devices cannot be inverted by normal circuit voltages HighK LSI Design I Lect. 3 21
Example LSI Design I Lect. 3 22 Body Effect Series devices sb increases as we proceed along series chain Result: Channelsubstrate depletion layer width increases Result Increased density of trapped carriers in depletion layer For charge neutrality to hold, channel charge must decrease Result: sb adds to channelsubstrate junction potential, gate channel voltage drop increases, effectively get a higher t LSI Design I Lect. 3 23 I Characteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? LSI Design I Lect. 3 24
Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = gate polysilicon gate t ox L n+ n+ W SiO2 gate oxide (good insulator, ε ox = 3.9) + g + source gs C g gd drain s channel d n+ + n+ ds LSI Design I Lect. 3 25 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = t ox polysilicon gate L n+ n+ W SiO2 gate oxide (good insulator, ε ox = 3.9) gs gate + g + source C g gd drain s channel d n+ + n+ ds LSI Design I Lect. 3 26 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C C = C g = ε ox WL/t ox = C ox WL ox = ε ox / t ox = t ox polysilicon gate L n+ n+ W SiO2 gate oxide (good insulator, ε ox = 3.9) gate + g + source C g gd drain gs s channel d n+ + n+ ds LSI Design I Lect. 3 27
Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = C g = ε ox WL/t ox = C ox WL = gc t = (( gs ds /2) t t ox polysilicon gate L n+ n+ W SiO2 gate oxide (good insulator, ε ox = 3.9) Where C ox = ε ox / t ox F/cm 2 gate + g + source C g gd drain gs s channel d n+ + n+ ds LSI Design I Lect. 3 28 Carrier velocity Charge is carried by ee Carrier velocity v proportional to lateral Efield E between source and drain v = LSI Design I Lect. 3 29 Carrier velocity Charge is carried by ee Carrier velocity v proportional to lateral Efield E between source and drain v = μe μ called mobility E = LSI Design I Lect. 3 30
Carrier velocity Charge is carried by ee Carrier velocity v proportional to lateral Efield E between source and drain v = μe μ called mobility E = ds /L Time for carrier to cross channel: t = LSI Design I Lect. 3 31 Carrier velocity Charge is carried by ee Carrier velocity v proportional to lateral Efield E between source and drain v = μe μ called mobility E = ds /L Time for carrier to cross channel: t = L / v LSI Design I Lect. 3 32 nmos Linear II Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I = ds LSI Design I Lect. 3 33
nmos Linear II Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Q = t = channel LSI Design I Lect. 3 34 nmos Linear II Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel Ids = t W = μc ds ox gs t 2 ds L W β = μcox = β ds gs L t 2 ds LSI Design I Lect. 3 35 nmos Saturation II If gd < t, channel pinches off near drain When ds > dsat = gs t Now drain voltage no longer increases current I ds = LSI Design I Lect. 3 36
nmos Saturation II If gd < t, channel pinches off near drain When ds > dsat = gs t Now drain voltage no longer increases current I = β dsat 2 ds gs t dsat LSI Design I Lect. 3 37 nmos Saturation II If gd < t, channel pinches off near drain When ds > dsat = gs t Now drain voltage no longer increases current I dsat ds = β gs t 2 dsat β = ( ) 2 gs t 2 LSI Design I Lect. 3 38 nmos I I Summary Shockley 1 st order transistor models 0 gs < t I = β ds 2 < β ( ) 2 > 2 ds gs t ds ds dsat gs t ds dsat cutoff linear saturation LSI Design I Lect. 3 39
Example I Characteristics for MOSFETs We will be using a 0.6 μm m process From AMI Semiconductor 2.5 t ox = 100 Å μ = 350 cm 2 2 /*s 1.5 t = 0.7 1 Plot I ds vs. ds 0.5 gs = 0, 1, 2, 3, 4, 5 0 Use W/L = 4/2 λ 14 W 3.9 8.85 10 W W β = μcox = ( 350) 120 μa/ 8 = L 100 10 L L I ds (ma) 0 1 2 3 4 5 2 LSI Design I Lect. 3 40 ds gs = 5 gs = 4 gs = 3 gs = 2 gs = 1 pmos II All dopings and voltages are inverted for pmos Mobility μ p is determined by holes Typically 23x 2 lower than that of electrons μ n 120 cm 2 /*s in AMI 0.6 μm process Thus pmos must be wider to provide same current In this class, assume μ n / μ p = 2 LSI Design I Lect. 3 41 MOS Device Equations Ideal Shockley Equations: 1. I ds = 0, gs t 0 (cutoff or subthreshold) 2 2. I ds = β [( gs t ) ds ds ], 0 < ds < gs 2 t (nonsaturation, linear, or triode) β 3. I ds = (( gs t ) 2 2, 0 < gs t < ds (saturation) β = MOS transistor gain = μ = carrier mobility W = Channel Width L = Channel length μ ε t ox process W L ( ) geometry LSI Design I Lect. 3 42
MOS Equations (continued) με K p = processdependent gain factor = = μ C ox μ nbulk μ pbulk μ nsurface t ox Si 1350 450 500 Units of cm 2 / ( sec) Ge 3600 GaAs 5000 ε SiO2 = 4 ε o = 4 x 8.854 x 10 14 F/cm t ox 200 A o For a 1 μm m process: Typical β n = 88.5 W/L μa/ Typical β p = 31.9 W/L μa/ LSI Design I Lect. 3 43 Spice/Spectre Spectre Models for MOSFETs LEEL 1 Shockley equation + some 2 nd order effects LEEL 2 Based on device physics LEEL 3 Semiempirical empirical match equations to real circuits based on parameters BSIM3 v3 3.1 Berkeley empirical deep submicron model Use this one all other models give incorrect results Predict too high a t Exaggerate the body effect Incorrectly calculate leakage currents (drain induced barrier lowering) K P major Spice/Spectre Spectre parameter 10 to 100 μa/ 2, varies 1020 % in manufacturing process LSI Design I Lect. 3 44 SecondOrder Effects Cannot Be Ignored LSI Design I Lect. 3 45
Threshold oltage Body Effect t0 Threshold voltage when sb = 0 t = fb + 2 φ b + 2 ε Si q N A (2 φ b + sb ) C ox = t0 + γ [ (2 φ b + sb ) 2 φ b ] 0.4 γ 1.2 γ = t ox 2 q ε Si N A = 1 2 q ε Si N A ε ox C ox Equivalent SPICE parameters: GAMMA, T0 NSUB is N A, PHI is φ s = 2 φ b (surface potential at onset of strong inversion) LSI Design I Lect. 3 46 Threshold oltage Body Effect t0 Threshold voltage when sb = 0 t = fb + 2 φ b + 2 ε Si q N A (2 φ b + sb ) C ox = t0 + γ [ (2 φ b + sb ) 2 φ b ] 0.4 γ 1.2 γ = t ox 2 q ε Si N A = 1 2 q ε Si N A ε ox C ox Equivalent SPICE parameters: GAMMA, T0 NSUB is N A, PHI is φ s = 2 φ b (surface potential at onset of strong inversion) LSI Design I Lect. 3 47 Subthreshold Region Conduction I ds 0,, but increases exponentially with ds & gs Affects dynamic storage memory cells Use BSIM to model LSI Design I Lect. 3 48
Channel Length Modulation Channel length changes for short channels as ds changes Must now be modeled Effective channel length: L eff = L L short L short = 2 ε Si ( ds ( gs t )) q N A Shorter length increases W/L ratio, increases β as d increases Gives a finite output impedance, not a pure current source More accurate model (which we must use): I ds = K P W ( gs t ) 2 (1 + λ l ds ) 2 L λ = channel length modulation factor (Spice parameter LAMBDA) Use SPICE LEEL I to model LSI Design I Lect. 3 49 Mobility ariation μ = average carrier drift velocity (v)( Electric Field Ε Decreases with increasing doping and with increasing T μ is Spice parameter U0 Use BSIM to model LSI Design I Lect. 3 50 FowlerNordheim Tunneling For very thin gate oxides, Current flows from gate to source or gate to drain by e tunneling through SiO 2 Exploit in High Electron Mobility Transistor (HEMT) E 0 E I FN = C 1 W L E 2 ox ox e E ox = gs, Electric field across gate oxide t ox E 0, C 1 are constants Limits oxide thickness as processes are scaled used in making EPROMS LSI Design I Lect. 3 51
Drain Punchthrough Drain depletion region extends to source at high voltages Lose gate control of transistor Used in pin I/O (pad) circuits to make Zener diodes Forces voltages to be scaled down as device sizes are scaled down LSI Design I Lect. 3 52 Impact Ionization Hot e For submicron gate lengths << 1 μm,, a major problem e get so much energy that they impact the drain, and dislodge holes, which are swept toward the grounded substrate Creates a substrate current e may penetrate the gate oxide and cause gate current Degrades t, subthreshold current, β Causes circuit failure Poor DRAM refresh times, noise in mixed analogdigital circuits, latchup Hot holes are too slow to cause trouble LSI Design I Lect. 3 53 Solutions to Impact Ionization Solve with lightlydoped drains Drop to 3. or lower I substrate = I ds C1 ( ds dsat ) C2 C1 = 2.24 X 10 5 0.1 X 10 5 ds C2 = 6.4 dsat = tm L eff E sat tm + L eff E sat tn 0.13 tm = gs tn E sat = 1.10 X 10 0.13 bs 0.25 gs = 1.10 X 10 7 + 0.25 X 10 7 gs LSI Design I Lect. 3 54
Spice Modeling Parameters Also must use process parameters in LEEL III model to calculate T0, KP, GAMMA, PHI,, and LAMBDA See Section 2.11 in book. LSI Design I Lect. 3 55 Small Signal AC MOSFET Model Linear transistor region operation only g ds = β [ (( gs t ) 2 ds ] = lim g ds β ( gs t ) ds 0 R channel (linear) = 1 β ( gs t ) Model as a resistor LSI Design I Lect. 3 56 Saturation Small Signal Model In saturation, behaves like a current source β d I ds = d [ 2 (( gs t ) 2 ] = 0 d ds d ds But channel length modulation gives this a slope g m = d I ds d ds ds = constant g m (linear) = β ds g m (sat) = β ( gs t ) LSI Design I Lect. 3 57
Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with source/drain diffusion LSI Design I Lect. 3 58 Gate Capacitance Approximate channel as connected to source C gs = ε ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 ff/μm polysilicon gate W t ox n+ L n+ SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) LSI Design I Lect. 3 59 Diffusion Capacitance C sb, C db Undesirable, called parasitic parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted aries with process LSI Design I Lect. 3 60
Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing LSI Design I Lect. 3 61 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing g = If s > t, gs < t Hence transistor would turn itself off nmos pass transistors pull no higher than Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than tp DD tn LSI Design I Lect. 3 62 Pass Transistor Ckts SS LSI Design I Lect. 3 63
Pass Transistor Ckts s = tn tn tn tn s = tp tn 2 tn SS LSI Design I Lect. 3 64 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds ( ds, gs ) with effective resistance R I ds = ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay LSI Design I Lect. 3 65 Summary Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Models in this lecture For pedagogical purposes only Obsolete for deepsubmicron technology Real transistor parameter differences: Much higher transistor current leakage Body effect less significant than predicted t is lower than predicted More accurate models covered later LSI Design I Lect. 3 66
c = ( s + d )/2 = s + ds /2 gc = g c = g s ds /2 = (( gs ds /2) gate polysilicon gate t ox L n+ n+ W SiO2 gate oxide (good insulator, ε ox = 3.9) + g + source gs C g gd drain s channel d n+ + n+ ds LSI Design I Lect. 3 67