CDHC, CD7HC, CDHCT, CD7HCT Data sheet acquired from Harris Semiconductor SCHS7E August 997 - Revised September 00 High-Speed CMOS Logic Triple -Input AND Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject (High Features Buffered Inputs Typical Propagation Delay: 8ns at = V, C L = pf, T A = o C Fanout (Over Temperature Range) - Standard Outputs............... 0 LS - Bus Driver Outputs............. LS Wide Operating Temperature Range... - o C to o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - V to 6V Operation - High Noise Immunity: N IL = 0%, N IH = 0% of at = V HCT Types -.V to.v Operation - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V IH = V (Min) - CMOS Input Compatibility, I l µa at V OL, V OH Description The HC and HCT logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 0 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CDHCFA - to Ld CERDIP CDHCTFA - to Ld CERDIP CD7HCE - to Ld PDIP CD7HCM - to Ld SOIC CD7HCMT - to Ld SOIC CD7HCM96 - to Ld SOIC CD7HCTE - to Ld PDIP CD7HCTM - to Ld SOIC CD7HCTMT - to Ld SOIC CD7HCTM96 - to Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 0. Pinout CDHC, CDHCT (CERDIP) CD7HC, CD7HCT (PDIP, SOIC) TOP VIEW A B C A Y B C C 0 B Y 6 9 A 7 8 Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 00, Texas Instruments Incorporated
Functional Diagram CDHC, CD7HC, CDHCT, CD7HCT A B C A Y B C C 0 B Y 6 9 A 7 8 Y TRUTH TABLE S na nb nc ny L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H Logic Symbol na nb ny nc
Absolute Maximum Ratings DC Supply,........................ -0.V to 7V DC Input Diode, I IK For V I < -0.V or V I > + 0.V......................±0mA DC Output Diode, I OK For V O < -0.V or V O > + 0.V....................±0mA DC Output Source or Sink per Output Pin, I O For V O > -0.V or V O < + 0.V....................±mA DC or Ground, I CC or I..................±0mA Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) E (PDIP) Package.................................. 80 M (SOIC) Package.................................. 86 Maximum Junction Temperature (Hermetic Package or Die)... 7 o C Maximum Junction Temperature (Plastic Package)........ 0 o C Maximum Storage Temperature Range..........-6 o C to 0 o C Maximum Lead Temperature (Soldering 0s)............. 00 o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range (T A )..................... - o C to o C Supply Range, HC Types.....................................V to 6V HCT Types..................................V to.v DC Input or Output, V I, V O................. 0V to Input Rise and Fall Time V...................................... 000ns (Max).V...................................... 00ns (Max) 6V....................................... 00ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. The package thermal impedance is calculated in accordance with JESD -7. DC Electrical Specifications HC TYPES High Level Input Low Level Input CMOS Loads Input Leakage V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH - -. - -. -. - V.. - -. -. - V 6. - -. -. - V - - - - 0. - 0. - 0. V. - -. -. -. V 6 - -.8 -.8 -.8 V V OH V OL I I V IH or -0.0.9 - -.9 -.9 - V -0.0.. - -. -. - V -0.0 6.9 - -.9 -.9 - V - - - - - - - - - V -..98 - -.8 -.7 - V -. 6.8 - -. -. - V V IH or 0.0 - - 0. - 0. - 0. V 0.0. - - 0. - 0. - 0. V 0.0 6 - - 0. - 0. - 0. V or - - - - - - - - - V. - - 0.6-0. - 0. V. 6 - - 0.6-0. - 0. V - 6 - - ±0. - ± - ± µa
DC Electrical Specifications (Continued) Quiescent Device HCT TYPES High Level Input Low Level Input CMOS Loads CMOS Loads Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: Unit Load I CC or V IH - -. to. - -. to. V OH V OL I I I CC I CC (Note ) V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX 0 6 - - - 0-0 µa - - - - V - - 0.8-0.8-0.8 V V IH or -0.0.. - -. -. - V -..98 - -.8 -.7 - V V IH or 0.0. - - 0. - 0. - 0. V and or -.. - - 0.6-0. - 0. V -. - ±0. - ± - ± µa -. - - - 0-0 µa -. to. NOTE:. For dual-supply systems theoretical worst case (V I =.V, =.V) specification is.8ma. - 00 60-0 - 90 µa HCT Input Loading Table UNIT LOADS All 0. NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g. 60µA max at o C. Switching Specifications Input t r, t f = 6ns HC TYPES Propagation Delay, Input to Output (Figure ) Propagation Delay, Data Input to Output Y (V) MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 0pF - - 00 - - 0 ns. - - 0 - - 0 ns 6 - - 7 - - 6 ns t PLH, t PHL C L = pf - 8 - - - - - ns
Switching Specifications Input t r, t f = 6ns (Continued) Transition Times (Figure ) t TLH, t THL C L = 0pF - - 7-9 - 0 ns. - - - 9 - ns 6 - - - 6-9 ns Input Capacitance C I C L = 0pF - - - 0-0 - 0 pf Power Dissipation Capacitance (Notes, ) C PD C L = pf - 6 - - - - - pf HCT TYPES Propagation Delay, Input to Output (Figure ) Propagation Delay, Data Input to Output Y t PLH, t PHL C L = 0pF. - - 8 - - ns t PLH, t PHL C L = pf - - - - - - ns Transition Times (Figure ) t TLH, t THL C L = 0pF. - - - 9 - ns Input Capacitance C I C L = 0pF - - - 0-0 - 0 pf Power Dissipation Capacitance (Notes, ) C PD - - 8 - - - - - pf NOTES:. C PD is used to determine the dynamic power consumption, per gate.. P D = V CC f i (C PD + C L ) where f i = input frequency, C L = output load capacitance, = supply voltage. (V) MIN TYP MAX MIN MAX MIN MAX Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns 0% 0%.7V.V 0.V V t THL t TLH t THL t TLH INVERTING t PHL t PLH 0% 0% INVERTING t PHL t PLH.V 0% FIGURE. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC