EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel C GS = 3 C GC + C GSO W C GD = C GDO W 1
SPICE Model for NMOS Transistor Typical default values used by SPICE: K P = 50 or 0 µa/v γ = 0 λ = 0 V TO = 1 V µ n or µ p = 500 or 00 cm /V-s Φ F = 0.6 V C GDO = C GSO = C GBO = C JSW = 0 T ox = 100 nm 3 MOS Transistor Scaling All physical dimensions shrinks by a factor of α All voltages (including threshold voltage) reduced by α also Constant field scaling Drain current: i D * = µ n ε ox T ox W α " v GS α L α α V TN α v % DS $ ' v DS # α & α = i D α Gate Capacitance: * C GC ( ) * W * L * = ε ox " = C ox T ox! W $ # α " α % &! L $ # " α & = C GC % α Circuit delay in a logic circuit. τ * * ΔV * = C GC = C GC ΔV /α * i D α i D /α = τ α 4
MOS Transistor Scaling Scale Factor α (cont.) Circuit and Power Densities: P * = V * DD i * D = i D α α = P α P * A = P* * W * L = P α * W α ( )( L α) = P A extremely important result! Power-Delay Product: Cutoff Frequency: PDP * = P * τ * = P α τ α = PDP α 3 ω T = g m C GC = µ n L ( V TN ) f T improves with square of channel length reduction 5 Impact of Velocity Saturation At low electric field, electron velocity is proportional to field At high electric field, the velocity reaches a maximum called saturation velocity, v SAT i D = C " oxw ( v GS V TN )v SAT The drain current is proportional to (v GS V TN ) rather than its square There are (many) other corrections to the basic model when the channel become very short Interested, take EE130 6 3
NMOSFET in OFF State We had previously assumed that there is no channel current when v GS < V TN. This is incorrect! As v GS is reduced (toward 0 V) below V TN, the potential barrier to carrier diffusion from the source into the channel is increased. The drain current is limited by carrier diffusion into the channel, rather than by carrier drift through the channel. This is similar to the case of a PN junction diode! varies exponentially with the potential barrier height at the source, which varies directly with the channel potential. 7 Sub-Threshold Leakage Current In the depletion (sub-threshold) region of operation, the channel potential is capacitively coupled to the gate potential. A change in gate voltage (Δv GS ) results in a change in channel voltage (Δv CS ): # i D exp ΔV & CS % ( Similar to pn junction diode! $ ' V T # C & ΔV CS = Δ ox % $ C ox + C ( Δ / m, m =1+ C dep >1 dep ' C ox Sub-threshold slope (also called sub-threshold swing): # S d(log 10 S )& % ( $ ' d 1 S = mv T ln(10) > 60mV/dec 8 4
MOS Transistor Scaling (cont.) Fixed Subthreshold Slope Leakage current ON state current Sub-threshold Conduction: i D decreases exponentially for v GS < V TN. Reciprocal of the slope in mv/decade gives the turn-off rate for the MOSFET. Fundamental limit of MOSFET sub-threshold slope: 60mV/decade 9 Mask Sequence Polysilicon-Gate Transistor Mask 1: Defines active area or thin oxide region of transistor Mask : Defines polysilicon gate of transistor, aligns to mask 1 Mask 3: Delineates the contact window, aligns to mask. Mask 4: Delineates the metal pattern, aligns to mask 3. Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 10 5
Basic Ground Rules for Layout Design of large circuits can be simplified with simple rules Minimum feature size: F = Λ Minimum alignment between different features: T = Λ Λ could be 1, 0.5, 0.5 µm, etc. In this example: W/L = 10Λ / Λ = 5 Transistor Area = 10 Λ 11 MOSFET Biasing Bias sets the dc operating point. The signal is actually comprised of relatively small changes in the voltages and/or currents. Remember (Total = dc + signal): v GS = + v gs and i D = + i d 1 6
Bias Analysis - Example 1: Constant Gate-Source Voltage Biasing = R D + =10V 50µA ( )( 100K) = 5.00 V Since I G = 0, V EQ = I G R EQ + = = K n ( V TN ) = 5x10 6 A ( 3 1 ) V = 50.0 µa V Check: > -V TN. Hence saturation region assumption is correct. Q-pt: (50.0 ma, 5.00 V) with = 3.00 V Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used. 13 Bias Analysis Using Load Line = R D + 10 =10 5 + For = 0, = 100 ua For = 0, = 10 V Plotting the line on the transistor output characteristic yields Q-pt at intersection with = 3V device curve. Check: The load line approach agrees with previous calculation. Q-pt: (50.0 ma, 5.00 V) with = 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region. 14 7
Bias Analysis - Constant Gate-Source Voltage Biasing with Channel-Length Modulation ( ) ( 1+ λ ) = K n V TN = R D =10 5x10 6 10 5 = 4.55 V = 5x10 6 ( )( 3 1) ( 1+ 0.0 ) [ ( )] = 54.5 µa ( 3 1) 1+ 0.0 4.55 Check: > - V TN. Hence the saturation region assumption is correct. Q-pt: (54.5 ma, 4.55 V) with = 3.00 V Discussion: The bias levels have changed by about 10% (54.5 µa vs 50 µa). Typically, component values will vary more than this, so there is little value in including λ effects in most circuits. 15 Bias Analysis - Example 6: Two-Resistor Feedback Biasing = K n ( V TN ) R D ( )( 1) = 3.3.6x10 4 10 4 = 0.769 V or +.00 V Since < V TN for = -0.769 V, the MOSFET would be cut-off, Assumption: I G = I B = 0, transistor is saturated (since = ) Analysis: = - R D = +.00 V and =130 µa > -V TN. Hence saturation region assumption is correct. Q-pt: (130 µa,.00 V) 16 8
Bias Analysis - Example 6: Two-Resistor Feedback Biasing = K n ( V TN ) R D ( )( 1) = 3.3.6x10 4 10 4 = 0.769 V or +.00 V Since < V TN for = -0.769 V, the MOSFET would be cut-off, Assumption: I G = I B = 0, transistor is saturated (since = ) Analysis: = - R D = +.00 V and =130 µa > -V TN. Hence saturation region assumption is correct. Q-pt: (130 µa,.00 V) 17 Bias Analysis Two-Resistor biasing for PMOS Transistor Assumption: I G = I B = 0; transistor is saturated Analysis: I G R G = 0 = + R D = 0 + K n ( V TP ) R D = 0 ( ) 5x10 5 ( ) = 0 15+.x10 5 + = 0.369 V or 3.45 V Since = 0.369 > V TP, = 3.45 V = 5.5 µa and = 3.45 V > V TP Hence saturation assumption is correct. Q-pt: (5.5 µa, -3.45 V) 18 9