EE 434 Lecture 16 Sall sinal odel Sall sinal applications in aplifier analysis and desin
Quiz 13 The of an n-channel OS transistor that has a quiescent current of 5A was easured to be 10A/. If the lenth of the transistor is.6u, deterine the width. Assue the process paraeters uc 100uA/, TO 700
1 And the nuber is. 8 6 9 7 5 4 3
Quiz 13 Solution The of an n-channel OS transistor that has a quiescent current of 5A was easured to be 10A/. If the lenth of the transistor is.6u, deterine the width. Assue the process paraeters uc 100uA/, TO 700 I DQ C L L C Ox I DQ ( 10E - 3) 5E - 3 0.6 100E - 6 60
Review fro Last Tie odel paraeters available fro OSIS site Square-law odel paraeters µ obtained fro K and C quite size and operatin point dependent so obtain fro siulation BSI odel Contains 97 paraeters odels best when close to size and operatin point of device hen corner odels added and binnin odels added, paraeter space becoes uch larer Actual device paraeters will vary due to noinal process variation and rando die-level variation odel still has soe errors Considerable onoin activity on device odelin Several hundred papers per year appearin on OSFET odelin alone Level of activity in odelin probably increasin
Sall Sinal odel Suary ( ) T GSQ L C o I DQ BSQ b φ γ ds o bs b s d b v v v i i i + + 0 0
Sall Sinal odel Suary Lare Sinal odel Sall Sinal odel I D 0 C C T L L GS ( ) ( 1+ λ ) GS T T + γ DS DS DS GS ( φ φ ) T0 BS GS GS T T T DS DS < GS GS T T i i i b d 0 0 where b v s + b C L γ φ v bs + ( ) GSQ BSQ T o v ds o I DQ
Sall Sinal odel Suary An equivalent circuit C L o I DQ b ( ) GSQ γ φ BSQ T This contains absolutely no ore inforation than the previous odel
Sall Sinal odel Suary ore convenient representation
Sall Sinal odel Suary Siplification that is often adequate
Sall Sinal odel Suary Even further siplification that is often adequate
Sall Sinal odel Suary Alternate equivalent representations for C L ( ) GSQ T fro I D C L ( ) GS T C L I DQ I DQ GSQ T I DQ Q
How does vary with I DQ? C L I DQ aries with the square root of I DQ I DQ GSQ T I DQ Q aries linearly with I DQ C L ( ) GSQ T Doesn t vary with I DQ
How does vary with I DQ? All of the above are true but with qualification is a function of ore than one variable (I DQ ) and how it varies depends upon how the reainin variables are constrained
Sall sinal analysis exaple DD R 1 OUT 1 uc 100uA/ T.75 λ.01-1 DD 8 SS -1.5 16u L1u R 1 15K SS sinωt
Sall sinal analysis exaple DD R 1 + GS SS 1 OUT + + I D DD I DR1 DS SS µc GS T 1 L ( ) ( + λ ) DS SS sinωt + OUT DS SS ust solve 5 siultaneous equations to obtain OUT But one of these equations is nonlinear akin the solution very tedious
Sall sinal analysis exaple I D µc GS T 1 L ( ) ( + λ ) DS 300 50 00 Id 150 100 50 0 0 1 3 4 5 ds
Sall sinal analysis exaple I R + + DD D 1 DS SS I D µc GS T 1 L ( ) ( + λ ) DS 300 50 00 Id 150 100 50 + 0 GS 0 1 3 4 5 Consider very sall SS ds Q-point
Sall sinal analysis exaple DD R 1 OUT 1 SS + + + I D DD GS I DR1 SS DS SS µc GS T 1 L + OUT DS ( ) ( + λ ) SS DS Consider 0,,- Define GS - T when 0 sinω t Thus - SS - T OUT DD I DR1 I D µc L ( + )
Sall sinal analysis exaple DD R 1 OUT 1 I D OUT µc DD L I DR 1 ( + ) SS OUT DD R1 µ C + L ( ) sinω t
Sall sinal analysis exaple DD R 1 1 OUT OUT DD R1 µ C + L ( ) SS T 1.5.75 0. 5 SS sinω t OUT L ( ) R µ C ( ) 0 DD 1 16 1 OUT 5 4 ( 0) 8 15K 10 1 This is tered the quiescent output voltae
Sall sinal analysis exaple 300 50 00 Id 150 100 50 0 0 1 3 4 5 ds 5 Q-point
Sall sinal analysis exaple DD R 1 OUT DD R1 µ C + L 0. 5 ( ) 1 OUT OUT DD 1 + L ( ) R µ C ( ) If 0.1 SS sinω t OUT 16 1 4 ( ) 8 15K 10 (.1 +.5) 3. 68 OUT DD 1 + L ( ) R µ C ( ) OUT 16 1 4 ( ) 8 15K 10 (.1+.5) 6. 08
Sall sinal analysis exaple 300 50 00 Id 150 100-50 0 0 1 3 4 5 3.68 5.0 6.08 ds Note sinal swin is not syetric
Sall sinal analysis exaple SS DD R 1 1 sinω t Note: Apparent ain is independent of OUT Aˆ OUT ( ) ( ) OUT Paraetric expression for apparent ain OUT DD 1 + L ( ) R µ C ( ) OUT DD 1 + L Aˆ Aˆ Aˆ Aˆ ( ) R µ C ( ) R R R 1 1 1 R µ C L µ C L µ C L 1 ( + ) ( + ) ( + ) ( + ) ( + + ) ( + + ) µ C L 4 R 1 µ C L
Sall sinal analysis exaple DD R 1 OUT 1 C Aˆ µ R1 L ery siple expression for apparent ain SS Derivation of apparent ain very tedious sinω t Apparent ain ives inial insiht into desin strateies Near the Q-point, all well-behaved circuits operate linearly Can this linear operation be exploited to siplify the analysis?
Sall sinal analysis exaple DD R 1 R 1 1 OUT 1 OUT SS Circuit Scheatic Linearized Sall Sinal Circuit sinω t
Sall sinal analysis exaple Linearized Sall Sinal Circuits R 1 1 OUT
Sall sinal analysis exaple Linearized Sall Sinal Circuits OUT s sr 1 } A A OUT I DQ R 1 R 1 Still need I DQ and Sall sinal analysis uch sipler (because linear)
Sall sinal analysis exaple A Linearized Sall Sinal Circuits I µc DQ L L A ( ) I ( ) µc R1 DQ µc R 1 L SS T 1.5.75 0. 5 µc L R 1 A R 10 4 16 0.5 15K 1 1 This is identical to the nuerical value obtained for the apparent ain! 1
Sall sinal analysis exaple How does sall sinal ain copare to apparent ain for this circuit? C Aˆ µ R1 L IDQ A R1 µc L R 1 A For this circuit the apparent ain and the actual ain are identical This is not true in eneral but they will be close provided is reasonably sall and they becoe equal in the liit as approaches 0