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1 2 3 4 5 6 EE 330 Class Seating 1 2 3 4 5 6 7 8 Zechariah Daniel Liuchang Andrew Brian Difeng Aimee Julien Di Pettit Borgerding Li Mun Crist Liu Salt Tria Erik Nick Bijan Wing Yi Pangzhou Travis Wentai Hisham Lee Robbins Choobineh Lwe Li Cook Wang Abbas Ryan Jiayu Jean-Francois Morgan Bodhisatta Nagulapally Alfonso Corey Wade Hong Burnier Hardy Pramanik Spurthi Raymundo Wright Mohamad Aqila-Sarah Honghao Clayton Christopher Antonio Jaehyuk Logan Samusdin Zulkifli Liu Hawken Little Montoya Han Heinen Nicholas Satvik Alex Wei Shen Minh Trevor Zhong Mingda Riesen Shah McCullough Theh Nguyen Brown Zhang Yang Abdussamad Brenda Benjamin Blake Mark Daniel Ilya Bryce Hisham Lopez Engh Burns Rusciano Mallek Simirov Rooney

EE 330 Lecture 15 MOSFET Modeling CMOS Process Flow

Review from Last Lecture Basic Devices and Device Models Resistor Diode Capacitor MOSFET BJT

Review from Last Lecture Model Extension Summary I I G B 0 0 0 V V GS T W V L 2 W 2 μc V V 1 V V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T OX GS T DS GS T DS GS T V T V T0 V BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L

Id Review from Last Lecture Operation Regions by Applications I D 300 250 200 150 100 50 Triode Region Saturation Region Analog Circuits Cutoff Region 0 0 1 2 3 4 5 Vds Digital Circuits V DS Most analog circuits operate in the saturation region (basic VVR operates in triode and is an exception) Most digital circuits operate in triode and cutoff regions and switch between these two with Boolean inputs

Review from Last Lecture How many models of the MOSFET do we have? Switch-level model (2) Square-law model Square-law model (with λ and bulk additions) α-law model (with λ and bulk additions) BSIM model BSIM model (with binning extensions) BSIM model (with binning extensions and process corners)

Review from Last Lecture The Modeling Challenge I D Actual Modeled with one model V GS3 (and W/L variations or Process Variations) Local Agreement with Any Model V GS2 (and W/L variations or Process Variations) V GS1 (and W/L variations or Process Variations) V DS (and W/L variations or Process Variations) I G I D V DS I = f V,V D 1 GS DS I = f V,V G 2 GS DS I = f V,V B 3 GS DS V GS I B V BS = 0 Difficult to obtain analytical functions that accurately fit actual devices over bias, size, and process variations

Model Status Simple dc Model Square-Law Model Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations BSIM Model Square-Law Model (with extensions for λ,γ effects) Short-Channel α-law Model Frequency Dependent Small Signal Simpler dc Model Switch-Level Models Ideal switches R SW and C GS

In the next few slides, the models we have developed will be listed and reviewed Square-law Model Switch-level Models Extended Square-law model Short-channel model BSIM Model BSIM Binning Model Corner Models

Square-Law Model I D V GS4 V GS3 V DS V GS2 V GS1 0 VGS VT W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T Model Parameters : {μ,c OX,V T0 } Design Parameters : {W,L} but only one degree of freedom W/L

Switch-Level Models Drain Gate G D Source R SW C GS V GS Switch closed for V GS = 1 S Switch-level model including gate capacitance and drain resistance C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C GS 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C GS and R SW Model Parameters : {C GS,R SW }

Extended Square-Law Model I I G B 0 0 0 V V GS T W V L 2 W 2 μc V V 1 V V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T OX GS T DS GS T DS GS T V T V T0 V BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L

Short-Channel Model 0 V V GS T W I μc V V V V V V V D OX GS T DS GS T DS 1 GS L 1 W μc V V V V V V 2 OX GS T GS T DS 1 GS L V 2 2 2 V T T 2 α is the velocity saturation index, 2 α 1 Channel length modulation (λ) and bulk effects can be added to the velocity Saturation as well

BSIM model Note this model has 95 model parameters!

BSIM Binning Model - Bin on device sizes - multiple BSIM models! With 32 bins, this model has 3040 model parameters!

BSIM Corner Models - Often 4 corners in addition to nominal TT, FF, FS, SF, and SS - five different BSIM models! TT: typical-typical FF: fast n, fast p FS: fast n, slow p SF: slow n, fast p SS: slow n, slow p With 4 corners, this model has 475 model parameters!

Accuracy Complexity Hierarchical Model Comparisons BSIM Binning Models Analytical Numerical (for simulation only) L Number of Model Parameters BSIM Models Number of Model Parameters Square-Law Models Number of Model Parameters Switch-Level Models Approx 3000 (for 30 bins) Approx 100 3 to 6 W Number of Model Parameters 0 to 2

Corner Models Basic Model FF (Fast n, Fast p) FS (Fast n, Slow p) TT Typical-Typical SF (Slow n, Fast p) SS (Slow n, Slow p) Corner Model Applicable at any level in model hierarchy (same model, different parameters) Often 4 corners (FF, FS, SF, SS) used but sometimes many more Designers must provide enough robustness so good yield at all corners

n-channel. p-channel modeling Source Gate Drain Bulk I D 3 V GS4 2.5 D n-channel MOSFET D 2 1.5 1 V GS3 V GS2 G S G D S 0.5 0 0 1 2 3 4 5 VDS GS4 GS3 GS2 GS1 V GS1 V V V V > 0 V DS G B (for enhancement devices) G I G V GS I D D S I B B S V BS V DS 0 VGS VTn W V L 2 W 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B 2 μ C V V V V V V V n OX GS Tn GS Tn DS GS Tn Positive V DS and V GS cause a positive I D

Bulk Source n-channel. p-channel modeling Gate Drain (for enhancement devices) p-channel MOSFET S S G G D D D V GS G I G G I D B S D I B S V BS B V DS 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp Negative V DS and V GS cause a negative I D Functional form of models are the same, just sign differences and some parameter differences (usually mobility is the most important)

n-channel. p-channel modeling Bulk Source Gate Drain V GS G I G I D S B D I B V BS V DS p-channel MOSFET (for enhancement devices) 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp 0 V V GS Tp W V L 2 W 2L I =I =0 DS I μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G Alternate equivalent representation B 2 μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp These look like those for the n-channel device but with

D n-channel. p-channel modeling D S S G G G G S D S D D D G B G B S S G I G V GS I D D I B B V BS V DS V GS G I G S B I B V BS V DS S I D D I D 3 2.5 2 1.5 V GS4 V GS3 Models essentially the same with different signs and model parameters 1 V GS2 0.5 0 V GS1 0 1 2 3 4 5 V DS VDS VGS4 VGS3 VGS2 V GS1> 0 0 VGS VTn W V L 2 W 2 μ C V V V V V V V 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B n OX GS Tn GS Tn DS GS Tn 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C p OX VGS VTp VGS VTp VDS VGS VTp

Model Relationships Determine R SW and C GS for an n-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) 0 V V GS T W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T when SW is on, operation is deep triode

Model Relationships Determine R SW and C GS for an n-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) W V W L 2 L DS I μc V V V μc V V V D OX GS T DS OX GS T DS V 1 1 DS R = 4K SQ I W 1 D V GS =VDD μc V V ( E 4) 3. 5 1 OX GS T L V GS =3.5V 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF

Model Relationships Determine R SW and C GS for an p-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 W V W DS I μ C V V V μ C V V V L 2 L D p OX GS T DS p OX GS T DS V 1 1 DS R = 12K SQ I W 1 1 D V GS =VDD μ C V V ( E 4) 3. 5 1 p OX GS T L V GS =3.5V 3 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF Observe the resistance of the p-channel device is approximately 3 times larger than that of the n-channel device for same bias and dimensions!

Modeling of the MOSFET Goal: Obtain a mathematical relationship between the port variables of a device. I f V,V,V I I D G B 1 f f 2 3 GS DS BS VGS,V DS,VBS V GS,V DS,VBS Drain V DS I D I B Gate Bulk I D Simple dc Model V GS V BS Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations Frequency Dependent Small Signal Simpler dc Model

Small-Signal Model Goal with small signal model is to predict performance of circuit or device in the vicinity of an operating point Operating point is often termed Q-point

Small-Signal Model y Y Q Q-point X Q x Analytical expressions for small signal model will be developed later

Design Rules Technology Files Process Flow (Fabrication Technology) Model Parameters

n-well n-well n- p-

Bulk CMOS Process Description n-well process Single Metal Only Depicted Double Poly This type of process dominates what is used for high-volume lowcost processing of integrated circuits today Many process variants and specialized processes are used for lowervolume or niche applications Emphasis in this course will be on the electronics associated with the design of integrated electronic circuits in processes targeting highvolume low-cost products where competition based upon price differentiation may be acute Basic electronics concepts, however, are applicable for lower-volume or niche applicaitons

Components Shown n-channel MOSFET p-channel MOSFET Poly Resistor Doubly Poly Capacitor

C D A A B B C D

Consider Basic Components Only Well Contacts and Guard Rings Will be Discussed Later

A A B B

Metal details hidden to reduce clutter A A D G S B D B S B n-channel MOSFET G

A A D G S B B B W L

A A Capacitor Resistor p-channel MOSFET B B n-channel MOSFET

n-well n-well n- p-

N-well Mask A A B B

Detailed Description of First Photolithographic Steps Only Top View Cross-Section View

~ Blank Wafer Implant n-well Photoresist Mask p-doped Substrate Will use positive photoresist (exposed region soluble in developer) A A B Develop Expose B

Develop N-well Exposure Photoresist Mask A-A Section B-B Section

Implant A-A Section B-B Section

N-well Mask A-A Section B-B Section

n-well n-well n- p-

Active Mask A A B B

Active Mask Field Oxide A-A Section Field Oxide Field Oxide Field Oxide B-B Section

n-well n-well n- p-

Poly1 Mask A A B B

Poly plays a key role in all four types of devices! A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

Poly 1 Mask A-A Section Gate Oxide Gate Oxide B-B Section

n-well n-well n- p-

Poly 2 Mask A A B B

Poly 2 Mask A-A Section B-B Section

n-well n-well n- p-

P-Select A A B B

P-Select Mask p-diffusion p-diffusion A-A Section Note the gate is self aligned!! B-B Section

n-select Mask n-diffusion A-A Section n-diffusion B-B Section

n-well n-well n- p-

Contact Mask A A B B

Contact Mask A-A Section B-B Section

n-well n-well n- p-

Metal 1 Mask A A B B

Metal Mask A-A Section B-B Section

A A B B

A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

How does the inverter delay compare between a 0.5u process and a 0.13u process? V DD V IN V OUT V IN V OUT V SS

How does the inverter delay compare between a 0.5u process and a 0.13u process? 5.0 1.25 Assume n-channel and p-channel devices are minimum sized V IN V OUT n t HL =R pd C R L pd ncoxw n VDD VTN t LH =R pd C L R pu L Lp C W V V p OX p DD TP C C W L W L L OX n n p p 0.5u 0.13u CL 1.25E-15 3.549E-16 Rpd 2217 4128 Rpu 6098 23529 THL 2.77E-12 1.47E-12 TLH 7.62E-12 8.35E-12 Rpu for the p-ch 0.13 is in question

End of Lecture 15