INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC0 74C/CT/CU/CMOS Logic Family Specifications The IC0 74C/CT/CU/CMOS Logic Package Information The IC0 74C/CT/CU/CMOS Logic Package Outlines 74C/CT7 Dual JK flip-flop with reset; negative-edge trigger File under Integrated Circuits, IC0 December 1990
74C/CT7 FEATURES Output capability: standard I CC category: flip-flops GENERAL DESCRIPTION The 74C/CT7 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT7 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (ncp) and reset (nr) inputs; also complementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the IG-to-LOW clock transition for predictable operation. The reset (nr) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output IG. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = ns TYPICAL SYMBOL PARAMETER CONDITIONS C CT UNIT t PL / t PL propagation delay C L = 15 pf; V CC =5 V ncp to nq 1 15 ns ncp to nq 1 18 ns nr to nq, nq 15 15 ns f max maximum clock frequency 77 79 Mz C I input capacitance.5.5 pf C PD power dissipation capacitance per flip-flop notes 1 and 2 0 0 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS Logic Package Information. December 1990 2
74C/CT7 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 5 1CP, 2CP clock input (IG-to-LOW, edge-triggered) 2, 1R, 2R asynchronous reset inputs (active LOW) 4 V CC positive supply voltage 11 GND ground (0 V) 12, 9 1Q, 2Q true flip-flop outputs 1, 8 1Q, 2Q complement flip-flop outputs, 7,, 10 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig. IEC logic symbol. December 1990
74C/CT7 FUNCTION TABLE OPERATING INPUTS OUTPUTS MODE nr ncp J K Q Q asynchronous reset L X X X L toggle load 0 (reset) load 1 (set) hold no change h l h l h h l l q L q q L q Notes 1. = IG voltage level h = IG voltage level one set-up time prior to the IG-to-LOW CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the IG-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the IG-to-LOW CP transition X = don t care = IG-to-LOW CP transition Fig.4 Functional diagram. Fig.5 Logic diagram (one flip-flop). December 1990 4
74C/CT7 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: standard I CC category: flip-flops AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = ns; C L = 50 pf SYMBOL t PL / t PL t PL / t PL t PL / t PL PARAMETER propagation delay ncp to nq propagation delay ncp to nq propagation delay nr to nq, nq T amb ( C) 74C +25 40 to +85 40 to +125 min. typ. max. min. max. min. max. 52 19 15 52 19 15 50 18 t TL / t TL output transition time 19 7 t W t W t rem t su t h f max clock pulse width IG or LOW reset pulse width IG or LOW removal time nr to ncp set-up time nj, nk to ncp hold time nj, nk to ncp maximum clock pulse frequency 80 1 80 1 80 1 80 1 0 5 8 8 8 8 8 2 2 70 8 10 2 27 10 2 27 5 29 25 75 15 1 100 17 100 17 100 17 100 17 4.8 28 0 40 4 0 40 4 180 1 95 19 1 1 1 1 1 4.0 0 48 41 0 48 41 2 44 8 110 19 UNIT TEST CONDITIONS V CC (V) Mz 2.0 WAVEFORMS Fig.7 Fig.7 Fig.7 December 1990 5
74C/CT7 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: standard I CC category: flip-flops Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT nk nr ncp, nj UNIT LOAD COEFFICIENT 0.0 0.5 1.00 AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = ns; C L = 50 pf SYMBOL PARAMETER T amb ( C) 74 CT +25 40 to +85 40 to +125 UNIT TEST CONDITIONS min. typ. max. min. max. min. max. t PL / t PL propagation delay 18 8 48 57 ns ncp to nq t PL / t PL propagation delay 21 45 54 ns ncp to nq t PL / t PL propagation delay 4 4 51 ns Fig.7 nr to nq, nq t TL / t TL output transition time 7 15 19 ns VCC (V) WAVEFORMS t W t W t rem t su t h f max clock pulse width IG or LOW reset pulse width IG or LOW removal time nr to ncp set-up time nj, nk to ncp hold time nj, nk to ncp maximum clock pulse frequency 1 8 ns 18 9 2 27 ns Fig.7 8 18 21 ns Fig.7 12 15 18 ns 2 ns 0 72 Mz December 1990
74C/CT7 AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1. V; V I = GND to V. Waveforms showing the clock (ncp) to output (nq, nq) propagation delays, the clock pulse width, the J and K to ncp set-up and hold times, the output transition times and the maximum clock pulse frequency. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1. V; V I = GND to V. Fig.7 Waveforms showing the reset (nr) input to output (nq, nq) propagation delays and the reset pulse width and the nr to ncp removal time. PACKAGE OUTLINES See 74C/CT/CU/CMOS Logic Package Outlines. December 1990 7
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