DS00 -Tap Silicon Delay Line FEATURES All-silicon time delay taps equally spaced Delay tolerance ± ns or ±%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing edge accuracy Economical Auto-insertable, low profile Standard -pin DIP, -pin DIP, or -pin SOIC Tape and reel available for surface-mount Low-power CMOS TTL/CMOS compatible Vapor phase, IR and wave solderability Custom delays available P ASSIGNMENT TAP 0 9 Vcc TAP TAP DS00 -P DIP (00 MIL) TAP TAP 0 9 V CC TAP TAP DS00S -P SOIC (00 MIL) Vcc TAP TAP DS00M -P DIP (00 MIL) Quick turn prototypes Extended temperature range available DESCRIPTION The DS00 -Tap Silicon Delay Line provides five equally spaced taps with delays ranging from ns to 0 ns, with an accuracy of ± ns or ±%, whichever is greater. This device is offered in a standard -pin DIP making it compatible with existing delay line products. Space-saving -pin DIPs and -pin SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is achieved by the combination of a 00% silicon delay line and industry standard DIP and SOIC packaging. In order to maintain complete P DESCRIPTION TAP TAP Output Number V CC + Volts Ground No Connection Input pin compatibility, DIP packages are available with hybrid lead configurations. The DS00 reproduces the input logic level at each tap after the fixed delay specified by the dash number in Table. The device is designed with both leading and trailing edge accuracy. Each tap is capable of driving up to ten LS loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call (). 09 /
LOGIC DIAGRAM Figure TAP TAP TAP 0% 0% 0% 0% 0% PART NUMBER DELAY TABLE (t PHL, t PLH ) Table PART NO. TAP TAP TAP DS00-0 ns ns ns ns 0 ns DS00- ns 0 ns ns 0 ns ns DS00-00 0 ns 0 ns 0 ns 0 ns 00 ns DS00- ns 0 ns ns 00 ns ns DS00-0 0 ns 0 ns 90 ns 0 ns 0 ns DS00- ns 0 ns 0 ns 0 ns ns DS00-00 0 ns 0 ns 0 ns 0 ns 00 ns DS00-0 0 ns 00 ns 0 ns 00 ns 0 ns Custom delays available 09 /
ABSOLUTE MAXIMUM RATGS* Voltage on Any Pin Relative to Ground -.0V to +.0V Operating Temperature 0 C to 0 C Storage Temperature - C to + C Soldering Temperature 0 C for 0 seconds Short Circuit Output Current 0 ma for second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (0 C to 0 C; V CC =.0V ± %) PARAMETER SYMBOL TEST COND. M TYP MAX UNITS NOTES Supply Voltage V CC..00. V High Level Input Voltage V IH. V CC +0. V Low Level Input Voltage V IL -0. 0. V Input Leakage Current I I 0.0V < V I < V CC -.0.0 u A Active Current I CC V CC = Max; Period = Min. High Level Output Current I OH V CC = Min. V OH = Low Level Output Current I OL V CC = Min. V OL = 0. 0 0 ma -.0 ma ma AC ELECTRICAL CHARACTERISTICS (T A = C; V CC =.0V ± %) PARAMETER SYMBOL M TYP MAX UNITS NOTES Input Pulse Width t WI 0% of t PLH ns Input to Tap Delay (leading edge) t PLH Table ns,,, Input to Tap Delay (trailing edge) t PHL Table ns,,, Power-up Time t PU 00 ms Period (t WI ) ns CAPACITAE (T A = C) PARAMETER SYMBOL M TYP MAX UNITS NOTES Input Capacitance C 0 pf 09 /
NOTES:. All voltages are referenced to ground.. Measured with outputs open.. V CC = V @ C. Delays accurate on both rising and falling edges within ± ns or ±%, whichever is greater.. See Test Conditions.. The combination of temperature variations from C to 0 C or C to 0 C and voltage variations from.0v to.v or.0v to.v may produce an additional input-to-tap delay shift of ±. ns or ±%, whichever is greater.. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP slows down, all other taps will also slow down; TAP can never be faster than TAP.. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-sensitive (decoupling, layout, etc.). TERMOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following t WI (Pulse Width): The elapsed time on the pulse between the.v point on the leading edge and the.v point on the trailing edge, or the.v point on the trailing edge and the.v point on the leading edge. t RISE (Input Rise Time): The elapsed time between the 0% and the 0% point on the leading edge of the input t FALL (Input Fall Time): The elapsed time between the 0% and the 0% point on the trailing edge of the input t PLH (Time Delay, Rising): The elapsed time between the.v point on the leading edge of the input pulse and the.v point on the leading edge of any tap output t PHL (Time Delay, Falling): The elapsed time between the.v point on the trailing edge of the input pulse and the.v point on the trailing edge of any tap output TEST SETUP DESCRIPTION Figure illustrates the hardware configuration used for measuring the timing parameters on the DS00. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (0 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE bus. TEST CONDITIONS PUT: Ambient Temperature C ± C Supply Voltage (V CC ).0V ± 0.V Input Pulse High =.0V ± 0.V Low = 0.0V ± 0.V Source Impedance 0 ohm maximum Rise and Fall Time.0 ns maximum Pulse Width 00 ns Period µs OUTPUT: Each output is loaded with the equivalent of a F0 input gate. Delay is measured at the.v level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. 09 /
TIMG DIAGRAM: SILICON DELAY LE Figure PERIOD t RISE t FALL V IH V IL 0.V.V.V.V.V 0.V.V t WI t WI t PHL t PLH.V.V TAP DALLAS SEMICONDUCTOR TEST CIRCUIT Figure PULSE GENERATOR START Z O 0 TIP TIME TERVAL COUNTER STOP TIP (TIME TERVAL PROBE) DEVICE UNDER TEST VHF SWITCH CONTROL UNIT 09 /