EE273 Lecture 15 Asynchronous Design Novemer 16, 199 Willim J. Dlly Computer Systems Lortory Stnford University illd@csl.stnford.edu 1 Tody s Assignment Term Project see project updte hndout on we checkpoint 1 (signling components) due Wednesdy (11/1) checkpoint 2 (timing components) due on 11/25 Reding no new reding, complete Section 10.4 if you hven t lredy done so FYI meso- mens middle timing midwy etween sync nd sync? plesio- mens ner nerly mesochronous? 2 Copyright 199 y W. J. Dlly, ll rights reserved. 1
A Quick Overview Periodic Synchronizers clock prediction - looking into the future Asynchronous design most synchroniztion is unnecessry cn e voided y using synchronous design A stopple clock stop clock etween events strt clock when n input event occurs Comintionl synchronous modules inputs nd outputs encode events not just vlues modules oey the wek conditions numer of events on ech output is equl to or one less thn the numer of events on ech input Composition wek conditions re closed under cyclic composition 3 Periodic Timing Trnsmit nd receive clocks re periodic ut t unrelted frequencies e.g., modules in system operte off of seprte oscilltors with independent frequencies cse where one is rtionlly derived from the other is n interesting specil cse In this sitution, single synchroniztion won t lst forever (like mesochronous) or even for long time (like plesiochronous) However, we cn still look into the future nd predict clock conflicts fr enough hed to reduce synchronizer dely 4 Copyright 199 y W. J. Dlly, ll rights reserved. 2
Clock-Predictor Circuit Suppose we wnt to know the vlue of xclk, one rclk cycle (t rcy ) in the future This is just phse shift of t xcy -t rcy It is esy to generte this phse shift using simple timing loop Note tht we could just s esily predict xclk severl rclk cycles in the future So how do we uild synchronizer using this? xclk t rcy φc pxclk 5 Asynchronous Timing Sometimes we need to smple signl tht is truly synchronous We cn still move the synchroniztion out of the dtpth y using n synchronous FIFO synchronizer However this still incurs high ltency on the full nd empty signls s we hve to wit for rute force synchronizer to mke its decision We cn still void dely in this cse if we don t relly need to synchronize often synchroniztion is just n expensive convenience 6 Copyright 199 y W. J. Dlly, ll rights reserved. 3
Asynchronous Design Most often we synchronize just to lign n event to clock it doesn t relly mtter if we hndle the event on clock i or i+1 We cn void this unnecessry synchroniztion y processing events synchronously The rrivl of n event triggers its hndling 7 Exmple, A Stopple Clock Suppose our input is n synchronous -it signl We need to wit for 12 events on the input nd then output the verge vlue We could synchronize to locl clock on ech smple this is n exmple of unnecessry synchroniztion We could stop our clock nd restrt it on ech smple no proility of synchroniztion filure lower power in rin clk in rin sync Proc Proc clk sm out rout out rout Copyright 199 y W. J. Dlly, ll rights reserved. 4
Stopple Clock Circuit in Com Logic out done rin ASM go clk 9 Stopple Clocks Some Questions Wht do the wveforms on rin, go, clk, nd done look like? Where is rout generted? Wht re the constrints on input timing? On output timing? How do we design the ASM lock? 10 Copyright 199 y W. J. Dlly, ll rights reserved. 5
An Asynchronous Module To ensure correct design of synchronous circuits (nd to simplify verifiction) we need to impose some discipline on our designs We strt y specifying the properties of comintionl synchronous module some numer of inputs undled or dul-ril some numer of outputs undled or dul ril constrint on input nd output events r r ACL c rc 11 The Wek Conditions Inputs nd outputs trnsition in the following order 1. some input(s) ecome vlid 2. some output(s) ecome vlid 3. ll inputs ecome vlid 4. ll outputs ecome vlid 5. some input(s) ecome invlid 6. some output(s) ecome invlid 7. ll input(s) ecome invlid. ll output(s) ecome invlid So, for exmple it is not llowed for ny output to ecome vlid efore ny input ecomes vlid ll outputs to ecome vlid while ny input is invlid ny output to ecome invlid while ll inputs re vlid ll outputs to ecome invlid while ny input is vlid 12 Copyright 199 y W. J. Dlly, ll rights reserved. 6
The Wek Conditions Stte Digrm ssert siv iv reset sov ov sii ii two-phse soi oi four-phse 13 The Wek Conditions Some Questions Wht does it men for signl to e vlid or invlid? Which conditions pply to the circuit nd which pply to the environment? Is it sufficient for one output to lwys lg ll inputs? Wht do the wek conditions sy out the numer of events on ech input nd output? 14 Copyright 199 y W. J. Dlly, ll rights reserved. 7
The Wek Conditions Exmple: Self-Timed AND Gte Suppose we wnt to uild n synchronous AND gte using this discipline. inputs dul-ril Cn we just use n AND gte nd n OR gte? why not? Is the lower circuit OK? why? isn t it logiclly equivlent to the upper circuit? wht s different? 1 0 1 0 1 0 1 0 c1 c0 c1 c0 15 A Bundled Self-Timed AND Gte If the inputs re undled insted of dul ril, how do we generte undled output? A Muller C-element output follows input when oth inputs re equl This is n exmple of mtched-dely circuit dely of C element plus dely line must e dely of AND gte r r C c cr Output cr is n exmple of completion signl 16 Copyright 199 y W. J. Dlly, ll rights reserved.
A Mtched-Dely Full Adder Suppose we wnt to uild full dder with undled inputs using the mtcheddely design style Cn we generte fst crry nd still oey the wek conditions? C in A B S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 17 Mtched-Dely Full Adder First Attempt Does this work? Does it give good performnce? c in s c out r r cr in C C cr out sr 1 Copyright 199 y W. J. Dlly, ll rights reserved. 9
Mtched-Dely Full Adder with Fst Crry Does this work? Does it oey the wek conditions? Is there completion signl? c in g p s c out Under wht conditions is the crry fst? r r cr in C C 0 1 cr out sr 19 Composition of Asynchronous Modules The wek conditions re closed under cyclic composition An cyclic composition of modules tht oey the wek conditions lso oeys the wek conditions Only true if the circuit is fully connected Two independent prllel circuits do not oey the wek conditions Why is this true? 20 Copyright 199 y W. J. Dlly, ll rights reserved. 10
Exmple, An Asynchronous Adder Ech line here represents two wires: vlue nd request Wht is the verge dely of this dder with the first full dder design? the second? Is there completion signl? If not how could we generte one? Cn we fctor out some of the mtched-dely completion logic? 31 31 1 1 0 0 c out c in c out c in c out c in s c31 c2 c1 s s c32 s31 s1 s0 c0 21 Next Time Asynchronous Stte Mchines Asynchronous Pipelines Itertive Asynchronous Circuits 22 Copyright 199 y W. J. Dlly, ll rights reserved. 11