EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced VLSI Design at Cornell University Amirtharajah/Parkhurst, EEC 8 Spring 0
Outline Review: CMOS Inverter Transfer Characteristics CMOS Inverters: Rabaey 5.4-5.5 (Kang & Leblebici, 6.-6.4, 6.7) Amirtharajah/Parkhurst, EEC 8 Spring 0 4
CMOS Inverter VTC: Device Operation P linear N cutoff P cutoff N linear P linear N sat P sat N sat P sat N linear Amirtharajah/Parkhurst, EEC 8 Spring 0 5
Logic Circuit Delay For CMOS (or almost all logic circuit families), only one fundamental equation necessary to determine delay: I C Consider the discretized version: Rewrite to solve for delay: dv Only three ways to make faster logic: C, ΔV, I dt Δt I C C ΔV I ΔV Δt Amirtharajah/Parkhurst, EEC 8 Spring 0 6
Vin CMOS Inverter Capacitances Cgs,p Cgd,p Cgd,n Vdd Csb,p Cdb,p Cdb,n Cgs,n Csb,n Gnd f Cint Amirtharajah/Parkhurst, EEC 8 Spring 0 7 Cg Assume input transition is fixed, then delay determined by output Capacitance on node f (output): Junction cap Cdb,p and Cdb,n Gate capacitance Cgd,p and Cgd,n Interconnect cap Receiver gate cap
CMOS Inverter Junction Capacitances Junction capacitances C db,p and C db,n : C j Equation for junction cap: ( ) V AC V φ0 N N j0 εq a d, C m j0 N a + N d φ0 m Non-linear, depends on voltage across junction Use K eq factor to get equivalent capacitance for a voltage transition C AK C + db eq j PK eqsw C jsw Amirtharajah/Parkhurst, EEC 8 Spring 0 8
CMOS Inverter Gate Capacitances Gate capacitances C GD,p and C GD,n : Just after the input switches(t 0 + ), what regions are transistors in? One is in cutoff: C GD Overlap Cap One is in Saturation: C GD Overlap Cap Therefore, gate-to-drain capacitance is due to overlap capacitance : C gd, p Cgd, n C ox WL D However, also need to consider Miller effect... Amirtharajah/Parkhurst, EEC 8 Spring 0 9
CMOS Inverter Capacitances: Miller Effect C gd Vout Vout Vin Vin C gd When input rises by ΔV, output falls by ΔV Change in stored charge: ΔQ C gd ΔV (-C gd ΔV) Effective voltage change across C gd is ΔV Effective capacitance to ground is twice C gd Including Miller effect: C C C WL (For transistor in Cutoff) gd, p gd, n ox D Amirtharajah/Parkhurst, EEC 8 Spring 0 0
CMOS Inverter Capacitances: Receiver Receiver gate capacitance Includes all capacitances of gate(s) connected to output node Unknown region of operation for receiver transistor: total gate cap varies from (/3)WLC ox to WLC ox Ignore Miller effect (taken into account on output) Assume worst-case value, include overlap C WL C + WL g eff ox D C ox C g WL C ox Amirtharajah/Parkhurst, EEC 8 Spring 0
Inverter Capacitances: Analysis Simplify the circuit: combine all capacitances at output into one lumped linear capacitance: C load *Cgd,n + *Cgd,p + Cdb,n + Cdb,p + Cint + Cg Miller effect Csb,n Csb,p 0 Cgs,n and Cgs,p are not connected to the load. These are part of the gate capacitance Cg Amirtharajah/Parkhurst, EEC 8 Spring 0
First-Order Inverter Delay Suppose ideal voltage step at input Assume: Current charging or discharging capacitance C load is nearly constant I avg t PHL C load (Vdd - Vdd/) / I avg Vin Vout C load t PLH C load (Vdd/ - Vss) / I avg Amirtharajah/Parkhurst, EEC 8 Spring 0 3
Inverter Delay: Falling Vin I D.n C load Assume PMOS fully off (ideal step input, I D,p 0) I I C D n dv dt C load dv dt out, Need to determine I D,n Amirtharajah/Parkhurst, EEC 8 Spring 0 4
Inverter Delay: Falling Vdd Vdd - Vtn NMOS in saturation NMOS in linear region Vdd/ t 0 t t From t 0 to t : NMOS in saturation From t to t : NMOS in linear region Find I D in each region Amirtharajah/Parkhurst, EEC 8 Spring 0 5
Inverter Delay: Falling t -t 0 Assumption: Input fast enough to go through transition before output voltage changes V out drops from V to V DD -V TN (NMOS saturated) I DS k n ( V in V T 0, n ) / k n ( V V T 0, n ) / t t t 0 dt t 0 k n ( V k n ( V CL V C V L T 0, n T 0, n V ) T 0, n ) V V V T 0, n dv out Amirtharajah/Parkhurst, EEC 8 Spring 0 6
I t t DS Inverter Delay: Falling t -t V out drops from (V -V T0,n ) to V DD / NMOS in linear region t t k n [ ( ) ] V V V V C k n L ( V ( V V + V V T 0, n OL CL V )/ T 0, n T 0, n k out n [ ( ) ] V V V V out ( V ln ) dv T 0, n out V ( V out T 0, n ) ( V + V OL out )/ + V OL )/ Amirtharajah/Parkhurst, EEC 8 Spring 0 7
Inverter Delay: Falling, Total Total fall delay (t -t 0 ) + (t -t ) t PHL C V T 0, n 4( V V ) L T 0, n + ln k ( ) + n V VT 0, n V VT 0, n V VOL Amirtharajah/Parkhurst, EEC 8 Spring 0 8
t PLH Inverter Delay: Rising Similar calculation as for falling delay Separate into regions where PMOS is in linear, saturation C V T 0, p 4( V VOL V ) L T 0, p + ln k ( ) + p V VOL VT 0, p V VOL VT 0, p V VOL Note: to balance rise and fall delays (assuming V V DD, V OL 0V, and V T0,n V T0,p ) requires k k p n.5 Amirtharajah/Parkhurst, EEC 8 Spring 0 9 W L W L p n μn μ p
Inverter Rise, Fall Times Summary -- Exact method: separate into two regions t V drops from 0.9V out DD to V DD -V T,n (NMOS in saturation) V out rises from 0.V DD to V T,p (PMOS in saturation) t V drops from V out DD -V T,n to 0.V DD (NMOS in linear region) V out rises from V T,p to 0.9 V DD (PMOS in linear region) t f,r t + t Amirtharajah/Parkhurst, EEC 8 Spring 0 0
Review of approximate method CMOS Inverter Delay Assume a constant average current for the transition V Vdd I I avg average of drain V ½Vdd current at beginning and end of transition I t t PHL PLH C I C I load avg load avg ( V V ) DD ( V V ) DD DD SS t t I avg ½(I +I ) Amirtharajah/Parkhurst, EEC 8 Spring 0
CMOS Inverter Delay: nd Approximation Another approximate method: Again assume constant I avg I avg current I at start of transition t t PHL PLH k k n p C load ( V V ) C DD load ( V V ) DD V V DD Tn DD TP Why is this a good approximation (esp. for deep submicron)? V Vdd V ½Vdd I t t I avg I Amirtharajah/Parkhurst, EEC 8 Spring 0
CMOS Inverter Delay: Finite Input Transitions What if input has finite rise/fall time? Both transistors are on for some amount of time Capacitor charge/discharge current is reduced Empirical equations: t phl (ns) t rise (ns) t t tr phl ( actual) t phl ( step) + ( f ) ( ) plh actual t plh step + t Amirtharajah/Parkhurst, EEC 8 Spring 0 3
How to Improve Delay? Minimize load capacitances Small interconnect capacitance Small Cg of next stage Raise supply voltage Increases current faster than increased swing ΔV Increase transistor gain factor Increase transistor drive current for charging/discharging output capacitance Use low threshold voltage devices More subthreshold leakage power dissipation Amirtharajah/Parkhurst, EEC 8 Spring 0 4
Inverter Power Consumption Static power consumption (ideal) 0 Actually DIBL (Drain-Induced Barrier Lowering), gate leakage, junction leakage are still present Dynamic power consumption P P avg avg / T dv T out Vout Cload dt + DD out load T dt dt 0 T / T / T V out Cload + VDDVoutCload CloadVout T 0 T Pavg CloadVDD CloadVDD f T P avg T T 0 ()() t i t dv out ( V V ) C dt Amirtharajah/Parkhurst, EEC 8 Spring 0 5 v dt /
Next Time: Combinational Logic Combinational MOS Logic DC Characteristics, Equivalent Inverter method AC Characteristics, Switch Model Amirtharajah/Parkhurst, EEC 8 Spring 0 6