IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Design &Implementation 16-Bit Low Full Adder using Reversible Logic Gates Patel Fenil S. 1 Tarunkumar C. Lad 2 1 M. Tech (Purs.) 2 M. Tech 1 CGPIT, Maliba Campus, UTU 2 SVNIT, SURAT Abstract---Everyday new technology which is faster, smaller and more complex than its predecessor is being developed. The increase in clock frequency to achieve greater speed and increase in number of transistors packed onto a chip to achieve complexity of a conventional system results in increased power consumption. Almost all the millions of gates used to perform logical operations in a conventional computer are irreversible. Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. That is, every time a logical operation is performed some information about the input is erased or lost and is dissipated as heat. Reversible logic is one of the latest technologies having promising applications in Quantum Computing. Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, Nanocomputing and optical computing. Reversible logic gates are widely known to be compatible with future computing technologies which virtually dissipate zero heat. Reversible logic gates produce zero power dissipation. So these can be used forlow power VLSI design. Adders are fundamental building blocks in many computational units. For this reason, we have simulated several adder circuits using the reversible gates. This paper implements a design of Adder using reversible logic gates. This paper proposes a new 16- bit reversible adder using 4*4 Reversible DKG gates that can work singly as a reversible full adder. Keywords: Reversible logic, Reversible gates, Quantum Computer, dissipation, Garbage, Full Adder. I. INTRODUCTION The advancement in higher-level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. This trend of reduction of heat in computation also has its physical limit according to Landauer, who proved that in logic computation every bit of information loss generates ktln2 joules [2] of heat energy, where k is Boltzmann's constant of 1.38xlO-23J/K, and T is the absolute temperature of the environment. At room temperature, the dissipating heat is around 2.9 x 10-21 1. Energy loss by Landauer limit is important because it is likely that the growth of heat generation due to information loss will be noticeable in future. Bennett showed that zero energy dissipation would be possible if the network consists of reversible gates only. Reversible logic has also found its applications in several disciplines such as quantum computing, nanotechnology, DNA technology and optical computing. In modern VLSI systems power dissipation is very high due to rapid switching of internal signals. The paper is organized as follows. In 1973, C. H. Bennett [4, 5] concluded that no energy would be dissipated from a system as long as the system was able to return to its initial state from its final state regardless of what occurred in between. It made clear that, for power not to be dissipated in the arbitrary circuit, it must be built from reversible gate. Reversible circuits are of particular interest in low power CMOS VLSI design. II. REVERSIBLE LOGIC A gate is considered to be reversible only if for each distinct input there is a distinct output assignment. Thus inputs to reversible gates can be uniquely determined from its outputs. A reversible logic gate must have the same number of inputs and outputs [6]. In an n-output reversible gate the output vectors are permutation of the numbers 0 to 2n-1. A reversible gate is balanced, i.e. the outputs are is for exactly half of the inputs. A circuit without constants on its inputs and composed of reversible gates realizes only balanced functions. It can realize non balanced functions only with garbage outputs. Some of the major problems with reversible logic synthesis are fan outs cannot be used, and also feedbacks from gate outputs to inputs are not permitted. [6] Features for any gate to become reversible gate as follows: [7] Number of input and output lines must be the same. Feedback (loop) is not allowed in reversible logic. Fan-out is not allowed in reversible logic; Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed. One of the major constraints in reversible logic is to minimize the number of reversible gates used. Minimizing the garbage outputs produced; Garbage output refers to the output that is not used for further computations. Garbage is the number of outputs added to make an n-input k output Boolean function (n,k) function reversible Using minimum number of input constants. III. LITERATURE REVIEW (1) R. Landauer s showed, the amount of energy (heat) dissipated for every irreversible bit operation is given by KT ln2, where K is the Boltzmann s constant (1.3807 10-23 JK-1) and T is the operating temperature. At room temperature (300 K), KT ln2 is approximately 2.8 10-21 J, which is small but not negligible. He also showed that only the logically irreversible steps in a computation carry an unavoidable energy penalty. If we could compute entirely with All rights reserved by www.ijsrd.com 977
reversible operations, there would be no lower limit on energy consumption [8]. (2) Bennett showed that ktln2 energy dissipation would not occur, if a computation is carried out in a reversible way, since the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation [4]. (3) Yvan Van Rentergem and Alexis De Vos presented four designs for Reversible full-adder circuits and the implementation of these logic circuits into electronic circuitry based on CMOS technology and passtransistor design [9]. (4) Lihui Ni, Zhijin Guan, and Wenying Zhu described general approach to construct the Reversible full adder and can be extended to a variety of Reversible full adders with only two Reversible gates [10] (5) Bruce, J.W., M.A. Thornton, L. shivakuamaraiah, P.S. kokate and X. Li, used only Fredkin gates to construct full adder with gates cost equal to 4, 3 garbage outputs and 2 constant input [11]. (6) In this paper, a design constructing the Arithmetic Logic Unit (ALU) based on reversible logic gates as logic components is proposed. The presented reversible ALU reduces the information bits use and loss by reusing the logic information bits logically and realizes the goal of lowering power consumption [12]. B. CNOT Gate CNOT gate is also known as controlled-not gate. It is a 2*2 reversible gate. The CNOT gate can be described as: I/p = (A, B); o/p = (P= A, Q= A B) Quantum cost of CNOT gate is 1[9]. Fig. 2 shows a 2*2 CNOT gate and its symbol [1]. C. TOFFOLI Gate Fig. 2: CNOT Gate TOFFOLI gate shown in fig. 3 which is a 3*3 gate with inputs (A, B, C) and outputs P=A,Q=B, R=AB XOR C. It has Quantum cost five [1]. IV. BASIC REVERSIBLE LOGIC GATES It is an n-input n-output logic function in which there is a one-to-one correspondence between the inputs and the outputs. Because of this objective mapping the input vector can be uniquely determined from the output vector. This prevents the loss of information which is the root cause of power dissipation in irreversible logic circuits. In the design of reversible logic circuits the following points must be considered to achieve an optimized circuit. Now we define some popular reversible gates formally, those that are needed in our research, with appropriate figures, examples and their cost. Some of the important reversible logic gates are, A. NOT Gate The simplest Reversible gate is NOT gate and is a 1*1 gate [9]. The Reversible 1*1 gate is NOT Gate with zero Quantum Cost is as shown in the Fig.1 [1]. Fig. 3: Toffoli Gate A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 Table. 2: 3x3 Toffoli Gate D. FEYNMAN Gate The Feynman gate shown in fig. 4 which is a 2*2 gate and is also called as Controlled NOT and it is widely used for fanout purposes. The inputs (A, B) and outputs P=A, Q= A XOR B. It has Quantum cost one [1]. Fig. 1: NOT Gate A P 0 1 1 0 Table. 1: 1 x 1 NOT Gate Fig. 4: Feynman Gate All rights reserved by www.ijsrd.com 978
A B P Q 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 Table. 3: 2 x 2 Feynman Gate G. DKG gate DKG gate shown in fig. 7 which is a 3*3 gate having inputs (A,B,C) and outputs P = B; Q = A`C+AD`; [1] R = (A XOR B)(C XOR D) XOR CD; S = B XOR C XOR D. E. FREDKIN Gate Fredkin gate shown in fig. 5 which is a 3*3 gate with inputs (A, B, C) and outputs P=A, Q=A'B+AC, R=AB+A'C. It has Quantum cost five [1]. F. PERES Gate Fig.5: Fredkin Gate A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 Table. 4: 3 x 3 Ferdkin Gate Peres gate shown in fig. 6 which is a 3*3 gate having inputs (A, B, C) and outputs P = A; Q = A XOR B; R = AB XOR C. It has Quantum cost four [1]. Fig. 7: Reversible DKG gate Fig. 8: DKG gate implemented as Full adder V. DESIGN OF DKG GATE A. Inputs Here we implement 4-bit full adder. Thus the inputs are 4 bits. Three input vectors and a single bit Cin. Two of the three input vectors are added 4-bits values. The remaining vector could be called the ancilla vector which is filled with zeros. Fig. 6: Peres Gate A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 Table. 5 : 3 x 3 Peres Gate B. Outputs The outputs of the system are one garbage vector of 8 bits, one sum vector of 4 bits and a Cout (Carry out) bit. C. Design Theory First of all, we need to know that in order to build a reversible circuit we must use reversible gates [14].There are different ways to implement a reversible adder. These different implementations depend on a balance between gates count, garbage outputs, and ancilla bits. Being universal, these previously presented gates can implement any logical function and therefore they can also implement the well-known functions for a full-adder: All rights reserved by www.ijsrd.com 979
5) RTL Design view: A. Fig. 9: DKG Traditional Logic implementation VI. DESIGN & COMPARE 16-BIT FULL ADDER USING DKG REVERSIBLE GATES & 16-BIT SIMPLE FULL ADDER 16-bit full adder using DKG reversible gates Fig. 11: RTL view 6) Result for Behavior Simulation: Fig. 12: Result for 16 Bit Full adder using DKG gate 7) Result for Post Routing: Fig. 10: 16-bit Full Adder using DKG Reversible Gates 1) Device utilization summary: Selected Device: 5vlx30ff324-3 2) Slice Logic Utilization: Number of Slice LUTs: 25 out of 19200 0% Number used as Logic: 25 out of 19200 0% 3) Slice Logic Distribution: Number of LUT Flip Flop pairs used: 25 Number with an unused Flip Flop: 25 out of 25 100% Number with an unused LUT: 0 out of 25 0% Number of fully used LUT-FF pairs: 0 out of 25 0% Number of unique control sets: 0 4) IO Utilization: Number of IOs: 98 Number of bonded IOBs: 82 out of 220 37% Fig. 13: 16-Bit Full adder using DKG gate for post routing 8) Result for power analysis: Fig. 14: X-power Analyzer All rights reserved by www.ijsrd.com 980
B. 16-Bit Full Adder Using simple gates Design &Implementation 16-Bit Low Full Adder using Reversible Logic Gates 3) Result for Behavior Simulation: Fig. 15: 16-bit Full Adder Using Simple logic Gates Fig. 18: Result for 16 Bit Full adder using simple logic gates 4) Result for Post Routing: Fig. 16: Full Adder Circuit Where, S = A XOR B XOR Cin Cout = (A OR B) + (Cin OR (A XOR B)) 1) Device utilization summary: Selected Device: 5vlx30ff324-3 a) Slice Logic Utilization: Number of Slice LUTs: 25 out of 19200 0% Number used as Logic: 25 out of 19200 0% b) Slice Logic Distribution: Number of LUT Flip Flop pairs used: 25 Number with an unused Flip Flop: 25 out of 25 100% Number with an unused LUT: 0 out of 25 0% Number of fully used LUT-FF pairs: 0 out of 25 0% Number of unique control sets: 0 c) IO Utilization: Number of IOs: 50 Number of bonded IOBs: 50 out of 220 22% 2) RTL Design view: Fig. 17: RTL view Fig. 19: Result for 16 Bit Full adder using simple logic gates for post-routing 5) Result for power analysis: Fig. 20: X-power Analyzer Reversible Logic Gates Simple Logic Gates Quiescent 0.38870(w) Quiescent 0.38664(w) Dynamic 0.10274(w) Dynamic 0.03633(w) 0.49144(w) 0.42297(w) Junction Temp. 53.2(degrees C) Junction Temp. 52.8(degrees C) Table. 6: compare total power for both circuit VII. APPLICATION Reversible computing may have applications in computer security and transaction processing, but the main long-term benefit will be felt very well in those areas which require high energy efficiency, speed and performance.it include the area like Low power CMOS Optical computing, Quantum computer Nanotechnology All rights reserved by www.ijsrd.com 981
Design of low power arithmetic and data path for digital signal processing (DSP) Field Programmable Gate Arrays (FPGAs) in CMOS technology for extremely low power, high testability and self-repair. CONCLUSION AND ACKNOWLEDGMENT We have presented an approach to the realize the multipurpose binary reversible gates. Such gates can be used in regular circuits realizing Boolean functions. In the same way it is possible to construct multiple-valued reversible gates having similar properties. We present a new efficient 16-Bit Reversible Full Adder using DKG gate which is implemented in VHDL. We can simulate and synthesis it using Xilinx software and also calculate the power consumption. Here we present Result of Behavior, Post routing Simulation. And last analysis of 16-Bit Full adder. 16-Bit Reversible Full Adder using DKG gate which is implemented in VHDL. The paper can further be extended towards the digital design development using reversible logic circuits which are helpful in quantum computing, low power CMOS, nanotechnology, cryptography, optical computing, communication, computer graphics. Here we compare 16-Bit Reversible Full Adder & 16-bit Simple Full Adder, and we get total power. For Reversible Full Adder it`s 0.49144 (w) and for Simple Full adder it`s 0.42297 (w).so, finally we get 0.06847 (w) power from Reversible Full adder. REFERENCES [1] Patel Fenil S., Tarunkumar C. Lad, VHDL Implementation of 4-Bit Full Adder Using Reversible Logic Gates, IJSRD - International Journal for Scientific Research & Development Vol. 1, Issue 10, 2013 ISSN (online): 2321-0613. [2] C H Bennett, "Notes on the History of Reversible Computation", IBM Journal of Research and Development, vol. 32, pp. 16-23, 1998. [3] William C. Athas, Lars J,Svensson, Jeffrey G. koller, Nestoras Tzartzanis, and Eric Ying Chin Chou, Lowpower Digital Systems based on Adiabatic-Switching principle, IEEE Transactions on VLSI systems, Vol. 2, No. 4, December 1994. [4] C.H. Bennett, Logical Reversibility of Computation, IBM J.Research and Development, pp. 525-532, November 1973. [5] Majid Haghparast and Keivan Navi, "A novel Reversible BCD Adder For Nanotechnology Based Systems" Islamic Azad University, Science and Research Branch, American Journal of Applied Sciences 5 (3): 282-288, 2008 ISSN 1546-9239. [6] P.K.LALA, J.P.PARKERSON, P.CHAKRABORTY Adder Designs using Reversible Logic Gates Electrical Engineering Department, Texas A&M University-Texarkana, Texas 75503,USA Computer Science and Computer Engineering Department, University of Arkansas, Fayetteville, Arkansas, 72701, USA WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Issue 6, Volume 9, June 2010. [7] Maii T. Emam, Layle A. A. Elsayed, Reversible Full Adder/Subtractor Computer System Engineering Department, Faculty of Engineering, Alexandria University Alexandria, Egypt. 2010 11 th International Workshop on Symbolic and Nurnerical Methods, Modeling and Applications to Circuit Design (SM2ACD). [8] R. Landauer, Irreversibility and Heat Generation in the Computational Process, IBM Journal of Research and Development, 5, pp. 183-191, 1961. [9] Yvan Van Rentergem and Alexis De Vos, Optimal Design of a Reversible Full Adder, International Journal of Unconventional Computing, vol. 1, pp. 339 355, 2005. [10] Lihui Ni, Zhijin Guan, and Wenying Zhu, A General Method of Constructing the Reversible Full-Adder, Third International Symposium on Intelligent Information Technology and Security Informatics, pp.109-113, 2010. [11] Bruce, J.W., M.A. Thornton, L. shivakuamaraiah, P.S. kokate and X. Li, Efficient adder circuits based on a conservative reversible logic gate, IEEE computer society Annual symposium on VLSI, Pittsburgh, Pennsylvania, and pp.: 83-88, 2000. [12] Zhijin Guan, Wenjuan Li, Weiping Ding, Yueqin Hang, and Lihui Ni, An Arithmetic Logic Unit Design Based on Reversible Logic Gates, Communications, Computers and Signal Processing (PacRim)v, pp.925-931, 03 October 2011. [13] Perkowski, M. 2000. Reversible Computation for Beginners. Lecture Series. [14] Hafiz Md. Hasanbabu, Md. Rafiqu Islam, Ahsan Raja Chowdhary and Syed Mostahead Ali chowdhary Reversible logic synthesis for minimization of full adder ckt, IEEE conference on Digital system design 2003,Enro-micro 03, Belek,Antalya,Tarkey,2003,PP 50-54. All rights reserved by www.ijsrd.com 982