Chap 2. Combinational Logic Circuits

Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization Map Manipulation Multi-Level Circuit Optimization Part 3 Additional Gates and Circuits Other Gate Types Exclusive-OR Operator and Gates High-Impedance Outputs Overview 3 2. Binary Logic and Gates 4 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization Map Manipulation Multi-Level Circuit Optimization Part 3 Additional Gates and Circuits Other Gate Types Exclusive-OR Operator and Gates High-Impedance Outputs Digital circuits hardware components that manipulate binary information implemented using transistors and interconnections in IC each basic circuit is called logic gate performs a specific logical operation Boolean Algebra mathematical notation to specify the operation of each gate used to analyze and design circuits Combinational Logic 5 2. Binary Logic and Gates 6 logic gate and, or, not, nand, nor, xor, xnor, logic gate, gate n 2 n 3) NOT Z = X' (Z is equal to NOT X) (state). -- complement operation ( => & => ) adder, subtracter, multiplier, comparator, code converter, encoder, decoder, multiplexer, demultiplexer Binary Logic take on two discrete values & with the operations of mathematical logic three logical operations ) AND Z = X Y (Z is equal to X and Y) 2) OR Z = X + Y (Z is equal to X or Y) AND/OR is similar to multiplication/addition

2. Binary Logic and Gates 7 2. Binary Logic and Gates 8 logical OR logical AND logical NOT + = = ' = + = = ' = + = = + = = Logic Gates electronic circuits that operate on one or more input signals to produce an output signal voltage operated circuits: logic & logic intermediate region is crossed during state transition 9 2.2 Boolean Algebra Multi-input input Gates Boolean function deals with binary variables and logic operation symbols with three basic logic operations AND, OR, NOT express logical relationship between binary variables F = X + Y' Z Consider F = X + Y' Z represented in a truth table transformed from an algebraic expression into a circuit diagram composed of logic gates (Fig 2.3) 2.2 Boolean Algebra 2.2 Boolean Algebra 2 Basic Identities of Boolean Algebra AB + C + = (by identity 3) most basic identities of Boolean algebra commutative laws -- the order doesn't affect the result dual - obtained by interchanging OR and AND, and replacing 's by 's and 's by 's X + Y = Y + X, X Y = Y X associative laws -- parentheses can be removed altogether X + (Y + Z) = (X + Y) + Z = X + Y + Z X (Y Z) = (X Y) Z = X Y Z distributive laws (dual) X + Y Z = (X + Y) (X + Z) (A + B) (A + CD) =? DeMorgan's theorem -- obtain complement of an expression (X + Y)' = X' Y' (X Y)' = X' + Y (Table 2.4) can be extended to three or more variables Table 2-3. Basic Identities of Boolean Algebra (A + B + C +... )' = A' B' C'...

2.2 Boolean Algebra 3 2.2 Boolean Algebra 4 Algebraic Manipulation Boolean algebra is a useful tool for simplifying digital circuits F = X'YZ + X'YZ' + XZ = X'Y (Z+Z') + XZ = X'Y + XZ = X'Y + XZ compare two implementations in Fig 2.4 use truth table to verify two expressions (Table 2.5) manipulate Boolean algebra lower terms, literals obtain a simpler circuit popular tools. X + XY = X ( + Y) = X 2. XY + XY' = X (Y + Y') = X 3. X + X'Y = (X + X') (X + Y) = X + Y 4. X (X + Y) = X + X Y = X ( + Y) = X 5. (X + Y)(X + Y') = X + YY' = X 6. X (X' + Y) = XX' + XY = XY consensus theorem XY + X'Z + YZ = XY + X'Z (prove it!) dual (X+Y)(X'+Z)(Y+Z) = (X+Y)(X'+Z) (Ex) (A+B)(A'+C) = AA' + AC + A'B + BC = AC + A'B + BC = AC + A'B 2.2 Boolean Algebra 5 2.3 Standard Forms 6 Complement of a Function obtained from an interchange of 's to 's and 's to 's derived algebraically by applying DeMorgan's theorem (Ex 2.) Find the complement of F = X'YZ' + X'Y'Z F' = (X'YZ' + X'Y'Z)' = (X'YZ')' (X'Y'Z)' = (X + Y' + Z) (X + Y + Z') facilitate the simplification procedures for Boolean expression contain product terms (XY'Z) and sum terms (X+Y+Z') Minterms & Maxterms minterm (a product term) & maxterm (a sum term) all the variables appear exactly once show exactly one combination of the binary variables in a truth table 2 n distinct terms for n variables (Ex 2.2) Find the complement of F = X'YZ' + X'Y'Z by taking dual and complementing each literal (Ex) 4 minterms for 2 variables X & Y X'Y', X'Y, XY', & XY dual of F (X' + Y + Z') (X' + Y' + Z) comp of each literal (X + Y' + Z) (X + Y + Z') 2.3 Standard Forms 7 2.3 Standard Forms 8 m j (minterm) -- complemented if the bit is uncomplemented if the bit is M j (maxterm) -- complemented if the bit is uncomplemented if the bit is j denotes the binary number of the term Table 2-6. Minterms for 3 Variables minterm: having the minimum No of 's in its truth table maxterm: having the maximum No of 's in its truth table a minterm and maxterm with the same subscript are complements of each other (M j = m j ') (Ex) (m 3 )' = ( X' Y Z )' = X + Y' + Z' = M 3 Table 2-7. Maxterms for 3 Variables

2.3 Standard Forms 9 2. 3 Standard Forms 2 a Boolean function can be expressed by a sum of minterms (Ex) Table 2-8(a) F = X'Y'Z'+X'YZ'+XY'Z+XYZ = m+m2+m5+m7 F(X,Y,Z) = Σ m(,2,5,7) (Σ = logical sum, Boolean OR) F' = X'Y'Z+X'YZ+XY'Z'+XYZ' = m+m3+m4+m6 F(X,Y,Z)' = Σ m(,3,4,6) F = (m+m3+m4+m6)' = m m3' m4' m6' = M M3 M4 M6 = (X+Y+Z') (X+Y'+Z') (X'+Y+Z) (X'+Y'+Z) F(X,Y,Z) = Π M(,3,4,6) (Π: logical product, Boolean AND) summary of minterms (p44) a function can be converted to the sum of minterms form by means of a truth table X Y Z F (Ex) E = Y' + X'Z from the truth table, E(X,Y,Z) = Σ m(,,2,4,5) E(X,Y,Z)' = Σ m(3,6,7) (the total number of minterms in E and E' is 8) G(X,Y) = Σm(,,2,3) = 2.3 Standard Forms 2 2.3 Standard Forms 22 Sum of Products a standard algebraic expression obtained directly from a truth table (sum of minterms) & simplify the expression to sum-of-products form (Ex) F = AB + C(D+E) (three-level) => AB + CD + DE (two-level) two-level implementation is preferred for its delay time (Ex) F = Y' + X'YZ' + XY three product terms -- two AND gates, one OR gate two-level implementation 2.3 Standard Forms 23 Overview Product of Sums another standard algebraic expression obtained by forming a logical product of sum terms (Ex) F = X(Y'+Z)(X+Y+Z') needs 2 OR gates and one AND gates Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization Map Manipulation Multi-Level Circuit Optimization Part 3 Additional Gates and Circuits Other Gate Types Exclusive-OR Operator and Gates High-Impedance Outputs

Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm Optimization requires a cost criterion to measure the simplicity of a circuit Two distinct cost criteria we will use: Literal cost (L) Gate input cost (G) Gate input cost with NOTs (GN) Literal Cost Literal a variable or it complement Literal cost the number of literal appearances in a Boolean expression corresponding to the logic circuit diagram Examples: F = BD + A BC + A CD L = 8 F = BD + A BC + A B D+ AB C L = F = (A + B)(A + D)(B + C + D)( B + C + D) L = Which solution is best? Gate Input Cost Gate input costs - the number of inputs to the gates in the implementation corresponding exactly to the given equation or equations. (G - inverters not counted, GN - inverters counted) For SOP and POS equations, it can be found from the equation(s) by finding the sum of: all literal appearances the number of terms excluding terms consisting only of a single literal,(g) and optionally, the number of distinct complemented single literals (GN). Example: F = BD + A BC + A C D G = 8, GN = F = BD + A BC + A B D + AB C G =, GN = F = (A + B)(A + D)(B + C + D)( B + C + D) G =, GN = Which solution is best? Cost Criteria (continued) Example : GN F = A + B C + B C L = = 5 G + 2 = 9 G = L + 2 = 7 B C A F L (literal count) counts the AND inputs and the single literal OR input. G (gate input count) adds the remaining OR gate inputs GN(gate input count with NOTs) adds the inverter inputs Cost Criteria (continued) 2.4 2-level 2 Circuit Optimization 3 Example 2: A B F = A B C + ABC C L = 6 G = 8 GN = F = (A + C)( B + C)( A + B) L = 6 G = 9 GN = 2 Same function and same A literal cost B But first circuit has better C gate input count and better gate input count with NOTs Select it! F F Karnaugh map (K-map) to simplify Boolean functions of up to 4 variables (5 or 6 variables can be drawn, but cumbersome to use) a diagram of squares, each representing one minterm simplified expressions are in sum-of-products or product-of-sums two-level implementations Example 2-level SOP 2-level POS

2.4 Map Simplification 3 2.4 Map Simplification 32 Two-Variable Map Three-variable Map four minterms for a Boolean function with 2 variables 8 minterms for 3 variables (Ex) Ex2.3 F(X,Y,Z) = Σ m(2,3,4,5) m+m2+m3 = X'Y+XY'+XY = X+Y (by algebra) => X'Y+X(Y'+Y) = X'Y+X = X+Y (from K-map) F = X'Y + XY' 2.4 Map Simplification 33 2.4 Map Simplification 34 (Ex) Ex2.4 F(X,Y,Z) = Σ m(3,4,6,7) F2(X,Y,Z) = Σ m(,2,4,5,6) (Ex) (Ex) (Ex) F2(X,Y,Z) = Σ m(,3,4,5,6) = X'Z + XZ' + XY' or = X'Z + XZ' + Y'Z m+m2+m4+m6 = Z' m+m+m2+m3+m6+m7 = X' + Y 2.4 Map Simplification 35 2.4 Map Simplification 36 Four-variable Map 6 minterms for 4 variables Ex2.5 F(W,X,Y,Z) = Σ m(,,2,4,5,6,8,9,2,3,4) F = Y' + W'Z' + XZ' Ex2.6 F = A'B'C' + B'CD' + A'BCD' + AB'C' F = B'D' + B'C' + A'CD'

2.5 Map Manipulation 37 Implicant 38 Combining squares ensure that all minterms of the functions are included necessary to minimize the number of terms Essential Prime Implicants implicant A product term is an implicant of a function F if that product term=, then the function F= if the function has the value for all minterms of the product term Ex) F=AB+BC+AB C implicant. AB, BC, AB C are implicants of F ABC, ABC, A BC (minterms) are also implicants of F AC (product term, nonminterm) is also implicant of F : product term AC= (A,B,C) (,,) (,,) F=., F(,,)=, F(,,)=. AC implicant. 2: product term AC minterm ABC AB C minterm F=. AC implicant. Therefore, the total numer of implicants of F are 7. Prime implicant 39 Essential prime implicant 4 prime implicant if the removal of any literal from an implicant results in a product term that is not an implicant of F a product term obtained by combining the maximum possible number of adjacent squares in the map Ex) F=AB+BC+AB C prime implicant. AB, BC, AB C, A BC, ABC, ABC, AC are implicants AB is prime implicant of F prime implicant 2 m (m=,,2,.,n) essential prime implicant If a minterm of a function F is included in only one prime implicant, that prime implicant is said to be essential prime implicant. Ex) F=AB+BC+AB C essential prime implicant. delete B A minterm of A=(,,) But, F(,,)= A is not an implicant of F. Thus AB is prime implicant of F. AB C is not prime implicant of F delete B AC AC= F=, AC=implicant AC is prime implicant of F delete A C (,,) But, F(,,)= How about BC, A BC, ABC, ABC? Prime Implicant Groups() 4 Prime Implicant Groups(2) 42 (a) (b) (c) (d) Prime Implicant Groups that involve (a) one, (b) two Prime Implicant Groups that involve (c) four, (d) eight

Example 43 Essential Prime Implicants 44 F2(X,Y,Z) = Σ m(,3,4,5,6) = X'Z + XZ' + XY' or = X'Z + XZ' + Y'Z (a) (b) (a) Prime Implicant Groups, (b) Essential Prime Implicant Groups Essential Prime Implicants 45 2.5 Map Manipulation 46 To find the simplified expression from the map, ) first determine all prime implicant 2) simplified expression all the essential prime implicant + other prime implicant (Ex) Fig 2.2 (a) (b) (a) Prime Implicant Groups, (b) Essential Prime Implicant Groups A'D and BD': essential prime implicants A'B: not essential 47 2.5 Map Manipulation 48 (Ex) Fig 2.22 A'B'C'D', BC'D, ABC', AB'C: essential prime implicants ACD or ABD: not essential F = A'B'C'D' + BC'D + ABC' + AB'C + ACD or ABD

49 2.5 Map Manipulation 5 Nonessential Prime Implicant Selection Rule minimize the overlap among prime implicant as much as possible Ex2.7 F(A,B,C,D) = Σ m(,,2,4,5,,,3,5) F' = A'C' + ABD + AB'C + A'B'D' 2.5 Map Manipulation 5 Ex 2-92 52 Product-of-Sums Simplification F(A,B,C,D)= m(,,2,4,5,,,3,5) from sum-of-products to product-of-sums complement the function (taking a dual) ) Combine the squares marked with 's 2) change the function, which is expressed in product of sums to sum of products Ex2.8 F(A,B,C,D) = Σ m(,,2,5,8,9,) F' = AB + CD + BD' F = (A'+B')(C'+D')(B'+D) Ex 2-2 53 2.5 Map Manipulation 54 F(A,B,C,D)= m(,,2,5,8,9,) Ex) F = (A'+B'+C) (B + D) ) plot the map by taking its complement i) combining the s results in SOP form. ii) combining the s and complementing it gives POS form. F (SOP) F (POS) F' = ABC' + B'D' 2) marking 's in the squares to represent F' remaining squares are marked with 's 3) combine the s (SOP) or 4) combine the 's and then complement the function (POS) Ex) F=(A +B +D )(A+B +C )(A +B+D )(B+C +D ) ) SOP a) F b) marking s with product terms, others are s. c) combine s to get F directly 2) POS combine s and complement F to get F

2.5 Map Manipulation 55 2.5 Map Manipulation 56 Don't Care Conditions unspecified minterms of a function ex) 4-bit binary code for the decimal digits marked with cross (X) provide the further simplification of the function Ex) F(A,B,C,D) = Σ m(,3,7,,5) d(a,b,c,d) = Σ m(,2,5) obtain a simplified product-of-sums F = CD + A'B' = CD + A'D F' = Z' + WY' F = Z(W' + Y) 2-6 Multiple-Level Optimization Multiple-Level Circuit Example Multiple-level circuits - circuits that are not two-level (with or without input and/or output inverters) Multiple-level circuits can have reduced gate input cost compared to two-level (SOP and POS) circuits Multiple-level optimization is performed by applying transformations to circuits represented by equations while evaluating cost Transformations Factoring - finding a factored form from SOP or POS expression Algebraic - No use of axioms specific to Boolean algebra such as complements or idempotence Boolean - Uses axioms unique to Boolean algebra Decomposition - expression of a function as a set of new functions Transformations (continued) Substitution of G into F - expression function F as a function of G and some or all of its original variables Elimination - Inverse of substitution Extraction - decomposition applied to multiple functions simultaneously

Transformation Examples Algebraic Factoring F = A C D + A B C + ABC + AC D G = 6 Factoring: F = A ( C D + B C) + A (BC + C D ) G = 6 Factoring again: F = A C( B + D ) + AC (B + D ) G = 2 Factoring again: F = ( AC + AC) (B + D) G = Transformation Examples Decomposition The terms B + Dand AC + AC can be defined as new functions E and H respectively, decomposing F: F = E H, E = B + D, and H = AC + AC G = This series of transformations has reduced G from 6 to, a substantial savings. The resulting circuit has three levels plus input inverters. Transformation Examples Substitution of E into F Returning to F just before the final factoring step: F = A C( B + D) + AC (B + D) G = 2 Defining E = B + D, and substituting in F: F = A C E + ACE G = This substitution has resulted in the same cost as the decomposition Transformation Examples Elimination Beginning with a new set of functions: X = B + C Y = A + B Z = AX + C Y G = Eliminating X and Y from Z: Z = A(B + C) + C (A + B) G = Flattening (Converting to SOP expression): Z = A B + A C + AC + BC G = 2 This has increased the cost, but has provided an new SOP expression for two-level optimization. Transformation Examples Two-level Optimization The result of 2-level optimization is: Z = A B + C G = 4 This example illustrates that: Optimization can begin with any set of equations, not just with minterms or a truth table Increasing gate input count G temporarily during a series of transformations can result in a final solution with a smaller G Transformation Examples Extraction Beginning with two functions: E = A BD + ABD H = B C D + BCD G = 6 Finding a common factor and defining it as a function: F = BD + BD We perform extraction by expressing E and H as the three functions: F = BD + BD, E = AF, H = CF G = The reduced cost G results from the sharing of logic between the two output functions

Overview 2.7 NAND and NOR Gates 68 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization Map Manipulation Multi-Level Circuit Optimization Part 3 Additional Gates and Circuits Other Gate Types Exclusive-OR Operator and Gates High-Impedance Outputs Boolean functions are expressed in terms of AND, OR, NOT straight forward to implement the function with these gates Other useful logic gates 2.6 NAND and NOR Gates 69 2.6 NAND and NOR Gates 7 NAND gate a universal gate because any digital system can be implemented with it Two-Level Implementation easy to implement with NAND gates, if the function is in sum of products form (Ex) F = AB + CD Implementation of NOT (inverter), AND, OR 2 graphic symbols: AND-invert & invert-or F = ( (AB)' (CD)' )' = AB + CD 2.6 NAND and NOR Gates 7 2.6 NAND and NOR Gates 72 Ex2.9) F(X,Y,Z) = Σ m(,2,3,4,5,7) Multilevel NAND Circuits with three or more levels ) convert all AND gates to NAND gates w/ AND-invert 2) convert all OR gates to NAND gates w/ invert-or 3) convert rest small circles to inverters Ex) F = A (CD + B) + BC'

73 2.6 NAND and NOR Gates 74 NOR gate dual of the NAND operation another universal gate implementation of NOT (inverter), AND, OR two graphic symbol for NOR gate 2.6 NAND and NOR Gates 75 2.7 Exclusive-OR Gate 76 Two-Level Implementation easy to implement with NOR gates, if the function is in product of sums form (Ex) F = (A + B) (C + D) E exclusive-or (XOR) gate X Y = X Y' + X' Y if only one variable is equal to, but not both exclusive-nor gate ( X Y )' = X Y + X' Y' if both are equal to or both are equal to (Ex) F = (AB' + A'B) E (C + D') they are to be the complement of each other 2.7 Exclusive-OR Gate 77 Odd Function 78 properties F=X Y Z X = X X = X' = (XY +X Y)Z +(XY+X Y )Z X X = X X' = = XY Z +X YZ +X Y Z+XYZ X Y' = (X Y)' X' Y = (X Y)' A B = B A (A B) C = A (B C) = A B C implementation with NAND gates

Odd Function 79 Parity Generation and Checking 8 Parity Generation and Checking 8 2.8 Integrated Circuits 82 Integrated Circuits (IC) small silicon semiconductor crystal, called a chip contains electronic components for the digital gates Levels of Integration SSI (small scale integration), < gates MSI, ~ gates LSI, ~ s VLSI, > s 2.8 Integrated Circuits 83 Delay 84 Digital Logic Families RTL, DTL - earliest logic families TTL - widespread, considered as standard ECL - high speed operation MOS - high component density CMOS - low power consumption BiCMOS - CMOS + TTL, used selectively Positive and Negative Logic Normal Convention: Positive Logic/Active High Low Voltage = ; High Voltage = Alternative Convention sometimes used: Negative Logic/Active Low Low Voltage = ; High Voltage = propagation delay( ): t pd transport delay(td): - inertial delay(id): - rejection time

Transport Delay, Inertial Delay 85 Positive and Negative Logic 86 inputs: (V), +V(V) positive logic( Active High Logic) +V(V): logic (True), (V): logic (False) negative logic (Active Low Logic) +V(V): logic (False), (V): logic (True) 2.8 Integrated Circuits 87 Transmission Gate 88 - Electronic Switch between two points (f) polarity indicator: small triangles in I/O XOR gate using Transmission Gates 89