arrier oard esign Guide for OM Express Modules (OM.0 R.0) 0.0-000-00
opyright opyright 0-0 VI Technologies Incorporated. ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VI Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VI Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users. Trademark Windows, Windows XP, Windows 000, Windows ME and Plug and Play are registered trademarks of Microsoft orporation. PI and PI Express are registered trademarks of the PI Special Interest Group. PS/ is a registered trademark of International usiness Machines orporation. I² is a registered trademark of Philips Electronics. ll trademarks are the properties of their respective owners. isclaimer No license is granted, implied or otherwise, under any patent or patent rights of VI Technologies. VI Technologies make no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VI Technologies assume no responsibility for any errors in this document. Furthermore, VI Technologies assumes no responsibility for the use or misuse of the information (including use or connection of extra device/equipment/add-on card) in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. F- Radio Frequency Interference Statement This equipment has been tested and found to comply with the limits for a class digital device, pursuant to part of the F rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his personal expense. Notice The changes or modifications not expressly approved by the party responsible for compliance could void the user s authority to operate the equipment. Notice Shielded interface cables and.. power cord, if any, must be used in order to comply with the emission limits. Notice The product described in this document is designed for general use, VI Technologies assumes no responsibility for the conflicts or damages arising from incompatibility of the product. heck compatibility issue with your local sales representatives before placing an order Tested To omply With F Standards FOR HOME OR OFFIE USE
OM Express (OM.0 R.0) arrier oard esign Guide REVISION HISTORY Revision ate escription 0.0 //0 Initial internal draft release. 0.0 0//0 dded note on section.. Updated figure and figure captions. 0. //0 Updated legal page: opyright year. dded HMI registered trademark. 0.0 //0 Removed VP interface section. Updated pinlists table of onnector -. Updated differential trace width, spacing, impedance and accumulated trace length of PIe in tables -, -, - and -. hanged PIe rev..0 and rev..0 to PIe Gen and Gen in table -. Updated differential trace width, spacing, and impedance of ST in table -. Updated accumulated trace length of US.0 and.0 in tables - and -. Updated differential trace width, spacing, and impedance of US.0 in table -. Updated Note on pages,,, and dded OMe-X0 information and OME schematics. Updated the naming of OMEX0 and OMEX0 to OMe-X0 and OMe-X0 respectively. Updated copyright year and disclaimer notice. iii
OM Express (OM.0 R.0) arrier oard esign Guide TLE OF ONTENTS Revision History...iii Table of ontents...iv Lists of Figures...vi Lists of Tables... viii : Introduction....: ocument Overview....: ocument onventions.....: cronyms and bbreviations.....: Illustrations and Schematics... : General arrier oard Recommendations....: P Stackup example.....: Microstrip versus stripline designs....: General Layout and Routing Rules.....: Routing Styles and Topology.....: General Trace ttribute Recommendations.....: General lock Routing onsiderations... : OM Express Mechanical Specification....: OM Express Module Form Factors...0.: imensions of the OM Express onnectors....: Pinout of OM Express Interface.....: Type 0 Pinout onnector......: onnector -.....: Type Pinout onnector......: onnector -......: onnector -... : Interface Layout and Routing Recommendations....: PI Express x Interface.....: PIe x Signal efinition.....: PIe x Reference Schematics......: PIe x Interface Topology...0...: Mini PI Express socket......: PIe x Mode Layout and Routing Recommendations....: PI Express Graphics (PEG x) Interface.....: PEG x Signal efinition.....: PEG x Reference Schematics......: PEG x Interface Topology......: PEG x Layout and Routing Recommendations....: igital isplay Interface.....: igital isplay Interface Signal efinition.....: I Reference Schematics...0...: I Layout and Routing Recommendations....: VG Interface.....: VG Signal efinition.....: VG Reference Schematics......: VG Interface Topology......: VG Layout and Recommendations....: LVS Interface.....: LVS Signal efinition.....: LVS Reference Schematics......: LVS Interface Topology......: LVS Layout and Routing Recommendations...0 iv
OM Express (OM.0 R.0) arrier oard esign Guide.: igital Video Port (VP) Interface.....: VP Signal efinition.....: VP Reference Schematics......: VP Interface Topology.....: igital Video Port Layout and Routing Recommendation....: Low Pin ount Interface.....: LP Signal efinition.....: LP Reference Schematics......: LP Interface Topology......: LP Layout and Routing Recommendations....: Serial OM Interface.....: Serial OM Signal efinition.....: Serial OM Reference Schematics......: Serial OM Interface Topology......: Serial OM Layout and Routing Recommendations....: General Purpose I us Interface.....: General Purpose I Signal efinition.....: General Purpose I Reference Schematics......: General Purpose I Layout and Routing Recommendations....0: PI Interface (Type Only)....0.: PI Signal efinition....0.: PI Reference Schematics....0..: PI Interface Topology....0..: PI Layout and Routing Recommendations....: IE Interface (Type Only).....: IE Signal efinition.....: IE Reference Schematics......: IE Interface Topology...0...: IE Supporting Modes......: IE able etection......: IE Layout and Routing Recommendation....: ST Interface.....: ST Signal efinition.....: ST Reference Schematics......: ST Layout and Routing Recommendations....: US.0 and US.0 Interface.....: US.0 and US.0 Signal efinition.....: US.0 and.0 Reference Schematics......: US Layout and Routing Recommendations...0.: udio Interface.....: udio Signal efinition.....: udio Reference Schematics......: udio Layout and Routing Recommendations....: System Management us (SMus) Interface.....: System Management us Signal efinition......: SMus Layout and Routing Recommendations....: LN Interface.....: LN Signal efinition.....: LN Reference Schematics......: LN Layout and Routing Recommendations.....: LN Layout and Routing Recommendations... ppendix : Video ombinations & isplay evice Support... ppendix : OME, OME & OME Reference Schematics... v
OM Express (OM.0 R.0) arrier oard esign Guide LISTS OF FIGURES Figure -: onventions pertaining to illusrations and schematics... Figure -: Six-layer microstrip P stackup example... Figure -: Six-layer stripline P stackup example... Figure -: Point-to-point and multi-drop examples... Figure -: aisy-chain example... Figure -: lternate multi-drop example... Figure -: Suggested clock trace spacing... Figure -: lock trace layout in relation to the ground plane... Figure -: Series termination for multiple clock loads... Figure -: OM Express connector placement on arrier oard P... Figure -: OM Express Form Factors comparisons...0 Figure -: OM Express connector dimensions... Figure -: Orientation of OM Express connectors on a OM Express module... Figure : PI Express lock uffer... Figure : PI Express x Mode Slot... Figure -: PI Express x Mode Topology Example...0 Figure : Mini PI Express ard Socket... Figure -: Mini PI Express x Mode Topology Example... Figure -: PI Express (x mode) Trace Spacing... Figure : PEG x Slot (PE) Example... Figure -: PEG x Topology Example... Figure -: PEG x Trace Spacing... Figure -0: I Interface Implementation Example...0 Figure -: HMI Interface onnector iagram... Figure -: isplayport Interface onnector iagram... Figure -: VG Interface onnector Example... Figure -: VG Interface Sample iagram... Figure -: Recommended RG Trace Properties... Figure -: LVS onnector Example... Figure -: LVS Panel Power... Figure -: LVS acklight... Figure -: LVS Interface Sample iagram... Figure -0: VP slot example... Figure -: VP Slot Interface iagram... Figure -: igital TV-out Interface using External TV Encoder Implementation... Figure -: VI Panel Interface using External VI Transmitter Implementation... Figure -: TTL Panel Interface using External TTL Panel Implementation... Figure -: LP Flash ROM Interface... Figure -: LP Super I/O Example... Figure -: LP OM Interfaces... Figure -: LP Topology Example... Figure -: Serial OM port Interface Example... Figure -0: Serial OM Interface Topology Example... Figure -: EEPROM ircuitry Reference Example... Figure : PI onnector Example... Figure -: PI Interface Topology Example... Figure -: IE onnector... Figure -: F ard Socket... Figure -: IE evices Layout Guidelines...0 Figure -: IE able etection with 0-onductor Ribbon able... Figure -: IE able etection with 0-onductor Ribbon able... vi
OM Express (OM.0 R.0) arrier oard esign Guide Figure -: ST onnector ( ST ports)... Figure -0: ST Trace Spacing... Figure -: US.0 (port 0 and port ) Interface... Figure -: US.0 (port 0 and port ) Interface... Figure -: US.0 ifferential Signal Layout Recommendations...0 Figure -: US.0 ifferential Signal Layout Recommendations...0 Figure -: US ifferential Signal Routing Example...0 Figure -: US.0 and.0 Trace Spacing... Figure -: H udio odec Implementation Example... Figure -: Single On-oard High efinition udio odec Implementation Example... Figure -: Fully On-oard High efinition udio odec Implementation Example... Figure -0: SMus Interface Example... Figure -: LN Implementation Example... Figure -: 0/00 Ethernet Layout Recommendation (integrated magnetic module)... Figure -: 0/00 Ethernet Layout Recommendations (external magnetic module)... Figure -: Gigabit Ethernet Layout Recommendations (integrated magnetic module)...0 Figure -: Gigabit Ethernet Layout Recommendations (external magnetic module)...0 vii
OM Express (OM.0 R.0) arrier oard esign Guide LISTS OF TLES Table : cronyms and bbreviation... Table : General Six layer microstrip P stackup... Table : P Stack-Up etail... Table : Recommended Trace Width and Spacing... Table : Four x Lane PI Express Signal escriptions... Table : PI Express Signal Groups PE to PE slot...0 Table : Mini-PI Express socket pinout definition... Table : PI Express Trace Properties... Table : PI Express Interface Routing Topology and Signal Type... Table : PI Express Interface Layout Guidelines... Table : PEG x Signal escriptions... Table : PEG x Signal Group... Table : PEG x Interface Trace Properties... Table 0: PEG x Interface Routing Topology and Signal Type... Table : PEG x Interface Layout Guidelines... Table : igital isplay Interface Signal escriptions...0 Table : I Interface Termination Option and Routing Topology... Table : I Interface Trace Properties... Table : I Interface Layout Guidelines... Table : VG Signal escriptions... Table : VG Interface Trace Properties... Table : VG Interface Termination Option and Routing Topology... Table : VG Interface Layout Guidelines... Table 0: LVS Signal escriptions... Table : LVS Interface Termination Option and Routing Topology...0 Table : LVS Interface Trace Properties...0 Table : LVS Interface Layout Guidelines... Table : VP Signal escriptions... Table : VP Interface Termination Option and Routing Topology... Table : VP Interface Trace Properties... Table : VP Interface Layout Guidelines... Table : LP Signal escriptions... Table : LP Interface Topology, Signal Type and Layout Guidelines... Table 0: LP Interface Trace Properties...0 Table : Serial OM Signal escriptions... Table : Serial OM Interface Topology, Signal Type and Layout Guidelines... Table : Serial OM Interface Trace Properties... Table : General Purpose I Signal escriptions... Table : General Purpose I Interface Topology, Signal Type and Layout Guidelines... Table : General Purpose I Interface Trace Properties... Table : PI Signal escriptions... Table : PI slot connection... Table : PI Interface Routing Requirements... Table 0: PI Interface Layout Guidelines... Table : PI Interface Trace Properties... Table : IE Signal escriptions... Table : IE Supporting Modes, Transfer Rate and able Type... Table : IE Interface Signal Type and Routing Topology... Table : IE Interface Trace Properties... Table : IE Interface Layout Guidelines... Table : ST Signal escriptions... viii
OM Express (OM.0 R.0) arrier oard esign Guide Table : ST Trace Properties... Table : ST Routing, Topology and Layout Guidelines... Table 0: US.0 Signal escriptions... Table : US.0 Signal escriptions... Table : US.0 Interface Routing Topology and Signal Type... Table : US.0 Interface Layout Guidelines... Table : US.0 Trace Properties... Table : US.0 (SuperSpeed US) Interface Routing Topology and Signal Type... Table : US.0 (SuperSpeed US) Interface Layout Guidelines... Table : US.0 Trace Properties... Table : udio Interface Signal escriptions... Table : Trace Properties for udio Interface... Table 0: Topology and Layout Guidelines for udio Interface... Table : SMus Interface Signal escriptions... Table : Trace Properties for SMus Interface... Table : Topology and Layout Guidelines for SMus Interface... Table : LN Signal escriptions... Table : Trace Properties for LN Interface... Table : Topology and Layout Routing Guidelines for LN Interface... ix
OM Express (OM.0 R.0) arrier oard esign Guide : INTROUTION This document provides layout and routing design guidelines to developers of OM Express carrier boards that support the features of VI OMe-X0, OMe-X0 and OMe-X0 OM Express modules. This guideline provides all the major underlying interfaces related to OM.0 R.0. While, there are a total of seven different Type of OM Express defined in the OM.0 R.0, this document discusses only Type 0, Type and Type implementations This document is not intended to be a specification. ll information in the document is believed to be accurate as of the publication date. However, no guarantees are given regarding the accuracy of this document..: ocument Overview brief description of each chapter is given below. hapter : Introduction hapter briefly introduces the structure of the design guide document. hapter : General carrier board recommendations General design schemes and recommended layout rules are shown in chapter. This chapter contains board descriptions and general layout and routing guidelines for a OM Express arrier oard. These design recommendations should be used when designing a system. hapter : OM Express Mechanical Specification etailed information about the OM Express connector placement and dimensions are described in chapter. hapter : Interface layout and routing recommendations etailed layout and routing guidelines for each interface are described in chapter. ppendix : Video combinations and display device support ppendix contains the combination of video and display device support using OM.0 R.0 module. ppendix : OME, OME and OME reference schematics ppendix contains the schematics for the carrier board reference design. These schematics (OME, OME and OME) can be used as one example on how to design a OM Express carrier board that provides optimal performance when used with VI OM Express OMe-X0 module (OM.0 R.0), OMe-X0 module (OM.0 R.0) and OMe-X0 module (OM.0 R.0). The reference designs are only for reference and not to be copied.
.: ocument onventions OM Express (OM.0 R.0) arrier oard esign Guide..: cronyms and bbreviations Term escription udio odec F card ompactflash card M irect Memory ccess igital nalog onverter isplay ata hannel I igital isplay Interface VI igital Visual Interface VP igital Video Port EEPROM Electrically ErasableProgrammable Read-Only Memory EMI Electromagnetic Interference GE Gigabit Ethernet H High efinition udio HMI High-efinition Multimedia Interface I Inter-Integrated ircuit IE Integrated rive Electronics IEEE Institute of Electrical and Electronics Engineers LN Local rea Network L Liquid rystal isplay LP Low Pin ount LVS Low-Voltage ifferential Signaling N No onnection P Printed ircuit oard PI Peripheral omponent Interconnect PIe Peripheral omponent Interconnect Express PEGx PI Express Graphics x Lane RG Red, Green and lue analog signals RJ Registered Jack ROM Read-Only Memory ST Serial dvanced Technology ttachment SMus System Management us TTL Transistor-Transistor Logic US Universal Serial us VG Video Graphics rray Table : cronyms and bbreviation
..: Illustrations and Schematics OM Express (OM.0 R.0) arrier oard esign Guide Illustrations and schematics depicted in this document may show the directional flow of signals. irectional flow is indicated by the pointed ends of the polygonal shapes. See Figure -. Figure -: onventions pertaining to illusrations and schematics
OM Express (OM.0 R.0) arrier oard esign Guide : GENERL RRIER OR REOMMENTIONS This section contains general guidelines for the printed circuit board (P) stackup and the layout of traces. General guidelines for routing style, topology, and trace attribute recommendations are also discussed..: P Stackup example Figure - illustrates an example of a P with a six-layer stackup. The stackup consists of three signal layers and three reference (power and ground) layers. The three signal layers are referred to as the component layer, inner layer and solder layer. The example below also shows the P stackup in a microstrip design. Figure -: Six-layer microstrip P stackup example..: Microstrip versus stripline designs arrier board designers can choose between two basic categories of P design: microstrip and stripline. Microstrip designs have the outer signal layers exposed. Stripline designs have the outermost signal layers shielded by reference layers. Figure -: Six-layer stripline P stackup example The choice of microstrip or stripline design depends on the application for which the carrier board is being designed. If the carrier board is being designed for locations where sensitivity to electromagnetic interference (EMI) is an issue, a stripline design is recommended for reducing EMI and noise coupling. For applications where the tolerance for EMI levels is greater, a microstrip design is recommended to reduce costs. ue to the inherent nature of stripline P stacks, broad-side coupling is possible.
OM Express (OM.0 R.0) arrier oard esign Guide Layer escription Thickness Value Spacing (mil) omponent Layer 0. oz. opper+planting Prepeg. ~. mil thickness Ground Layer.0 oz. opper Prepeg. ~. mil thickness Inner Layer ~. mil thickness Prepeg. ~. mil thickness ~ mil Power Layer.0 oz. opper Prepeg. ~. mil thickness Ground Layer.0 oz. opper Prepeg. ~. mil thickness Solder Layer 0. oz.opper+planting Table : General Six layer microstrip P stackup escription Value Notes ielectric constant (Ɛr) of Prepeg. ~. @ GHz oard Impedance Ω ±0% For all signal layers Table : P Stack-Up etail Notes:. It is not recommended to have any signal routings on either power layer or the ground layer. If a signal must be routed on the power layer, then it should be routed as short as possible on the power layer.. Signal routing on the ground layer is not allowed.. Lower trace impedance providing better signal quality is preferred over higher trace impedance for clock signals.
.: General Layout and Routing Rules OM Express (OM.0 R.0) arrier oard esign Guide This section provides general layout rules and routing guidelines for designing OM Express arrier oards...: Routing Styles and Topology Topology is the physical connectivity of a net or a group of nets. There are two types of topologies for a motherboard layout: point-to-point and multi-drop. n example of these topologies is shown in Figure -. Multi-rop SI SI Point-to-Point SI or onnector SI or onnector Figure -: Point-to-point and multi-drop examples High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state. In order to maintain better signal quality, transmission stubs should be kept as short as possible (less than. ). Therefore, daisy chain style routing is strongly recommended for these signals. Figure - below shows an example of daisy chain routing. trace segment SI SI short stub SI or onnector SI or onnector Figure -: aisy-chain example If daisy chain routing is not allowed in some circumstances, different routings may be considered. n alternative topology is shown in Figure -. In this case, the branch point is somewhere between both ends. It may be near the source or near the loads. eing close to the load side is best. The separated traces should be equal in length. SI or onnector SI equal length somewhere in the middle SI or onnector Figure -: lternate multi-drop example
..: General Trace ttribute Recommendations OM Express (OM.0 R.0) arrier oard esign Guide mil trace width and 0 mil spacing are generally advised for most signal traces on a OM Express carrier board layout. To reduce trace inductance the minimum power trace width is recommended to be 0 mil. s a quick reference, the overall recommended trace width and spacing for different trace types are listed in Table, and the recommended trace width and spacing for each signal group is shown in hapter. Trace Type Trace Width (mil) Spacing (mil) Regular Signal or wider 0 or wider Interface or us Reference Voltage Signal 0 or wider 0 or wider Power 0 or wider 0 or wider Table : Recommended Trace Width and Spacing General rules for minimizing crosstalk in high-speed bus designs are listed below: Maximize the distance between traces. Maintain 0 mil minimum spaces between traces wherever possible. Maximize the distance (0 mil minimum) between two adjacent routing areas of different signal groups wherever possible. void parallelism between traces on adjacent layers. Select a board stack-up that minimizes coupling between adjacent traces...: General lock Routing onsiderations lock routing guidelines are listed below: The recommended clock trace width is mil. The minimum space between one clock trace and adjacent clock traces is 0 mil. The minimum space from one segment of a clock trace to other segments of the same clock trace is at least two times of the clock width. That is, more space is needed from one clock trace to others or its own trace to avoid signal coupling (see Figure -). lock traces should be parallel to their reference ground planes. That is, a clock trace should be right beneath or on top of its reference ground plane (see Figure -). Series terminations (damping resistors) are needed for all clock signals (typically 0 Ω to Ω). When two loads are driven by one clock signal, the series termination layout is shown in Figure -. When multiple loads (more than two) are applied, a clock buffer solution is preferred. Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically 0 mil to 0 mil wide) is preferred. No clock traces on the internal layer if a six-layer board is used.
OM Express (OM.0 R.0) arrier oard esign Guide clock trace clock synthesizer 0 mil at least two times of the width of the clock segment clock segment Figure -: Suggested clock trace spacing another ground plane clock trace another ground plane clock trace relative ground plane relative ground plane Recommended Figure -: lock trace layout in relation to the ground plane NOT recommended damping resistors clock load clock source clock load in equal length in equal length Figure -: Series termination for multiple clock loads
OM Express (OM.0 R.0) arrier oard esign Guide : OM EXPRESS MEHNIL SPEIFITION arrier boards for VI OM Express modules must follow the placement defined in the OM Express specification. Figure - is a depiction of the top view of a carrier board P with an appropriate amount of space reserved for the OM Express module. The placement of the OM Express connectors must be exact to ensure that OM Express modules can be properly fitted. To increase the thermal performance, a buffer of mm around the perimeter of the area designated for the OM Express module is recommended as a keepout zone. Figure -: OM Express connector placement on arrier oard P
.: OM Express Module Form Factors OM Express (OM.0 R.0) arrier oard esign Guide The VI OM Express Module specifies three different types of form factors are shown below. asic module: mm x mm Extended module: 0 x mm ompact module: mm x mm Figure -: OM Express Form Factors comparisons 0
OM Express (OM.0 R.0) arrier oard esign Guide.: imensions of the OM Express onnectors The OM Express connectors comprises of up to two 0-pin connectors. Each connector is said to have two rows..±0.0.±0.0 Pin / on receptacle Pin / on plug 0.±0.0.±0.0 0. pitch..±0.0. ø0.±0. Pin / on receptacle Pin / on plug. ø.±0..±0.0 (units are in mm) Figure -: OM Express connector dimensions The connectors on the bottom of the OM Express module should have the rows in the reverse order of the rows on the carrier board. Figure - shows an example of how the rows should be oriented on the OM Express module. Figure -: Orientation of OM Express connectors on a OM Express module
.: Pinout of OM Express Interface OM Express (OM.0 R.0) arrier oard esign Guide The pinout tables show the pinout of the OM Express interface as implemented in VI OM Express modules. The pinout table in section... is intended for Type 0 only while the pinout table in section... is meant for Type and Type...: Type 0 Pinout onnector...: onnector - Pin Pinout Name (Row ) Pin Pinout Name (Row ) (FIXE) (FIXE) GE0_MI- GE0_T# GE0_MI+ LP_FRME# GE0_LINK00# LP_0 GE0_LINK000# LP_ GE0_MI- LP_ GE0_MI+ LP_ N LP_RQ0# GE0_MI- LP_RQ# 0 GE0_MI+ 0 LP_LK (FIXE) (FIXE) GE0_MI0- PWRTN# GE0_MI0+ SM_K GE0_TREF SM_T SUS_S# SM_LERT# ST0_TX+ ST_TX+ ST0_TX- ST_TX- SUS_S# N ST0_RX+ ST_RX+ 0 ST0_RX- 0 ST_RX- (FIXE) (FIXE) RSV RSV RSV RSV SUS_S# PWR_OK RSV RSV RSV RSV TLOW# WT (S)T_T# /H_SIN /H_SYN /H_SIN 0 /H_RST# 0 /H_SIN0 (FIXE) (FIXE) /H_ITLK SPKR /H_SOUT I_K -IOS_IS0 I_T THRMTRIP# THRM# US- US- US+ US+ US O# US O# US- US- 0 US+ 0 US+ (FIXE) (FIXE) US- US- US+ US+ US O# US_0 O# US0- US- US0+ US+ V_RT EX_PERST# EX0_PERST# N N SYS_RESET# 0 LP_SERIRQ 0 _RESET# (FIXE) (FIXE) RSV RSV RSV RSV GPI0 GPO
OM Express (OM.0 R.0) arrier oard esign Guide Pin Pinout Name (Row ) Pin Pinout Name (Row ) RSV RSV RSV RSV GPO PIE_TX+ PIE_RX+ PIE_TX- PIE_RX- 0 (FIXE) 0 (FIXE) PIE_TX+ PIE_RX+ PIE_TX- PIE_RX- GPI GPO PIE_TX+ PIE_RX+ PIE_TX- PIE_RX- WKE0# GPI WKE# PIE_TX0+ PIE_RX0+ PIE_TX0- PIE_RX0-0 (FIXE) 0 (FIXE) LVS_0+ I0_PIR0+ LVS_0- I0_PIR0- LVS_+ I0_PIR+ LVS_- I0_PIR- LVS_+ I0_PIR+ LVS_- I0_PIR- LVS_V_EN I0_PIR+ LVS_+ I0_PIR- LVS_- LVS_KLT_EN 0 (FIXE) 0 (FIXE) LVS K+ I0_PIR+ LVS K- I0_PIR- LVS_I_K LVS_KLT_TRL LVS_I_T V_V_SY GPI V_V_SY RSV V_V_SY RSV V_V_SY PIE_K_REF+ IOS_IS# PIE_K_REF- I0_HP 0 (FIXE) 0 (FIXE) SPI_POWER I0_PIR+ SPI_MISO I0_PIR- GPO0 I0_PIR+ SPI_LK I0_PIR- SPI_MOSI I0 UX_SEL N RSV N SPI_S# SER0_TX I0_TRLLK_UX+ SER0_RX I0_TRLLK_UX+ 00 (FIXE) 00 (FIXE) 0 SER_TX 0 FN_PWNOUT 0 SER_RX 0 FN_THIN 0 N 0 N 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 (FIXE) 0 (FIXE)
..: Type Pinout onnector The signal names in gray indicate signals that are relevant to Type. OM Express (OM.0 R.0) arrier oard esign Guide...: onnector - Pin Pinout Name (Row ) Pin Pinout Name (Row ) (FIXE) (FIXE) GE0_MI- GE0_T# GE0_MI+ LP_FRME# GE0_LINK00# LP_0 GE0_LINK000# LP_ GE0_MI- LP_ GE0_MI+ LP_ N LP_RQ0# GE0_MI- LP_RQ# 0 GE0_MI+ 0 LP_LK (FIXE) (FIXE) GE0_MI0- PWRTN# GE0_MI0+ SM_K GE0_TREF SM_T SUS_S# SM_LERT# ST0_TX+ ST_TX+ ST0_TX- ST_TX- SUS_S# / N N ST0_RX+ ST_RX+ 0 ST0_RX- 0 ST_RX- (FIXE) (FIXE) N / ST_TX+ N / ST_TX+ N / ST_TX- N / ST_TX- SUS_S# PWR_OK N / ST_RX+ N / ST_RX+ N / ST_RX- N / ST_RX- TLOW# / N WT (S)T_T# / T_T# /H_SIN / N /H_SYN / _SYN /H_SIN / N 0 /H_RST# / _RST# 0 /H_SIN0 / _SIN0 (FIXE) (FIXE) /H_ITLK / _ITLK SPKR /H_SOUT / _SOUT I_K -IOS_IS0 I_T THRMTRIP# / N THRM# / N US- / N US- / N US+ / N US+ / N US O# / N US O# US- US- 0 US+ 0 US+ (FIXE) (FIXE) US- US- US+ US+ US O# US_0 O# US0- US- US0+ US+ V_RT EX_PERST# EX0_PERST# N N SYS_RESET# 0 LP_SERIRQ 0 _RESET# (FIXE) (FIXE) N N N N GPI0 GPO N N N N GPO N N N N 0 (FIXE) 0 (FIXE)
OM Express (OM.0 R.0) arrier oard esign Guide Pin Pinout Name (Row ) Pin Pinout Name (Row ) N N N N GPI GPO PIE_TX+ PIE_RX+ PIE_TX- PIE_RX- WKE0# GPI WKE# PIE_TX0+ PIE_RX0+ PIE_TX0- PIE_RX0-0 (FIXE) 0 (FIXE) LVS_0+ N / LVS_0+ LVS_0- N / LVS_0- LVS_+ N / LVS_+ LVS_- N / LVS_- LVS_+ N / LVS_+ LVS_- N / LVS_- LVS_V_EN N / LVS_+ LVS_+ N / LVS_- LVS_- LVS_KLT_EN 0 (FIXE) 0 (FIXE) LVS K+ N / LVS K+ LVS K- N / LVS K- LVS_I_K LVS_KLT_TRL LVS_I_T V_V_SY GPI V_V_SY RSV / K_RST# V_V_SY RSV / K_0GTE V_V_SY PIE_K_REF+ IOS_IS# PIE_K_REF- VG_RE 0 (FIXE) 0 (FIXE) SPI_POWER / SPI_V VG_GRN SPI_MISO / SPI_I VG_LU GPO0 VG_HSYN SPI_LK VG_VSYN SPI_MOSI / SPI_O VG_I_K N / VG_I_T N SPI_S# / -SPI_SS0 SER0_TX / RSV RSV SER0_RX / RSV RSV 00 (FIXE) 00 (FIXE) 0 SER_TX / RSV 0 FN_PWNOUT / RSV 0 SER_RX / RSV 0 FN_THIN / RSV 0 N / RSV 0 N / RSV 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 (FIXE) 0 (FIXE)
...: onnector - OM Express (OM.0 R.0) arrier oard esign Guide The signal names in blue are meant for VP pins which are defined and proprietary of VI Technologies. Pin Pinout Name (Row ) Pin Pinout Name (Row ) (FIXE) (FIXE) / IE_ / IE_ US_SSRX0- / IE_ US_SSTX0- / IE_0 US_SSRX0+ / IE_ US_SSTX0+ / IE_ / IE_ / IE_ US_SSRX- / IE_ US_SSTX- / IE_ US_SSRX+ / IE_ US_SSTX+ / IE_0 / IE_ / IE_REQ US_SSRX- / IE_ US_SSTX- / IE_IOW# 0 US_SSRX+ / IE_ 0 US_SSTX+ / IE_K# (FIXE) (FIXE) US_SSRX- / IE_ US_SSTX- / IE_IRQ US_SSRX+ / IE_IORY US_SSTX+ / IE_0 / IE_IOR# / IE_ N / PI_PME# N / IE_ N / PI_GNT# N / IE_S# RSV / PI_REQ# RSV / IE_S# RSV / PI_GNT# RSV / IE_RESET# N / PI_REQ# N / PI_GNT# 0 N / PI_GNT0# 0 N / IE_REQ# (FIXE) (FIXE) N / PI_REQ0# N / PI_ N / PI RESET# N / PI_ N / PI_0 RSV / PI_ N / PI_ RSV / PI_ N / PI_ N / PI_/E0# RSV / PI_ N / PI_ RSV / PI_ RSV / PI_ N / PI_0 N / PI_ 0 N / PI_ 0 N / PI_ (FIXE) (FIXE) I_TRLLK_UX+ / PI_ N / PI_PR I_TRLT_UX- / PI_/E# N / PI_SERR# I UX_SEL / PI_PERR# N / PI_STOP# RSV / N RSV / PI_TRY# I_TRLLK_UX+ / PI_EVSEL# N / PI_FRME# I_TRLT_UX- / PI_IRY# N / N / PI_/E# RSV / PI_ I_PIR0+ / PI_ I_PIR0+ / PI_0 0 I_PIR0- / PI_ 0 I_PIR0- / (FIXE) (FIXE) I_PIR+ / PI_ I_PIR+ / PI_ I_PIR- / PI_ I_PIR- / PI_ I_HP / PI_/E# I_HP / PI_ RSV / PI_ RSV / PI_0 I_PIR+ / PI_ I_PIR+ / PI_IRQ# I_PIR- / PI_ I_PIR- / PI_IRQ# RSV / PI_ RSV / N I_PIR+ / PI_IRQ# I_PIR+ / N 0 I_PIR- / PI_IRQ# 0 I_PIR- / PI_LK (FIXE) (FIXE) PEG_RX0+ PEG_TX0+ PEG_RX0- PEG_TX0- N N PEG_RX+ PEG_TX+ PEG_RX- PEG_TX- N TYPE# PEG_RX+ PEG_TX+ PEG_RX- PEG_TX- 0 (FIXE) 0 (FIXE) PEG_RX+ PEG_TX+ PEG_RX- PEG_TX- RSV RSV
OM Express (OM.0 R.0) arrier oard esign Guide Pin Pinout Name (Row ) Pin Pinout Name (Row ) RSV RSV N N N N RSV N N N N 0 (FIXE) 0 (FIXE) N N N N / N / N N N N N RSV IE_LI# VP_0 VP_ VP_ VP_ 0 (FIXE) 0 (FIXE) VP_ VP_ VP_ VP_ RSV RSV VP_ VP_ VP_0 VP_ VP_ VP_ VP_ VP_ 0 (FIXE) 0 (FIXE) VP_E VP_TVLKR VP_VS N VP_HS VP_LK VP_TVFL N RSV RSV / VP_ET VP_SP VP_V_EN VP_SPLK VP_KLT_EN 00 (FIXE) 00 (FIXE) 0 N 0 LT_K 0 N 0 N 0 0 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 V_V 0 (FIXE) 0 (FIXE) Notes:. The VP is VI s defined interface and not specified in the OM Express standad specification.. The VI OMe-X0 OM Express module does not support VP interface.
OM Express (OM.0 R.0) arrier oard esign Guide : INTERFE LYOUT N ROUTING REOMMENTIONS The information presented in this chapter includes the signal descriptions, reference schematic examples, topology examples, and detailed layout and routing guidelines for each bus interface. The information provided is intended for designing OM Express carrier boards that are compliant with VI OM Express modules..: PI Express x Interface VI OM Express (OM.0 R.0) modules can support up to four PI Express lanes. The four lanes can be grouped into four x mode configurations. Each of these modes consists of two differential signal pairs: the receive data pair and the transmit data pair. This section will help the developer to create a robust PI Express x interface design on the carrier board. However, the carrier board designer should do an appropriate analysis and simulation to verify that the design fulfills PI Express specification requirements...: PIe x Signal efinition The general purpose PI Express interfaces are defined by the PIMG OM Express specification on connector -. The Signal Name Pin # I/O escription Type PIE_RX0+ PIE_RX0- I Receive input differential pair. hannel 0 PIE_TX0+ PIE_TX0- O Transmit output differential pair. hannel 0 0, and PIE_RX+ PIE_RX- I Receive input differential pair. hannel PIE_TX+ PIE_TX- O Transmit output differential pair. hannel 0, and PIE_RX+ PIE_RX- I Receive input differential pair. hannel PIE_TX+ PIE_TX- O Transmit output differential pair. hannel 0 PIE_RX+ PIE_RX- I Receive input differential pair. hannel PIE_TX+ PIE_TX- O Transmit output differential pair. hannel 0 PIE_K_REF+ PIE_K_REF- O PIe and PEG lanes reference lock 0, and EX0_PERST# O PIe ard0: Reset, ctive Low 0, and EX_PERST# I PIe ard: Reset, ctive Low 0, and _RESET# 0 O Reset output from Module to arrier oard 0, and WKE0# I PIe wake up signal 0, and PI_RESET# O PI reset output Table : Four x Lane PI Express Signal escriptions
..: PIe x Reference Schematics OM Express (OM.0 R.0) arrier oard esign Guide PIe lock uffer +.V + F E 000uF/0V PEX0_LK+ PEX0_LK- PIE_LK+ PIE_LK- PIE_LK+ PIE_LK- PIE_LK+ PIE_LK- PIE_LK+ PIE_LK- -00Y00 0 0uF -PEREQ_ PIE_LK_REF+ PIE_LK_REF- SM_LK SM_ +.VLK_F 0.uF 0.uF +.V 0.uF R R R R R R0 R R R 0 R 0 R 0 R 0 R 0 R 0.uF 0K 0K 0K 0K 0K 0K 0K 0K _% 0.uF OE_0 OE_ OE_ OE_ OE_ OE_ OE_ OE_ OE_INV -YPSS -LK_P -HIGH_W -SR_IV -SR_STOP SR_IN -SR_IN SLK ST IREF U V V V V V V OE_0 OE_ OE_ OE_ OE_ OE_ OE_ OE_ 0 OE_INV YPSS#/PLL P# HIGH_W# SR_IV# SR_STOP# SR_IN SR_IN# SLK ST IREF IF_0 IF_0# IF_ IF_# IF_ IF_# IF_ 0 IF_# IF_ 0 IF_# IF_ IF_# IF_ IF_# IF_ IF_# LOK 0 R R R R R R R0 R R0 R TP_KG_LOK PELK0+ PELK0- PELK+ PELK- PELK+ PELK- PELK+ PELK- PELK+ PELK- TO PEX0 TO PE SLOT TO PE SLOT TO Mini PIe TO PE SLOT IS0GLF +.V R 0K/X OE_INV PEX0_LK+ R._% R 0K PEX0_LK- R._% +.V R0 R 0K/X 0K -HIGH_W PIE_LK+ PIE_LK- PIE_LK+ R R R._%._%._% +.V R 0K/X -YPSS PIE_LK- R._% R 0K PIE_LK+ R._% +.V R R0 0K 0K/X -SR_IV PIE_LK- PIE_LK+ PIE_LK- R R R._%._%._% +.V R R 0K 0K/X -SR_STOP meet Zdif=. ohm +.V R 0K -LK_P R 0K/X Figure : PI Express lock uffer PE SM_LK SM_T -PE_WKE +.VSUS -PEPRT_ +.V +V_V 0 PI_Express_x +V PRSNT# +V +V +V +V SMLK JTG SMT JTG JTG +.V JTG JTG +.V.VUX +.V 0 WKE# PERST# Mechanical Key RSV PETP0 PETN0 PRSNT# PIE_LK+ PIE_LK- PIE_RX+ PIE_RX- PIE_TX+ PIE_TX- REFLK+ REFLK- PERP0 PERN0 +V_V +.V -PE_RST End of the x onnector +V_V E + 0uF/V 0 0.uF +.V EE000S-HZ +.VSUS E + 00uF 0 0.uF E + 00uF 0 0.uF -PEPRT_ R0.K +.V Figure : PI Express x Mode Slot
...: PIe x Interface Topology OM Express (OM.0 R.0) arrier oard esign Guide Each PI Express slot (PE to PE) contains one signal group that represents the PI Express x mode. These signal groups are listed in Table, and grouped in the example below. The PI Express signal has a pointto-point topology. Figure -: PI Express x Mode Topology Example Signal Groups PE slot (-Lane) PE slot (-Lane) PE slot (-Lane) PE slot (-Lane) Table : PI Express Signal Groups PE to PE slot Lane 0 Lane Lane Lane Signal Name PIE_RX0+ PIE_RX0- PIE_TX0+ PIE_TX0- PIE_RX+ PIE_RX- PIE_TX+ PIE_TX- PIE_RX+ PIE_RX- PIE_TX+ PIE_TX- PIE_RX+ PIE_RX- PIE_TX+ PIE_TX- 0
...: Mini PI Express socket OM Express (OM.0 R.0) arrier oard esign Guide The Mini PI Express socket is a -pin socket that is designed for modular PI Express Mini ards. pplying the Mini PIe socket enables the OM Express carrier board to have a flexible upgrade path. The Mini PI Express socket consists of a single PIe x lane and single US.0 channel wherein the PI Express Mini ard host can use either (PIe x or US.0 link) interfaces. Signal Pin # escription Type WKE# Request to return to full operation and respond to PIe +.VUX Primary source voltage,.v N No onnection Ground N No onnection +.V Secondary source voltage,.v LKREQ# lock request signal UIM_PWR User Identity Modules power source Ground UIM_T 0 ata signal for User Identity Module REFLK- Negative reference clock differential pair UIM_LK lock signal for User Identity Module REFLK+ Positive reference clock differential pair UIM_RESET Reset signal for User Identity Module Ground UIM_VPP Variable supply voltage for User Identity Module RSV Reserved Ground RSV Reserved W_ISLE# 0 Used to disable radio operation on add-in cards Ground PERST# PI Express reset PERn0 Receiver differential pair negative signal, Lane 0.VUX uxiliary voltage source,.v PERp0 Receiver differential pair positive signal, Lane 0 Ground Ground +.V Secondary source voltage,.v Ground SM_LK 0 SMus clock PETn0 Transmit differential pair negative signal, Lane 0 SM_T SMus data PETp0 Transmit differential pair positive signal, Lane 0 Ground Ground US_- US data interface differential pair, negative signal Ground US_+ US data interface differential pair, positive signal +.VUX Primary source voltage,.v 0 Ground +.VUX Primary source voltage,.v LE_WWN# LE status indicator signal Ground LE_WLN# LE status indicator signal 0, and
RSV Reserved LE_WPN# LE status indicator signal RSV Reserved +.V Secondary source voltage,.v RSV Reserved 0 Ground RSV Reerved +.VUX Primary source voltage,.v Table : Mini-PI Express socket pinout definition OM Express (OM.0 R.0) arrier oard esign Guide 0, and +.V +.VSUS +.VSUS PIE_TX+ PIE_TX- US_ME_T+ US_ME_T- PIE_RX+ PIE_RX- PIE_LK+ PIE_LK- -PEREQ_ -PE_WKE K -LKR RV-0/X Reserved Reserved Reserved Reserved +.VUX +.VUX PETp0 PETn0 PERp0 PERn0 Reserved(UIM_) Reserved(UIM_) MINIR ONN LE_WWN# 0 US_+ US_- SM_T SM_LK 0 +.V +.VUX REFLK+ REFLK- LKREQ# OEX OEX WKE# G M G M +.VUX 0 +.V LE_WPN# LE_WLN# PERST# W_ISLE# 0 UIM_VPP UIM_RESET UIM_LK UIM_T 0 UIM_PWR +.V +.VUX TP TP TP TP TP SM_T SM_LK -PE_RST0 -W_ISLE +.VSUS +.V +.VSUS.uF 0.uF.uF 0.uF.uF 0.uF Mini 0 Figure : Mini PI Express ard Socket Figure -: Mini PI Express x Mode Topology Example
OM Express (OM.0 R.0) arrier oard esign Guide...: PIe x Mode Layout and Routing Recommendations ll the PI Express signals should be referenced to the ground plane at all times. Each trace of differential pairs should route to parallel to each other with the same trace length. The spacing between differential pairs must be equal at all times (in parallel), even during trace bending and serpentine topology. ifferential pairs must be routed on the same layer with maximum of one signal layer change allowed. The differential pairs must always move to the same layer with the same reference plane. Transmit differential pairs are recommended to be routed on the top layer and receive differential pairs are recommended to be routed on the bottom layer. o not route PI Express traces under magnetic devices or I s, oscillators and clock synthesizers. To minimize signal crosstalk, wider spacing is recommended wherever possible between traces. It is always best to reduce the line mismatch to add to the timing margin. In other words, a balanced topology can match the trace lengths within the groups to minimize skew. Figure -: PI Express (x mode) Trace Spacing Signal Group Trace & Spacing (S : W : S : W : S) ifferential Trace Impedance Spacing to Other Signals PE Receive Transmit PE Receive Transmit PE Receive Transmit PE Receive Transmit Table : PI Express Trace Properties 0 : : : : 0 ifferential Ω ± 0% 0 mil Signal Group Routing Topology Signal Type Note Receive PE Transmit Receive PE Transmit Point to Point Receive PE Transmit Receive PE Transmit Table : PI Express Interface Routing Topology and Signal Type Source Synchronous I/O Signals on't cross power plane division line
OM Express (OM.0 R.0) arrier oard esign Guide Signal Group Routing Layer PE PE Top or ottom PE PE Table : PI Express Interface Layout Guidelines ccumulated Trace Length < (for PIe Gen) < (for PIe Gen) ifferential Trace Length Mismatch <0.00 Note: The PIe Gen and PIe Gen mode trace length in VI OM Express module is approximately, therefore the PIe Gen and PIe Gen mode trace length in the carrier board should not be longer than and respectively.
.: PI Express Graphics (PEG x) Interface OM Express (OM.0 R.0) arrier oard esign Guide This section describes the layout and routing guidelines that ensure a robust PEG x interface design. The PI Express Graphics interface is defined by the PIMG OM Express specification on connector -. The VI OM Express modules (specifically the Type and Type ) can support one PI Express Graphics (PEG) x lane...: PEG x Signal efinition The PEG x lane uses differential signaling on each lane (consisting of a receive data and transmit data signal pair) that results in a high-bandwidth interface. The PEG x lane signals on VI OM Express modules (OM.0 R.0) are intended for handling an external video graphics card. However, if the PEG x lane signal is not used for an external video graphics interface, it can be used by other PIe Express devices. Signal Name Pin # I/O escription Type PEG_RX0+ I Receive input differential pair. hannel 0 PEG_RX0- I Receive input differential pair. hannel 0 PEG_TX0+ O Transmit input differential pair. hannel 0 PEG_TX0- O Transmit input differential pair. hannel 0 PEG_RX+ I Receive input differential pair. hannel PEG_RX- I Receive input differential pair. hannel PEG_TX+ O Transmit input differential pair. hannel PEG_TX- O Transmit input differential pair. hannel PEG_RX+ I Receive input differential pair. hannel PEG_RX- I Receive input differential pair. hannel PEG_TX+ O Transmit input differential pair. hannel PEG_TX- O Transmit input differential pair. hannel PEG_RX+ I Receive input differential pair. hannel PEG_RX- I Receive input differential pair. hannel PEG_TX+ O Transmit input differential pair. hannel PEG_TX- O Transmit input differential pair. hannel PIE_K_REF+ O PI Express reference clock, positive signal PIE_K_REF- O PI Express reference clock, negative signal Table : PEG x Signal escriptions and and and and 0, and
..: PEG x Reference Schematics OM Express (OM.0 R.0) arrier oard esign Guide +.VSUS +.V +.V +.V +V_V +V_V R.K R.K SM_LK SM_T -PE_WKE PEG_TX0+ PEG_TX0- +.V PEG_TX+ PEG_TX- PEG_TX+ PEG_TX- PEG_TX+ PEG_TX- +.V R.K R0.K R.K PSN_ PSN_ 0 0 0 PI_Express_x +V PRSNT# +V +V +V +V SMLK JTG SMT JTG JTG +. JTG JTG +.V.VUX +.V 0 WKE# PERST# Mechanical Key RSV PETP0 PETN0 PRSNT# PIE_LK+ PIE_LK- REFLK+ REFLK- PERP0 PERN0 End of the x onnector PETP RSV PETN 0 PERP PERN PETP PETN PERP PERN PETP PETN PERP RSV PERN 0 PRSNT# RSV R 0 +.V R 0 R.K -PE_RST0 PEG_RX0+ PEG_RX0- PEG_RX+ PEG_RX- PEG_RX+ PEG_RX- PEG_RX+ PEG_RX- +.V 0.uF E0 + 00uF E0 + 00uF +.VSUS 0.uF E + 00uF +V_V 0.uF E + 0uF/V E + 0uF/V lose PI Express x Slot 0 End of the x onnector PETP RSV PETN PERP PERN PETP PETN PERP PERN 0 PETP PETN PERP PERN PETP PETN PERP PRSNT# PERN 0 0 0 0 End of the x onnector PETP RSV 0 PETN PERP PERN PETP PETN PERP PERN PETP0 PETN0 PERP0 0 PERN0 PETP PETN PERP PERN PETP PETN PERP PERN PETP 0 PETN PERP PERN PETP PETN PERP PERN PETP PETN PERP 0 PRSNT# PERN RSV End of the x onnector Figure : PEG x Slot (PE) Example
...: PEG x Interface Topology OM Express (OM.0 R.0) arrier oard esign Guide The PE slot contains signal groups that represent -lane PI Express (PEG x) interfaces. These signal groups are listed in Table. Figure -: PEG x Topology Example Table : PEG x Signal Group Signal Groups PE slot (-Lane) Lane 0 Lane Lane Lane PEG x Signal Name PEG_RX0+ PEG_RX0- PEG_TX0+ PEG_TX0- PEG_RX+ PEG_RX- PEG_TX+ PEG_TX- PEG_RX+ PEG_RX- PEG_TX+ PEG_TX- PEG_RX+ PEG_RX- PEG_TX+ PEG_TX-...: PEG x Layout and Routing Recommendations The layout and routing recommendations for the PEG x signals in OM Express carrier board are listed below: Each trace of differential pairs should route to parallel to each other with the same trace length. ll the PI Express signals should be referenced to the ground plane at all times. The spacing between differential pairs must be equal at all times (in parallel), even during trace bending and serpentine topology. ifferential pairs must be routed on the same layer with maximum of one signal layer change allowed. The differential pairs must always move to the same layer with the same reference plane. Transmit differential pairs are recommended to be routed on the top layer and receive differential pairs are recommended to be routed on the bottom layer. o not route PI Express traces under magnetic devices or I s, oscillators and clock synthesizers. To minimize signal crosstalk, wider spacing is recommended wherever possible between traces. It is always best to reduce the line mismatch to add to the timing margin. In other words, a balanced topology can match the trace lengths within the groups to minimize skew.
OM Express (OM.0 R.0) arrier oard esign Guide Figure -: PEG x Trace Spacing Signal Group Trace & Spacing (S : W : S : W : S) PE Transmit : : : : (-Lane) Receive ifferential Table : PEG x Interface Trace Properties ifferential Trace Impedance Ω ± 0% Spacing to Other Signal 0 mil Signal Group Routing Topology Signal Type Note PE Transmit Point to Point (-Lane) Receive Table 0: PEG x Interface Routing Topology and Signal Type Source Synchronous I/O Signals on't cross power plane division line Signal Group Routing Layer ccumulated Trace Length Trace Length Mismatch PE Top or ottom (-Lane) Table : PEG x Interface Layout Guidelines < (for PIe Gen) < (for PIe Gen) <0.00 Note: The PIe Gen and PIe Gen mode trace length in VI OM Express module is approximately, therefore the PIe Gen and PIe Gen mode trace length in the carrier board should not be longer than and respectively.
.: igital isplay Interface OM Express (OM.0 R.0) arrier oard esign Guide The I interface is one of the newly added interfaces in OM Express (OM.0 R.0). The VI OM Express (OM.0 R.0 compliant) modules provide igital isplay Interface (I) pin-out signals designed for interfacing the HMI (High efinition Multimedia Interface) or isplayport connection. The Type 0 module supports one I interface for I port. Its pin-out locations are implemented only on connector row. Previously on Type modules, the pin-out were used for the LVS channel and VG interfaces. The Type module can support up to two I interface for I port and I port on connector -. The carrier board developer can use the I port to configure it to either HMI or iplayport connection. The I port is intended only for isplayport interface connection. The HMI and isplayport connectors both use differential signaling, however, the auxilliary channel is required when I port is going to be configured as a isplayport connection...: igital isplay Interface Signal efinition In Type 0 module, the corresponding I interfaces (I port ) pin-out signals are defined in connector row. In Type module, the corresponding I interfaces (I port and port ) pin-out signals are defined in connector -. Signal Name Pin # I/O escription Type I0_PIR0+ I0_PIR0- O igital isplay Interface 0 Pair 0 differential pair I0_PIR+ I0_PIR- O igital isplay Interface 0 Pair differential pair I0_PIR+ I0_PIR- O igital isplay Interface 0 Pair differential pair I0_PIR+ I0_PIR- O igital isplay Interface 0 Pair differential pair I0_PIR+ I0_PIR- O igital isplay Interface 0 Pair differential pair I0_PIR+ I0_PIR- O igital isplay Interface 0 Pair differential pair I0_PIR+ I0_PIR- O igital isplay Interface 0 Pair differential pair I0_HP I igital isplay Interface 0 Hot-Plug etect I_PIR0+ I_PIR0-0 O igital isplay Interface Pair 0 differential pair I_PIR+ I_PIR- O igital isplay Interface Pair differential pair I_PIR+ I_PIR- O igital isplay Interface Pair differential pair I_PIR+ I_PIR- 0 O igital isplay Interface Pair differential pair I_HP I igital isplay Interface Hot-Plug etect P ux+ function if I[] UX_SEL is not I_TRLLK_UX+ IO connected HMI I TRLLK if I[] UX_SEL is pulled high P ux- function if I[] UX_SEL is not I_TRLT_UX- IO connected HMI I TRLT if I[] UX_SEL is pulled high 0
OM Express (OM.0 R.0) arrier oard esign Guide I UX_SEL I Select the function of I[]_TRLLK_UX+ and I[]_TRLT_UX- I_PIR0+ I_PIR0-0 O igital isplay Interface Pair 0 differential pair I_PIR+ I_PIR- O igital isplay Interface Pair differential pair I_PIR+ I_PIR- O igital isplay Interface Pair differential pair I_PIR+ I_PIR- 0 O igital isplay Interface Pair differential pair I_HP I_TRLLK_UX+ I IO igital isplay Interface Hot-Plug etect P ux+ function if I[] UX_SEL is not connected HMI I TRLLK if I[] UX_SEL is I_TRLT_UX- IO pulled high P ux- function if I[] UX_SEL is not connected HMI I TRLT if I[] UX_SEL is pulled high Table : igital isplay Interface Signal escriptions..: I Reference Schematics HP -P_HP PWR_Select P_TX0+ S P_TX0- P_TX+ P_TX- P_TX+ P_TX- P_TX+ P_TX- _UX_SEL I_TRLLK I_TRLT Vgs must less than.v Q0 Si0S-T-GE G +.V S L L +V Q N00 G PS0 SM0P0TF_. PTX_0+_ 0.uF M0-00-P-T00 PTX_0-_ 0.uF PTX_+_ 0.uF M0-00-P-T00 PTX_-_ 0.uF PTX_+_ 0.uF M0-00-P-T00 PTX_-_ 0.uF PTX_+_ 0.uF M0-00-P-T00 PTX_-_ 0.uF +.V -PHP HMI_P_PWR uf HMI (lue rea) PTX0+_ PTX0-_ PTX+_ PTX-_ PTX+_ PTX-_ PTX+_ PTX-_ R 0/X R 0/X P P +V R R R R R0 R R R R 00 R +.V 0_% 0_% 0_% 0_% 0_% 0_% 0_% 0_% 0K PWR_Select 0. for layout reference 0. for layout reference +.V HMI_P_PWR HMI_P_PWR R.K R0.K HMIT HMIT HMIT0 HMILK P P P P P P P HMI 00 0 o-layout With isplayport P (Pink rea) HMI_P_PWR +.V P_UX+ to I_TRLLK P_UX- to I_TRLT I_TRLLK I_TRLT -PHP R 0/X R 0/X 0 0.uF/X R 00K/X PWR_Select P P P P P _UX_SEL = 0, P selected _UX_SEL =, HMI selected Notes:. For HMI only, please remove all isplayport components ( Pink rea ), and install HMI components on ( lue rea ). +.V ES PTX0+_ PTX0-_ PTX+_ PTX-_ PTX0+_ PTX0-_ PTX+_ PTX-_ PTX+_ PTX-_ PTX+_ PTX-_ Rlamp0T.TT G PTX+_ PTX-_ PTX+_ PTX-_. For isplayport Only, please remove all HMI components ( lue rea ), and install P components on ( Pink rea ). P P Rlamp0T.TT P P P P P P P P P P P P G L L0 R.K F0 MS0000 R 00K R R 00 K Q F0N R 0 G G G G 0 0 P 0 0-000/X M M 0.uF/X R 00K/X V Rlamp0T.TT G S R.K Q N00 G Q N00 G S S S G R 0 G R 0 G G G G G G G G R0 0K/X R 0/X Rlamp0T.TT G Figure -0: I Interface Implementation Example 0