hapter # 3: Multi-Level ombinational Logic ontemporary Logic esign Randy H. Katz University of alifornia, erkeley June 993 No. 3- hapter Overview Multi-Level Logic onversion to NN-NN and - Networks emorgan's Law and Pushing ubbles N-OR-Invert uilding locks Tools for Multi-Level Optimization Time Response in ombinational Networks Gate elays and Timing Waveforms Hazards/Glitches and How To void Them No. 3-2
oolean lgebra ommutative Laws: a + b = b + a a b = b a ssociative Laws: (a+b)+c = a+(b+c) (ab)c = a(bc) Identities: a + = a a = a = a a + = istributive Laws: a + (b c) = (a+b) (b+c) a (b+c) = (a b) + (a c) No. 3-3 oolean lgebra omplement: a + a = a a = a + a = a a a = a Theorems: a + ab = a ab + ab = b emorgan s Theorem: a b = a + b a + b = a b No. 3-4
Multi-Level Logic: dvantages Reduced sum of products form: x = + E + + E + + E + G 6 x 3-input N gates + x 7-input OR gate (may not exist!) 25 wires (9 literals plus 6 internal wires) E E E G 2 3 4 5 6 7 x E G 2 3 actored form: x = ( + + ) ( + E) + G x 3-input OR gate, 2 x 2-input OR gates, x 3-input N gate wires (7 literals plus 3 internal wires) 4 x No. 3-5 Multi-Level Logic: onversion of orms NN-NN and - Networks emorgan's Law: ( + )' = ' '; + = (' ')'; ( )' = ' + ' ( ) = (' + ')' In other words, OR is the same as NN with complemented inputs N is the same as with complemented inputs NN is the same as OR with complemented inputs is the same as N with complemented inputs OR/NN Equivalence + + OR Nand OR Nand No. 3-6
Mult-Level Logic: onversion etween orms N/ Equivalence + + N N It It is is possible to to convert from networks with Ns and ORs to to networks with NNs and s by by introducing the appropriate inversions ("bubbles") To preserve logic levels, each introduced "bubble" must be be matched with a corresponding "bubble" No. 3-7 Multi-Level Logic: onversion of orms Example: Map N/OR network to NN/NN network () () N N OR () () NN NN NN NN No. 3-8
Example: Map N/OR network to NN/NN network NN Z NN NN Z Z = [( )' ( )' ]' = [(' + ') (' + ')]' = [(' + ')' (' + ')'] This is the easy conversion! = ( ) + ( ) No. 3-9 Example: Map N/OR network to / network \ Z \ \ \ Z onserve "ubbles" Step Step 2 onserve "ubbles" Z = No. 3-
Example: Map N/OR network to / network \ Z \ Z \ \ onserve "ubbles" Step Step 2 Z = {[(' + ')' + (' + ')']'}' = {(' + ') (' + ')}' = (' + ')' + (' + ')' = ( ) + ( ) onserve "ubbles" This is the hard conversion! N/OR to to NN/NN more natural No. 3- Example: Map OR/N network to / network onserve ubbles Verify equivalence of the two forms Z = No. 3-2
Example: Map OR/N network to / network Z = [( + )' + ( + )']' = {( + )'}' {( + )'}' = ( + ) ( + ) onserve ubbles This is the easy conversion! No. 3-3 Example: Map OR/N network to NN/NN network Nand Nand Nand onserve ubbles! Step Step 2 onserve ubbles! No. 3-4
Example: Map OR/N network to NN/NN network Nand Nand Nand onserve ubbles! Step Step 2 Z = {[(' ')' (' ')']'}' = {(' ') + (' ')}' = (' ')' (' ')' = ( + ) ( + ) onserve ubbles! This is the hard conversion! OR/N to to / more more natural No. 3-5 Multi-Level Logic: More than Two Levels ƒ = ( + ) + ' Level Level 2 Level 3 Level 4 Original N-OR Network \ G G2 G3 G4 G5 Introduction and onservation of ubbles \ G G2 G3 G4 G5 Redrawn in terms of conventional NN Gates \ \ G G2 G3 G4 G5 No. 3-6
Multi-Level Logic: More than Two Levels Level Level 2 Level 3 Level 4 \ G G2 G3 G4 G5 Same beginning network after introduction of bubbles \ \ \ G G3 G4 G5 \ G2 inal network, redrawn in -only form No. 3-7 onversion Example (a) X Original circuit (b) X dd double bubbles at inputs X \ (c) \ X istribute bubbles some mismatches \ \ X (d) Insert inverters to fix mismatches No. 3-8
Multi-Level Logic: N-OR-Invert lock (OI) OI unction: Three stage logic N, OR, Invert Multiple gates "packaged" as a single circuit block logical concept N OR Invert Z T rue alse Z two-input two-stack No. 3-9 Multi-Level Logic: N-OR-Invert lock (OI) 2x2 OI Schematic Symbol & & + 3x2 OI Schematic Symbol & & + No. 3-2
Example: XOR implementation xor = ' + ' OI form = (? )' (' + ')' ( + ') (' + ) ( + ' ') General procedure to place in OI form: ompute the complement in Sum of Products form by circling the 's in the K-map! ƒ = (' ' + )' No. 3-2 Example: = ' + ' + ' = ' ' + ' + ' 2-input 3-stack OI gate K-map = ( + ) ( + ') ( + ') ' = (' + ) (' + ) (' + ') 2-input 3-stack OI gate No. 3-22
Example: 4-bit Equality unction Z = ( + ' ') ( + ' ') (2 2 + 2' 2') (3 3 + 3' 3') Each implemented in single 2x2 OI gate No. 3-23 Example: OI Implementation of a 4-it Equality Tester High if, Low if = = active low onservation of bubbles If all inputs are low (asserted in negative logic) then i = i, i=,...,3 Output Z asserted No. 3-24
Multi-Level Logic: Tools for Simplification Multi-Level Optimization:. actor out common sublogic (reduce fan-in, increase gate levels), subject to timing constraints 2. Map factored form onto library of gates 3. Minimize number of literals (correlates with number of wires) actored orm: sum of products of sum of products... + + 2 E 5 + 4 G + E 3 + X = ( + ' ) ( + (E + ')) + ( + E)( G) X No. 3-25 Multi-Level Logic: Tools for Simplification Operations on actored orms: ecompostion Extraction actoring Substitution Manipulate network by interactively issuing the appropriate instructions There exists no algorithm that guarantees "optimal" multi-level network will be obtained ollapsing No. 3-26
Time Response in ombinational Networks emphasis on timing behavior of circuits waveforms to visualize what is happening simulation to create these waveforms momentary change of signals at the outputs: hazards - can be useful pulse shaping circuits - can be a problem glitches: incorrect circuit operation Terms: gate delay - time for change at input to cause change at output minimum delay vs. typical/nominal delay vs. maximum delay careful designers design for the worst case! rise time - time for output to transition from low to high voltage fall time - time for output to transition from high to low voltage No. 3-27 Pulse Shaping ircuit ' = 3 gate delays remains high for three gate delays after changes from low to high is not always! No. 3-28
nother Pulse Shaping ircuit Resistor + Open Switch lose Switch Open Switch Initially undefined No. 3-29 Hazards/Glitches and How to void Them Unwanting switching at the outputs Occur because delay paths through the circuit experience different propagation delays anger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock) Usual solutions: - wait until signals are stable (by using a clock) - never, never, never use circuits with asynchronous inputs - design hazard-free circuits Suggest that first two approaches be used, but we'll tell you about hazard-free design anyway! No. 3-3
Hazards/Glitches and How to void Them Static -hazard Static -hazard Input change causes output to go from to to Input change causes output to go from to to ynamic hazards Input change causes a double change from to to to OR from to to to Kinds of Hazards No. 3-3 \ \ Glitch Example G G2 G3 \ \ input change within product term G G2 = = G3 = ' + ' \ \ G G2 G3 \ \ G G2 G3 \ \ G G2 G3 = = ( is still ) = ( is ) input change that spans product terms output changes from to to No. 3-32
Glitch Example General Strategy: add redundant terms = ' + ' becomes ' + ' + ' This eliminates -hazard? How about -hazard? Re-express in PoS form: = (' + ')( + ) Glitch present! dd term: (' + ) This expression is equivalent to the hazard-free SoP form of No. 3-33 Glitch Example Start with expression that is free of static -hazards = ' + ' + ' Work with complement: ' = ( ' + ' + ' )' = (' + ) ( + ') ( + ') = + ' + ' + ' ' + ' ' = + ' + ' covers all the adjacent 's in the K-map free of static- and static- hazards! No. 3-34
etecting Static Hazards in Multi-Level ircuits alculate transient output function variables and complements are treated as independent variables cannot use X + X' = or X X' = for simplifications Example: = + ( + ) (' + ') = + ' + ' + ' + ' 2-level form : to, covered by term, so no -hazard present : to, term goes low while term ' goes high some static hazards are present! No. 3-35 Static -hazards Solution: dd redundant terms to insure all adjacent transitions are covered by terms 2 = ' + ' + ' + + 2 's hazards in corrected in 2 No. 3-36
Static -Hazards Similar to previous case, but work with the complement of If terms of the transient output function cover all transitions, then no -hazards are present = [ + ( + ) (' + ')]' = (' + ' + ') (' ' + ) = ' ' + ' ' + ' ' + ' = ' ' + ' + ' ' = ( + ) (' + + ') ( + ' + ) -hazard free equivalent to 2 on last slide -hazard on transition from to No. 3-37 Static -Hazards 3 -Hazard orrected in 3 No. 3-38
esigning Networks for Hazard-free operation Simply place transient output function in a form that guarantees that all adjacent ones are covered by a term no term of the transient output function contains both a variable and its complement (,,,) = m(,3,5,7,8,9,2,3,4,5) = + ' + + ' + ' = (' + + ') + ( + ') (factored by distributive law, which does not introduce hazards since it does not depend on the complementarity laws for its validity) No. 3-39 ynamic Hazards \ \ \ G Slow G2 G3 G4 \ V ery slow G5 Three different paths from or ' to output =, = to =, = different delays along the paths: G slow, G4 very slow Handling dynamic hazards very complex eyond our scope No. 3-4
Elements of a ata Sheet data sheet contains all the relevant documentation that you need to use the component:. escription of unction 2. function/truth table 3. logic schematic with labeled I/Os 4. oolean expression of function in terms of I/Os 5. lternative package pint-outs 6. Internal transistor shcematics 7. Operating specifications 8. Recommended operating conditions 9. Electrical characteristics.. Switching characteristics. No. 3-4 Operating Specifications: the absolute worst-case conditions under which the component can operate or be stored. Max input volt: 7v, Temp: to 7. Recommended Operating onditions: the normal operating conditions for the supply voltage, input voltages, output currents, and temperature. V HI : min input volt recognized as a logic (2v) V IL : max input volt recognized as a logic (.8v) I OH : max current gate can supply to maintain volt of logic (-.4 m) I OL : min current gate can supply to maintain volt of logic (8 m) No. 3-42
Electrical haracteristics: voltages and currents that can be observed at the inputs and outputs. V OH : min output high volt (2.7v min, 3.4v typical) V OL : max output low volt (.4v max,.25v typical) I IH : max current into input when high (2u) I IL : max current into input when low (-.4 m) The voltages determine the noise margin:.7v margin on logic, and.4v on logic. Switching haracteristics: the typical and maximum gatdelays under specified test conditions. t PLH : delay from low to high (9ns typical, 5ns worst) t PHL : delay from high to low (ns typical, 5ns worst) No. 3-43 an-out: a given output can drive only a finite number of inputs before the output signal levels become degraded and are no longer recognized as good logic /s. To determine the fan-out examine the I OH of the driving gate. This value must exceed the sum of the I IH values of the inputs that the gate is driving. Similarly, the I OL of the gate must exceed the sum of the I IL values of the inputs to which it is connected. Example: I IH: 2u, I OH : -.4m I IL : -.4m, I OL : 8m It can drive 2 gates to logic and to logic. No. 3-44
Technology Metrics There are differences in the underlying technologies that may make one technology more attractive than another. The main technology metrics are:. Gate elay: the time delay between the changes. Om general, bipolar techs are faster than MOS (EL the fastest). 2. egree of Integration: the area required to implement a given function in the underlying tech. MOS pack much more densely than bipolar. SSI: up to gates MSI: up to gates (not important) LSI / VLSI: up to gates (MOS has advantage) No. 3-45 3. Power issipation: the power consumption and heat generated that must be dissipated. - ipolar generate more heat and consume more power - EL consume the most power - MOS, especially MOS, consume very little power 4. Noise Margin: the max volt that can be added to or subtracted from the login voltages and still have the ckt interpret the voltage as the correct logic value. - Modern TTL / MOS have good noise margins - EL has tighter noise margin 5. omponent ost: TTL, MOS, EL No. 3-46