A Cost Effective Design of Reversible Single Precision Floating Point Multiplier

International Journal of Research in Computer and Communication technology, IJRCCT, ISSN 2278-584, ol 2, Issue, January 2. Cost Effective Design of Reversible Single Precision Floating Point Multiplier S.R.Malathi, kshaya enugopal, Pavithra Sarathy Department of Computer Science and Engineering Sri enkateswara College of Engineering Chennai, Tamilnadu, India malathiraj@svce.ac.in, akshusvg@gmail.com, pavi.@gmail.com bstract The emerging computing technologies like quantum computing, optical computing, low power computing etc. make use of reversible logic. lso applications like image processing and signal processing make use of floating point (FP) multiplications as the major operations. In this paper we propose the design of a low power, cost effective reversible floating point multiplier for such applications. The proposed design is comparable with the reversible FP multipliers discussed in the literature so far. The proposed design using TS gates is cost effective in terms of the number of quantum gates and the garbage outputs compared to the existing ones. Since it has been proved that the 4 x 4 TS gate [4] can work singly as a reversible full adder with only two garbage outputs, it is an optimal reversible full adder with universal functionalities. Hence the proposed design yields an optimal floating point multiplier in terms of quantum cost and garbage outputs. The proposed design has three stages - partial product generation, compression using 4:2 TS compressors and the final stage which consists of TS adders to generate the resultant product. The proposed design of 2 x 2 FP multiplier is illustrated using TS gates which show that the number of garbage outputs in each 8X8 multiplier is reduced significantly. Keywords Reversible floating point multiplier, Reversible circuit design, Quantum computation. I. INTRODUCTION Reversible logic circuits are of interests in applications like low power CMOS design, optical information processing, DN computing, bioinformatics, quantum computing and nanotechnology where power minimization is one of the important criterion. s demonstrated by R. Landauer in the early 96s, irreversible hardware computation, regardless of its realization technique, results in energy dissipation due to the information loss []. It is proved that the loss of each one of information dissipates at least KTln2 joules of energy (heat), where K is the oltzmann s constant and T is the absolute temperature at which operation is performed []. In 97, C. H. ennett [2] concluded that no energy would dissipate from a system as long as the system was able to return to its initial state from its final state regardless of what occurred in between. One highly promising computing technology is the employment of reversible logic operations, which do not erase information and thus dissipate (virtually) zero heat. lthough the amount of heat dissipation at room temperature is small, it cannot be neglected in some applications (e.g., quantum circuit design). Reversible logic is the logic supporting the process of running the system in the backward direction. The logical operations can be run backwards by cascading a reversible logic gate with its dual. Reversible circuits are also called lossless circuits, as there is neither energy loss nor information loss. In the design of reversible circuits two restrictions are to be considered: () Fan-out is not permitted, (2) Feed back loops are not permitted. Due to these restrictions, synthesis of reversible circuits can be carried out from the inputs towards the outputs and vice versa []. From the point of view of reversible circuit design, there are three parameters Quantum Cost, arbage Output and the Depth of the circuit that determine the complexity and performance of reversible circuits [4]: Quantum Cost (QC) is the number of or 2 2 reversible gates which are used in the circuit. arbage Outputs (O) is the number of unused outputs which are added in order to make the circuit reversible. Depth of the circuit is the number of or 2 2 reversible gates which are in the longest path from input to output. Reduction of these three parameters is the bulk of the work in reversible circuit design. However, minimizing all these parameters together is not easy. In this paper, we aim to design a reversible single precision floating point multiplier with the minimized number of QC and O of the circuit with respect to its previous counterparts. In the existing literatures [5], [6], [7], [8] the multiplier circuits that are proposed are for fixed point numbers. In [6] Page 26

the design of a reversible floating-point adder is proposed that closely follows the IEEE754 specification for binary floatingpoint arithmetic. In [9] Single Precision FP multiplier is implemented using the Feynman gate, the Peres gate, the Toffoli gate, the Fredkin gate and the Reversible Full dder (RF) gate. It is well known that a single TS gate is capable of functioning as a reversible full adder. In this paper the proposed multiplier circuit is designed mainly using TS gates while the initial partial product generation is done using Fredkin gates as in [9]. ecause of the use of TS gate in the design, the proposed design is optimized in terms of garbage output and the number of gates. Rest of the paper is organized as follows. Section II provides an overview of IEEE single precision floating point number representation. Section III provides details about the basic and necessary reversible logic gates used in the proposed design. Section I provides the details about the design of the proposed reversible 8x8 multiplier. Section describes the proposed Floating Point (FP) Multiplier and a comparison of the multiplier with the existing work. Section I concludes the work. II. IEEE SINLE PRECISION FLOTIN POINT (FP) NUMER REPRESENTTION IEEE Single Precision Floating Point numbers [5] is a 2 representation which has three basic components: the Sign, the Exponent, and the Mantissa. The sign S is a single digit where positive number is denoted by and negative number by. Flipping the value of this flips the sign of the number. The exponent field E is 8 digits which need to represent both positive and negative exponents. To do this, a bias is added to the actual exponent and stored as exponent. For IEEE singleprecision floats, this bias value is 27. Thus, an exponent of zero means storing 27 in the exponent field. stored value of E indicates an actual exponent of (E-27). Exponents of -27 (all s) and +28 (all s) are reserved for special numbers. The mantissa, also known as the significant, is 2 digits which represents the precision s of the number. It is composed of an implicit leading non zero and the fraction s. In base two, the only possible non-zero digit is which is not represented explicitly. Thus the mantissa has effectively 24 s of resolution, by way of 2 fraction s. The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa), and de normalized numbers. THE LYOUT FOR SINLE (2 IT) PRECISION FLOTIN POINT LUE TLE I. Sign Single Precision [] Exponen t [-2] 8 s Fractio n [22-] 2 s III. REERSILE LOIC TES USED This section describes the important reversible gates used in this work. The Feynman gate, the Fredkin ate and the TS gate are the important reversible gates used in the design. The functionality and the quantum implementation of the Feynman gate, the Fredkin gate, and the TS gate are shown in Figure.. The implementation of TS gate as full adder and Fredkin gate as partial product generator is shown in Figure.2. The partial products generation for 8x8 multiplier is shown in Figure.. It can be seen from Table 2 that the number of garbage outputs per gate is minimum for TS gates than its counter parts. I. PROPOSED DESIN FOR 8X8 REERSILE MULTIPLIER In the design of single precision floating point multiplier, the quantum cost is mainly determined by the 24x24 mantissa multiplier unit. The 24x24 multiplier is implemented using nine 8x8 multiplier subunits. There are two steps for generating the product. The first step is to generate partial products and the next is to add all the partial products to obtain the final product. The proposed design for the 8X8 multiplier follows the Wallace tree multiplier architecture [9]. Here we have implemented partial product generation using Fredkin gates and TS gates to add the partial products as shown in Figure. and Figure. 5 respectively. The 8 x 8 multiplier uses 4:2 compressors and full adders [4], all implemented using TS gates to have uniformity in the type of gates. 4:2-compressor has 5 inputs and outputs. Four inputs are from position j and one input is from position j-. The output has a sum at position j and two carry s at position j+, which are represented as and in Figure. 5. Each 4:2-compressor has 2 TS gates and produces 4 garbage outputs. In Fig. 4 the group of partial products that are fed as inputs to 4:2-compressors and full adders are encircled. In that level-4 is implemented using a reversible carry propagate adder. In Table the number of gates used, garbage output produced and the quantum cost for the proposed 8 x 8 multiplier is listed along with its counterparts. TLE II. COMPRISON ETWEEN RIOUS FULL DDER CIRCUITS Existing Full dders Number of ates Number of arbage Outputs Unit Delay TS gate [4] 2 ias Full dder in [] 27 Full dders [], [2] 2 Full dders [] 5 5 5 Page 27

COST OF 8 X 8 REERSILE MULTIPLIERS TLE III.. PROPOSED REERSILE FLOTIN POINT MULTIPLIER Reversible 8x8 multiplier Number of ates Quantum Cost arbage Outputs In this section the design of various units used in the design of the single precision floating point multiplier are described. Proposed using TS Existing Circuit [9] Existing Circuit [5] 56 54 2 6 65 29 6 86. Proposed Design for the 24x24 Multiplier The 24x24 mantissa multiplier includes the implicit single along with the 2 trailing s in the multiplication. The 24 s of each operand are decomposed into three 8 vectors as shown Figure. 4 and nine 8x8 multipliers that was discussed in the previous section is used to implement the 24x24 mantissa multiplier. The 44 partial products generated by the nine 8x8 multipliers are then suitably aligned according to their positional weights and added using 4:2-TS compressors and TS adders to get the resultant 48 product. (a) Feynman ate: QC = + + C + + D Y 7 (b) Feynman ate: QC = Y Y + Fr C X7Y7 X7Y Fr X7 Fr X7Y (b) Fredkin ate: QC = 5 X Figure. The various reversible gates (a), (b), (c) used in the design and their quantum cost (QC). Cin = TS = XY 24 Mantissa- 24 Mantissa-2 H H H M MH (b) Figure. 2 (a)ts gate as a full adder and (b)fredkin gate as a partial product generator [4] = Fr Fr XY Fr X Figure. Partial Products eneration for the 8 x 8 Multiplier (a) Fr XY7 H H M M H L M L MM LM LH L L LL 48 Mantissa Product Figure. 4 Partitioning and Multiplication of the 24 Mantissa Page 28

X7 Y7 C C C4 X6 Y6 X5 Y5 X4 Y4 X Y X2 Y2 X Y X Y 7 6 5 4 2 7 6 5 4 2 C7 C6 C5 C4 C C2 C C D7 D6 D5 D4 D D2 D D E7 E6 E5 E4 E E2 E E F7 F6 F5 F4 F F2 F F 7 6 5 4 2 H7 H6 H5 H4 H H2 H H H7 S S2 S S S S C C2 S S S S S29 S28 C C29 C28 C27 S4 C42 S42 C4 S4 C4 S4 C9 S27 S9 C8 S9 S8 S7 H2 S6 S5 C6 C5 C4 S26 S8 C7 S25 S7 C6 S24 S6 C5 S6 S4 S2 S5 C4 S5 S4 S S2 C2 C F S22 S2 S2 C2 C2 C9 S4 C S C2 S2 S9 S9 S S Figure. 5 Partial product summation stages in the 8 x 8 multiplier. Proposed Design for Normalization and Rounding off unit The 48 product is normalized according to the IEEE754 standard by adjusting the exponent value until we get a before the binary point. In the product of two normalized binary mantissa the most significand two s indicating the integer part, can be any of the three combinations, or. If the most significand first is and second is one then the resultant product mantissa is already in the normalized form and the s to the right of the binary points (i.e) the 45th onwards is the product. Where as, if the most significand first is, then the mantissa has to be shifted to the right to make the binary point placed to the right of the nonzero MS and correspondingly the exponent has to be incremented by one. The rounding-off of the 48 mantissa product to 2 resultant mantissa is done by simple truncation. The shifting of mantissa for normalization and truncation of s for roundingoff is done using 2 Fredkin gates as shown in Figure. 6 C. Design for Sign and Exponent Unit D. functional erification & Quantum Cost The design of various units proposed in this paper was functionally verified which includes the 8x8 Multiplier, the 24x24 Multiplier, the Normalization and Rounding off unit and the Exponent unit. The various units of the irreversible (conventional) and reversible floating point multiplier were simulated using erilog HDL in XilinxISE 9.i and the outputs were checked for equivalence for same set of inputs. Thus functional equivalence was verified. The simulated output of 2- reversible single_precision floating_point_multiplier, for a typical test data input is shown in Figure 8. The comparison of the proposed reversible single precision multiplier with the one discussed in [9] is shown in Table 4. It can be seen that there is a significant number of reduction in the quantum cost and garbage output. The overall Quantum Cost of the proposed FP multiplier is reduced by 6 and the number of garbage outputs by 95. For any two normalized floating point numbers and their product is defined as Where, the fields S, E and M refer to the sign, exponent and mantissa of the operands and. The sign is computed by XOR function which is implemented using single Feynman gate. The exponents are added along with the biasing of -27 using reversible carry propagate adders in two stages. Figure. 7 shows the reversible carry propagate adder implemented using TS gates. Page 29

TLE I. COST OF THE REERSILE FLOTIN POINT MULTIPLIER SINLE PRECISION TS Existing System [9] 24X24 Mantissa Multiplier TS QC O QC O 659 87 654 88 28 47 5 C Proposed System 2 2 C TS 7 Normalization unit 7 2 C2 TS Rounding unit 25 25 Sign calculation Exponent calculation 82 44 2 Total 6957 49 6794 296 C7 S7 S2 S S 8 IT SUM Figure. 7 Exponent Unit with 8-it Reversible Carry Propagate dder Circuit (RCP) QC Quantum Cost; O arbage Output 48 Mantissa Product MS 47th 46th 46th Fr 2rd 45th th 45th th 45 44 2rd 22nd Fr 2 LS 24th th 24th Fr 2 rd 2 2st th 2 Normalized and Rounded off Mantissa Result Figure. 6 Normalization and Rounding off Unit using 2 (2:) Mux Figure. 8 Sample output from the simulated 2- Reversible Single Precision Floating Point Multiplier Page

I. CONCLUSION n efficient design of single precision floating point multiplier is presented in this paper. s it is well known that the TS gate can singly act as full adder and two TS gates can be used as reversible 4:2-compressor, we proposed the design using TS gates. The proposed normalization and rounding unit uses significantly less number of gates compared to its counterpart in [9]. lso to maintain uniformity only two types of gates are used in the proposed design and still results in significantly less number of quantum cost and garbage outputs as compared to the existing one. [] [2] [] [4] [5] [6] [7] [8] [9] [] [] [2] REFERENCES Landauer, R., 96. Irreversibility and heat generation in the computing process, IM J.Research and Development, 5 (): 8-9. ennett, C.H., 97. Logical reversibility of computation, IM J. Research and Development,7: 525-52. P. upta,. grawal, N. K. Jha, n lgorithm for Synthesis of Reversible Logic Circuits, IEEE Transactions on Computer-ided Design of Integrated Circuits and Systems, ol. 25, No., pp. 27-2, November 26. H. Thapliyal and M.. Srinivas, Novel reversible 'TS' gate and its application for designing components of primitive/reversible quantum LU, Proc. the 5th IEEE Intl. Conf. on Information, Communications and Signal Processing, angkok, Thailand, Dec 6-9, 25, pp. 425429. H. Thapliyal and M.. Shrinivas, Novel reversible multiplier architecture using reversible TS gate, IEEE Int. Conf.Computer Systems and pplications, pp., 26. M. Shams, M. Haghparast, K. Navi, Novel reversible multiplier circuit in nanotechnology, World ppl. Sci. J., vol.,pp. 86-8, 28. M. Haghparast, S.J. Jassbi, K. Navi and O. Hashemipour, Design of a novel reversible multiplier circuit using HN gate in nanotechnology, World ppl. Sci. J., vol., pp. 974-978, 28. M.S. Islam, M.M. Rahman, Z. egum and M.Z. Hafiz, Low cost quantum realization of reversible multiplier circuit, Information technology journal, vol. 8, pp. 282, 29. M. Nachtigal, H. Thapliyal, N. Ranganathan, Design of a reversible single precision floating point multiplier based on operand decomposition, 2 th IEEE Conference on Nanotechnology, pp.2-27, 2 Hafiz Md. Hasan abu, Md. Rafiqul Islam, Syed Mostahed li Chowdhury and hsan Raja Chowdhury, Reversible Logic Synthesis for Minimization of Full dder Circuit, Proceedings of the EuroMicro Symposium on Digital System Design(DSD ), -5September 2, elek- ntalya, Turkey,pp-5-54. Hafiz Md. Hasan abu, Md. Rafiqul Islam, Syed Mostahed li Chowdhury and hsan Raja Chowdhury," Synthesis of Full-dder Circuit Using Reversible Logic",Proceedings 7th International Conference on LSI Design (LSI Design 24), January 24, Mumbai, India,pp-757-76. J.W. ruce, M.. Thornton,L. Shivakumariah, P.S.Kokate and X.Li, "Efficient dder Circuits ased on a Conservative Logic ate", Proceedings of the IEEE Computer Society nnual Symposium on [] [4] [5] [6] LSI(ISLSI'2),pril 22, Pittsburgh, P, US, pp8-88.. anerjee,. Pathak, n algorithm for minimization of quantum cost, quant-ph 9.229v2, pp. -9, 27. "IEEE Standard for Floating-Point rithmetic," IEEE Std 754-28, pp.-58, ug. 29 28 doi:.9/ieeestd.28.4695 M.Jenath,.Nagarajan, FP Implementation Of Reversible Floating Point Multiplier, International Journal of Soft Computing and Engineering (IJSCE), olume-2, Issue-, pp. 48-44, March 22. M. Nachtigal, H. Thapliyal, N. Ranganathan, Design of a Reversible Floating Point dder rchitechture, 2 th IEEE Conference on Nanotechnology, pp.45-456, 2 Page